CN101728436A - Element of thin film transistor and manufacturing method thereof - Google Patents
Element of thin film transistor and manufacturing method thereof Download PDFInfo
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- CN101728436A CN101728436A CN200910251399A CN200910251399A CN101728436A CN 101728436 A CN101728436 A CN 101728436A CN 200910251399 A CN200910251399 A CN 200910251399A CN 200910251399 A CN200910251399 A CN 200910251399A CN 101728436 A CN101728436 A CN 101728436A
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Abstract
The invention provides an element of a thin film transistor and a manufacturing method thereof. The element of thin film transistor comprises a crystallized semiconductor layer and a pattern heavily doped semiconductor layer. The pattern heavily doped semiconductor layer is formed by using a deposition process and comprises a first heavily doped semiconductor layer and a second heavily doped semiconductor layer. The first heavily doped semiconductor layer coats the surface of the first side of the crystallized semiconductor layer and part of the upper surface connected with the surface of the first side. The second heavily doped semiconductor layer coats the surface of the second side of the crystallized semiconductor layer and part of the the upper surface connected with the surface of the second side.
Description
Technical field
The present invention relates to a kind of thin-film transistor element and preparation method thereof, especially refer to a kind of thin-film transistor element, it has the side surface of coating crystalline semiconductor layer and the patterning severe doping semiconductor layer of part upper surface, and the method for making above-mentioned thin-film transistor element.
Background technology
Amorphous silicon (amorphous silicon) film is used on the flat display apparatus at present widely, as the semiconductor layer (the general title uses amorphous silicon to be the amorphous silicon film transistor element as the thin-film transistor element of semiconductor layer) of thin-film transistor element.Yet low excessively electron mobility, low drive current and element reliability are not good, have caused the restriction of amorphous silicon film transistor element on using.For example, amorphous silicon membrane can produce irradiation attenuating effect (Staebler-Wronski effect) under the irradiation of light, and makes that element stability is not good and can't meet the specification requirement of high-order liquid crystal indicator.Moreover when being applied in organic electroluminescence display device, the amorphous silicon film transistor element has the problem of deterioration after long-time the use, can make that the magnitude of current by organic luminous layer descends, and then influence luminous brightness.The use polysilicon membrane except higher electron mobility is arranged, also can improve the situation of transistor deterioration as semiconductor layer.
The heavy doping drain/source layer (also being called ohmic contact layer) of the polycrystalline SiTFT on the known display panel mainly utilizes implanting ions technology to be made, but being subject to implanting ions board size only develops to small size substrate (substrates before 4.5 generations or 4 generations), the implanting ions board of present no large-size substrate, and use the technology of implanting ions technology and standard amorphous silicon film transistor element also incompatible, and make the technology of polycrystalline SiTFT element be restricted.
Summary of the invention
One of the object of the invention is to provide a kind of thin-film transistor element and preparation method thereof, to solve the difficult problem that known technology was faced.
A preferred embodiment of the present invention provides a kind of thin-film transistor element, comprises a substrate, a crystalline semiconductor layer, a patterning severe doping semiconductor layer, one source pole and a drain electrode, a gate insulator and a grid.Crystalline semiconductor layer is arranged on the substrate, and wherein crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface.Patterning severe doping semiconductor layer is arranged on crystalline semiconductor layer and the substrate, patterning severe doping semiconductor layer comprises one first severe doping semiconductor layer and one second severe doping semiconductor layer, wherein the first severe doping semiconductor layer coats first side surface of crystalline semiconductor layer and the part upper surface that is connected with first side surface, and the second severe doping semiconductor layer coats second side surface of crystalline semiconductor layer and the part upper surface that is connected with second side surface.Source electrode is arranged at respectively on the first severe doping semiconductor layer and the second severe doping semiconductor layer with drain electrode.Gate insulator is arranged on source electrode, drain electrode and the crystalline semiconductor layer.Grid is arranged on the gate insulator.
Another preferred embodiment of the present invention provides a kind of method of making thin-film transistor element, comprises the following steps.One substrate at first is provided, and on substrate, forms a crystalline semiconductor layer.On crystalline semiconductor layer and substrate, deposit a severe doping semiconductor layer subsequently, and patterning severe doping semiconductor layer is to form one first severe doping semiconductor layer and one second severe doping semiconductor layer.Then on the first severe doping semiconductor layer and the second severe doping semiconductor layer, form an one source pole and a drain electrode respectively.
Another preferred embodiment of the present invention provides a kind of method of making thin-film transistor element, comprises the following steps.One substrate at first is provided, and on substrate, forms a crystalline semiconductor layer.On crystalline semiconductor layer and substrate, deposit a severe doping semiconductor layer subsequently.Then on the severe doping semiconductor layer, form a conductive layer.Patterned conductive layer drains to form one source pole and afterwards, and patterning severe doping semiconductor layer is to form one first severe doping semiconductor layer and one second severe doping semiconductor layer.
First side surface of the crystalline semiconductor layer of thin-film transistor element of the present invention and second side surface are coated by the first severe doping semiconductor layer and the second severe doping semiconductor layer respectively, but and because severe doping semiconductor layer blocking hole conduction, and can avoid the problem of leakage current to give birth to.In addition, the present invention makes the method for thin-film transistor element and utilizes depositing operation to form the severe doping semiconductor layer, but not utilize implanting ions technology to form the severe doping semiconductor layer, therefore can technology can be not restricted because of substrate size, and depositing operation can be integrated in the standard technology of amorphous silicon film transistor element.
Description of drawings
Fig. 1 to Fig. 4 has illustrated the method schematic diagram of the making thin-film transistor element of a preferred embodiment of the present invention;
Fig. 5 to Fig. 8 has illustrated the method schematic diagram of the making thin-film transistor element of another preferred embodiment of the present invention.
Wherein, Reference numeral
10 substrates, 12 crystalline semiconductor layer
121 upper surfaces, 122 first side surfaces
123 second side surfaces, 14 severe doping semiconductor layers
141 first severe doping semiconductor layers, 142 second severe doping semiconductor layers
16 conductive layer 16S source electrodes
20 grids, 22 thin-film transistor elements
30 substrates, 32 crystalline semiconductor layer
321 upper surfaces, 322 first side surfaces
323 second side surfaces, 34 severe doping semiconductor layers
36 conductive layer 36S source electrodes
40 grids, 42 thin-film transistor elements
Embodiment
For making those skilled in the art can further understand the present invention, hereinafter the spy enumerates preferred embodiment of the present invention, and cooperates appended accompanying drawing, describe in detail constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 1 to Fig. 4.Fig. 1 to Fig. 4 has illustrated the method schematic diagram of the making thin-film transistor element of a preferred embodiment of the present invention.As shown in Figure 1, at first provide a substrate 10, wherein substrate 10 can be for example glass substrate of a transparency carrier, but not can be other various types of substrates as limit, for example, and plastic substrate or wafer.Then on substrate 10, form a crystalline semiconductor layer (crystallinesemiconductor layer) 12.Before forming crystalline semiconductor layer 12, optionally on substrate 10, form a resilient coating (figure does not show).The crystalline semiconductor layer 12 of present embodiment is selected a polysilicon semiconductor layer (polycrystalline silicon semiconductor layer) for use, but the material of crystalline semiconductor layer 12 is not limited to silicon, and can be other semi-conducting material, and its crystal form also is not limited to polycrystalline, and can be other crystal form, for example, crystallite.In the present embodiment, the making of crystalline semiconductor layer 12 comprises the following steps.On substrate 10, form a noncrystal semiconductor layer, for example an amorphous silicon semiconductor layer (amorphous siliconsemiconductor layer); Carry out a upgrading technology, change noncrystal semiconductor layer into crystalline semiconductor layer 12 (being polysilicon semiconductor layer) at this; And crystalline semiconductor layer 12 carried out patterning, for example utilize photoetching and etching technique.In the present embodiment, modifying process select for use a solid state crystallization (solid phasecrystallization, SPC) technology, between about 600 ℃ to 700 ℃ high temperature under change amorphous silicon into polysilicon.Because under this high temperature, substrate 10 is unavoidablely can Yin Wendu too high and produce and shrink, therefore the thin-film transistor element of present embodiment is top gate type (top-gate type) thin-film transistor element, that is after the solid state crystallization technology of finishing high temperature has formed polysilicon semiconductor layer, just make source/drain and grid in regular turn, therefore can not produce the inaccurate problem of contraposition.What deserves to be explained is in the present embodiment, modifying process is not limited to select for use solid state crystallization technology, and can select other various modifying process for use, rapid hot technics (rapid thermal process for example, RTP), boiler tube (furnace) heating process, quasi-molecule laser annealing (excimerlaser annealing, ELA) technology, crystallization inducing metal (metal-induced crystallization, MIC) technology, metal inducement side crystallization (metal-induced lateral crystallization, MILC) technology, gradualness side crystallization (sequential lateral solidification, SLS) (continuousgrain silicon CGS) waits other modifying process in technology or continuous silicone crystallization.In addition, the method for present embodiment also is not limited to form crystalline semiconductor layer 12 by modifying process, for example also can directly form crystalline semiconductor layer 12 on substrate 10, and crystalline semiconductor layer 12 is carried out patterning.After patterning, crystalline semiconductor layer 12 comprises a upper surface 121, one first side surface 122 and one second side surface 123.
As shown in Figure 2, then on crystalline semiconductor layer 12 and substrate 10, deposit a severe doping semiconductor layer 14 (a for example N type severe doping semiconductor layer), and patterning severe doping semiconductor layer 14 is to form one first severe doping semiconductor layer 141 and one second severe doping semiconductor layer 142, wherein severe doping semiconductor layer 14 for example can utilize chemical vapor deposition method to form, and the step of patterning severe doping semiconductor layer 14 can utilize for example photoetching with etching technique and cooperate mask to be reached.The first severe doping semiconductor layer 141 and the second severe doping semiconductor layer 142 be the both sides of corresponding crystalline semiconductor layer 12 respectively, and the first severe doping semiconductor layer 141 coats first side surface 122 of crystalline semiconductor layer 12 and the part upper surface 121 that is connected with first side surface 122, and the second severe doping semiconductor layer 142 coats second side surface 123 of crystalline semiconductor layer 12 and the part upper surface 121 that is connected with second side surface 123.
As shown in Figure 3, on substrate 10, crystalline semiconductor layer 12 and severe doping semiconductor layer 14, form a conductive layer 16 subsequently, a metal level for example, and utilize for example photoetching with etching technique and cooperate mask pattern conductive layer 16 is to form one source pole 16S and a 16D that drains.In the present embodiment, source electrode 16S is positioned on the first severe doping semiconductor layer 141 substantially, and does not contact with crystalline semiconductor layer 12, and source electrode 16S protrudes in the first severe doping semiconductor layer 141 and part covered substrate 10 in addition; Drain electrode 16D is positioned on the second severe doping semiconductor layer 142 substantially, and does not contact with crystalline semiconductor layer 12, and the 16D that drains in addition protrudes in the second severe doping semiconductor layer 142 and part covered substrate 10.As shown in Figure 3, first side surface 122 of crystalline semiconductor layer 12 and second side surface 123 are coated by the first severe doping semiconductor layer 141 and the second severe doping semiconductor layer 142 respectively, therefore be provided with the first severe doping semiconductor layer 141 between first side surface 122 of source electrode 16S and crystalline semiconductor layer 12, and be provided with the second severe doping semiconductor layer 142 between second side surface 123 of drain electrode 16D and crystalline semiconductor layer 12, but the first severe doping semiconductor layer 141 and the second severe doping semiconductor layer, 142 blocking holes conduction whereby, and can avoid producing leakage current (current leakage) between source electrode 16S/ drain electrode 16D and the crystalline semiconductor layer 12.
As shown in Figure 4, then go up with drain electrode 16D and form a gate insulator 18 in substrate 10, crystalline semiconductor layer 12, source electrode 16S, on gate insulator 18, form a grid 20 corresponding crystalline semiconductor layer 12 again, to form the thin-film transistor element 22 of present embodiment.
Please refer to Fig. 5 to Fig. 8.Fig. 5 to Fig. 8 has illustrated the method schematic diagram of the making thin-film transistor element of another preferred embodiment of the present invention, wherein be simplified illustration and the different place of being convenient to each embodiment of comparison, present embodiment mainly only describes at different place, and no longer adds to give unnecessary details to existing together mutually.As shown in Figure 5, at first provide a substrate 30.Then on substrate 30, form a crystalline semiconductor layer 32, and crystalline semiconductor layer 32 is carried out patterning.Crystalline semiconductor layer 32 comprises a upper surface 321, one first side surface 322 and one second side surface 323.
As shown in Figure 6, then on crystalline semiconductor layer 32 and substrate 30, form a severe doping semiconductor layer 34 in regular turn, an and conductive layer 36, wherein severe doping semiconductor layer 34 can utilize for example chemical vapor deposition method formation, and conductive layer 36 can be for example a metal level or the good conductive layer of other conductivity.
As shown in Figure 7, patterning severe doping semiconductor layer 34 to be forming one first severe doping semiconductor layer 341 and one second severe doping semiconductor layer 342, and patterned conductive layer 36 is to form one source pole 36S and a 36D that drains.In the present embodiment, severe doping semiconductor layer 34 utilizes same mask to carry out patterning with conductive layer 36, therefore have the advantage of work simplification, but not as limit, for example severe doping semiconductor layer 34 also can utilize different masks or alternate manner to carry out patterning respectively with conductive layer 36.The first severe doping semiconductor layer 341 and the second severe doping semiconductor layer 342 be the both sides of corresponding crystalline semiconductor layer 32 respectively, wherein the first severe doping semiconductor layer 341 coats first side surface 322 of crystalline semiconductor layer 32 and the part upper surface 321 that is connected with first side surface 322, and the substrate 30 of the first severe doping semiconductor layer, 341 other cover parts; The second severe doping semiconductor layer 342 coats second side surface 323 of crystalline semiconductor layer 32 and the part upper surface 321 that is connected with second side surface 323, and the substrate 30 of the second severe doping semiconductor layer, 342 other cover parts.In addition in the present embodiment, the edge of source electrode 36S substantially with the justified margin of the first severe doping semiconductor layer 341, and the edge of drain electrode 36D substantially with the justified margin of the second severe doping semiconductor layer 342.As shown in Figure 7, first side surface 322 of crystalline semiconductor layer 32 and second side surface 323 are coated by the first severe doping semiconductor layer 341 and the second severe doping semiconductor layer 342 respectively, therefore be provided with the first severe doping semiconductor layer 341 between first side surface 322 of source electrode 36S and crystalline semiconductor layer 32, and be provided with the second severe doping semiconductor layer 342 between second side surface 323 of drain electrode 36D and crystalline semiconductor layer 32, but the first severe doping semiconductor layer 341 and the second severe doping semiconductor layer, 342 blocking holes conduct whereby, and can avoid the problem of leakage current.
As shown in Figure 8, then go up with drain electrode 36D and form a gate insulator 38 in substrate 30, crystalline semiconductor layer 32, source electrode 36S, on gate insulator 38, form a grid 40 corresponding crystalline semiconductor layer 32 again, to form the thin-film transistor element 42 of present embodiment.
In sum, first side surface of the crystalline semiconductor layer of thin-film transistor element of the present invention and second side surface are coated by the first severe doping semiconductor layer and the second severe doping semiconductor layer respectively, but and because severe doping semiconductor layer blocking hole conduction, and can avoid the problem of leakage current to give birth to.In addition, the present invention makes the method for thin-film transistor element and utilizes chemical deposition process to form the severe doping semiconductor layer, but not utilize implanting ions technology to form the severe doping semiconductor layer, therefore technology can be not restricted because of substrate size, and chemical deposition process can be integrated in the standard technology of amorphous silicon film transistor element.In addition, thin-film transistor element of the present invention is the top gate type thin film transistor element, therefore forms under the situation of crystal silicon semiconductor layer in the higher Pignus pignoris technology of serviceability temperature, also can not produce the inaccurate problem of contraposition.Moreover, thin-film transistor element of the present invention uses the crystal silicon semiconductor layer as passage, so have high electron mobility, high drive current and with the characteristic of high element reliability, therefore can be applicable on the products such as high-order liquid crystal indicator or organic electroluminescence display device.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (19)
1. a thin-film transistor element is characterized in that, comprising:
One substrate;
One crystalline semiconductor layer is arranged on this substrate, and wherein this crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface;
One patterning severe doping semiconductor layer, be arranged on this crystalline semiconductor layer and this substrate, this patterning severe doping semiconductor layer comprises one first severe doping semiconductor layer and one second severe doping semiconductor layer, wherein this first severe doping semiconductor layer coats this first side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this first side surface, and this second severe doping semiconductor layer coats this second side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this second side surface; And
An one source pole and a drain electrode are arranged at respectively on this first severe doping semiconductor layer and this second severe doping semiconductor layer;
One gate insulator is arranged on this source electrode, this drain electrode and this crystalline semiconductor layer; And
One grid is arranged on this gate insulator.
2. thin-film transistor element according to claim 1 is characterized in that this crystalline semiconductor layer comprises a polysilicon semiconductor layer.
3. thin-film transistor element according to claim 1 is characterized in that, this first severe doping semiconductor layer is this substrate of cover part in addition, and this second severe doping semiconductor layer this substrate of cover part in addition.
4. thin-film transistor element according to claim 3 is characterized in that, the edge of this source electrode substantially with the justified margin of this first severe doping semiconductor layer, and edge that should drain electrode substantially with the justified margin of this second severe doping semiconductor layer.
5. thin-film transistor element according to claim 1 is characterized in that, this source electrode protrudes in this first severe doping semiconductor layer and this substrate of cover part, and this drain electrode protrudes in this second severe doping semiconductor layer and this substrate of cover part.
6. a method of making thin-film transistor element is characterized in that, comprising:
One substrate is provided;
On this substrate, form a crystalline semiconductor layer;
Deposition one severe doping semiconductor layer on this crystalline semiconductor layer and this substrate, and this severe doping semiconductor layer of patterning is to form one first severe doping semiconductor layer and one second severe doping semiconductor layer; And
On this first severe doping semiconductor layer and this second severe doping semiconductor layer, form an one source pole and a drain electrode respectively.
7. the method for making thin-film transistor element according to claim 6 is characterized in that, this crystalline semiconductor layer comprises a polysilicon semiconductor layer.
8. the method for making thin-film transistor element according to claim 6, it is characterized in that, this crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface, this first severe doping semiconductor layer coats this first side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this first side surface, and this second severe doping semiconductor layer coats this second side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this second side surface.
9. the method for making thin-film transistor element according to claim 8 is characterized in that, this first severe doping semiconductor layer is this substrate of cover part in addition, and this second severe doping semiconductor layer this substrate of cover part in addition.
10. the method for making thin-film transistor element according to claim 9, it is characterized in that, the edge of this source electrode substantially with the justified margin of this first severe doping semiconductor layer, and edge that should drain electrode substantially with the justified margin of this second severe doping semiconductor layer.
11. the method for making thin-film transistor element according to claim 8, it is characterized in that, this source electrode protrudes in this first severe doping semiconductor layer and this substrate of cover part, and this drain electrode protrudes in this second severe doping semiconductor layer and this substrate of cover part.
12. the method for making thin-film transistor element according to claim 6 is characterized in that, other is included in and forms a gate insulator and a grid in this crystalline semiconductor layer, this source electrode and this drain electrode in regular turn.
13. a method of making thin-film transistor element is characterized in that, comprising:
One substrate is provided;
On this substrate, form a crystalline semiconductor layer;
Deposition one severe doping semiconductor layer on this crystalline semiconductor layer and this substrate;
On this severe doping semiconductor layer, form a conductive layer;
This conductive layer of patterning drains to form one source pole and, and this severe doping semiconductor layer of patterning is to form one first severe doping semiconductor layer and one second severe doping semiconductor layer.
14. the method for making thin-film transistor element according to claim 13 is characterized in that, this source electrode, this drain electrode, this first severe doping semiconductor layer and this second severe doping semiconductor layer utilize same mask to carry out patterning.
15. the method for making thin-film transistor element according to claim 13 is characterized in that, this crystalline semiconductor layer comprises a polysilicon semiconductor layer.
16. the method for making thin-film transistor element according to claim 13, it is characterized in that, this crystalline semiconductor layer comprises a upper surface, one first side surface and one second side surface, this first severe doping semiconductor layer coats this first side surface of this crystalline semiconductor layer and this upper surface of part that is connected with this first side surface, and this second side surface of this this crystalline semiconductor layer of second severe doping semiconductor layer and this upper surface of part of being connected with this second side surface.
17. the method for making thin-film transistor element according to claim 16 is characterized in that, this first severe doping semiconductor layer is this substrate of cover part in addition, and this second severe doping semiconductor layer this substrate of cover part in addition.
18. the method for making thin-film transistor element according to claim 17, it is characterized in that, the edge of this source electrode substantially with the justified margin of this first severe doping semiconductor layer, and edge that should drain electrode substantially with the justified margin of this second severe doping semiconductor layer.
19. the method for making thin-film transistor element according to claim 13, it is characterized in that, this source electrode protrudes in this first severe doping semiconductor layer and this substrate of cover part, and this drain electrode protrudes in this second severe doping semiconductor layer and this substrate of cover part.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102645799A (en) * | 2011-03-29 | 2012-08-22 | 京东方科技集团股份有限公司 | Liquid crystal display device, array substrate and color-film substrate as well as manufacturing methods thereof |
| US8415672B2 (en) | 2010-08-30 | 2013-04-09 | Au Optronics Corporation | Transistor with etching stop layer and manufacturing method thereof |
| WO2018166411A1 (en) * | 2017-03-17 | 2018-09-20 | 京东方科技集团股份有限公司 | Thin film transistor and array substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917199A (en) * | 1998-05-15 | 1999-06-29 | Ois Optical Imaging Systems, Inc. | Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same |
| CN1624933A (en) * | 2004-12-21 | 2005-06-08 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN101127366A (en) * | 2006-08-18 | 2008-02-20 | 三星电子株式会社 | Display device and method of making the same |
| CN101329486A (en) * | 2007-06-18 | 2008-12-24 | 株式会社日立显示器 | Display device |
-
2009
- 2009-12-03 CN CN200910251399A patent/CN101728436A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917199A (en) * | 1998-05-15 | 1999-06-29 | Ois Optical Imaging Systems, Inc. | Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same |
| CN1624933A (en) * | 2004-12-21 | 2005-06-08 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN101127366A (en) * | 2006-08-18 | 2008-02-20 | 三星电子株式会社 | Display device and method of making the same |
| CN101329486A (en) * | 2007-06-18 | 2008-12-24 | 株式会社日立显示器 | Display device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8415672B2 (en) | 2010-08-30 | 2013-04-09 | Au Optronics Corporation | Transistor with etching stop layer and manufacturing method thereof |
| US8883574B2 (en) | 2010-08-30 | 2014-11-11 | Au Optronics Corporation | Transistor with etching stop layer and manufacturing method thereof |
| CN102645799A (en) * | 2011-03-29 | 2012-08-22 | 京东方科技集团股份有限公司 | Liquid crystal display device, array substrate and color-film substrate as well as manufacturing methods thereof |
| CN102645799B (en) * | 2011-03-29 | 2015-01-07 | 京东方科技集团股份有限公司 | Liquid crystal display device, array substrate and color-film substrate as well as manufacturing methods thereof |
| US9036106B2 (en) | 2011-03-29 | 2015-05-19 | Boe Technology Group Co., Ltd. | Liquid crystal display device in which array substrate includes black matrix and method of manufacturing the same |
| WO2018166411A1 (en) * | 2017-03-17 | 2018-09-20 | 京东方科技集团股份有限公司 | Thin film transistor and array substrate |
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Application publication date: 20100609 |