CN101728362A - 三维集成电路的堆叠接合界面结构 - Google Patents

三维集成电路的堆叠接合界面结构 Download PDF

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CN101728362A
CN101728362A CN200910119324A CN200910119324A CN101728362A CN 101728362 A CN101728362 A CN 101728362A CN 200910119324 A CN200910119324 A CN 200910119324A CN 200910119324 A CN200910119324 A CN 200910119324A CN 101728362 A CN101728362 A CN 101728362A
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substrate
vias
penetrates
protuberance
tsv
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CN101728362B (zh
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曾明鸿
卿恺明
陈承先
萧景文
黃宏麟
王宗鼎
谢元智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提出了一种堆叠半导体衬底的***、结构和制造方法。第一衬底包括第一侧与第二侧。穿透衬底通孔从第一衬底的第一侧突出，穿透衬底通孔的第一突出部具有导电保护涂层，以及穿透衬底通孔的第二突出部具有隔离衬垫。该***还包括第二衬底以及接合界面结构，其中接合界面结构在穿透衬底通孔的第一突出部的导电保护涂层处将所述第二衬底结合到第一衬底上。

Description

三维集成电路的堆叠接合界面结构
技术领域
本发明通常涉及一种三维互连衬底的衬底-衬底键合，尤其涉及一种使用预处理穿透衬底通孔(TSV)突起和键合的三维(3D)衬底堆叠接合界面结构。
背景技术
半导体器件是通过在半导体衬底中形成有源区域、在衬底上方沉积各种绝缘层、导电层和半导体层、以及按照顺序步骤对这些层进行图案化而制成。半导体器件的最上层或者最后形成的层通常包括金属化层。这些金属化层一般包括一或多个金属互连层，其中金属互连层具有设置在绝缘材料内部的导线，并且金属化层可以向底层的有源区域和衬底内部及上方的线路提供连接。集成电路芯片可以贴附在引线框上，然后在陶瓷或塑料载体中进行封装。
但是，随着收缩半导体器件的成本持续增长，其它可选择手段正在被研发，例如将电路集成扩展到三维或半导体衬底堆叠中。两个或更多的衬底结合一起，以形成三维结构。
在现有的制作工艺中，将接触焊垫金属层沉积到衬底上方，并进行图案化。钝化介电层形成在接触焊垫金属层上，并且在介电层上形成开口，以暴露出接触焊垫。因此，接触焊垫被嵌入芯片表面中。为了将接触焊垫连接到印刷电路板(PCB)上，在接触焊垫上形成突出金属块。利用焊料、粘合剂或者通过热压或热超声压，将金属块结合到PCB接触焊垫上。
金属块可以由焊料制成，利用金属焊垫上的金属块将管芯(die)放置在PCB上，并且焊料回流以形成焊点。因此，在存在热应力时，结合可以机械增强并且可靠，但是焊块尺寸难以随着焊垫的变小和焊垫之间的间距的减小也按比例减小。由于焊块尺寸减小以适应更小的接触焊垫和间距，焊垫的耐机械和热的性能变得更不牢固。此外，焊球(焊块)大小限定芯片之间的相隔距离。如果相隔距离太小，在热循环过程中焊点上将存在增加的疲劳应力。
此外，在焊块互连中，焊垫上的焊料湿润是决定互连工艺产量和焊点可靠性的关键因素。键合湿润涉及各种物理属性，例如表面张力不均衡、粘性耗散、分子运动、化学反应以及扩散。湿润的程度可以由接触角描述，液体界面以该角度与固体界面接触。铜与传统低共熔焊料之间的湿润程度可以不是最佳的。如果湿润较差，焊料可以在铜表面上形成紧凑滴，在铜和低共熔焊料之间留下不充足的键合区域。
此外，由于铜容易氧化，并且在键合工艺中能够氧化，因此焊点可靠性可能是个问题。如果铜氧化，则不会提供良好的电接触。另外，相对较大尺寸的焊块对收缩器件是不导电的，该尺寸可位于几十微米或更大的范围内。
发明内容
通过将预处理穿透衬底通孔(TSV)突起结合到另一衬底来形成三维(3D)衬底堆叠接合界面结构的***、结构和制造方法，上述及其他问题通常可以解决或避免，并且通常可以获得技术优点。
根据本发明的实施例，本发明提出了一种堆叠半导体衬底的***、结构和制造方法。该***提供了包括第一侧与第二侧的第一衬底。穿透衬底通孔(TSV)从第一衬底的第一侧突出，穿透衬底通孔的第一突出部具有导电保护涂层，以及穿透衬底通孔的第二突出部具有隔离衬垫。该***还包括第二衬底以及接合界面结构，其中接合界面结构在穿透衬底通孔的第一突出部的导电保护涂层处将所述第二衬底结合到第一衬底上。
示例实施例的一个优点是，由于利用穿透衬底通孔和铜突起的3D衬底堆叠接合界面的小节距组装，整个器件的封装尺寸可以按比例减小。
另一个优点是围绕铜突起部的隔离衬垫减少或消除了电流泄漏。额外的优点是3D衬底堆叠接合界面结构消除了第一侧隔离和金属化。这减少了工艺的总成本。再一个优点是将穿透衬底通孔和镀焊料结合的工艺消除了进行顶部μ块(μ-bump)光学处理的需要，从而进一步地降低了成本。
为了更好地理解下文中对本发明的详细描述，上文广泛地概述了本发明的示例实施例的特征及技术优点。本发明实施例的附加特征和优点将在下面的描述中给出，这些特征和优点形成本发明保护范围要求的目标。本领域的普通技术人员应当了解，文中公开的概念与特定实施例可以容易地作为修改或设计其他结构或步骤的基础，以实现本发明相同的目的。本领域的普通技术人员应当了解，这样的等同结构不脱离如所附权利要求限定的示例实施例的精神和范围。
附图说明
为了更全面地理解本发明的示例实施例及其优点，现在将结合附图给出下面的详细说明，其中：
图1为本发明实施例的3D衬底堆叠接合界面结构的***图；
图2A-2K为本发明实施例的堆叠接合界面结构制造方法剖视图；
图3为堆叠接合界面结构的细节示意图；以及
除非另有说明，不同附图中对应的数字及符号通常用于指示相应的元件。绘制的附图是为了清楚阐明发明优选实施例的相关方面，不必须按照比例绘制。
具体实施方式
下面，将对本发明的优选实施例的实现及使用做出讨论。但是，应当了解本发明提供许多可应用的发明概念，这些发明概念可以体现在各种特定环境下。文中讨论的特定实施例仅阐述了本发明的实现及使用的特定方式，并不用来限制本发明的保护范围。
参考图1，该图显示了本发明实施例的堆叠接合界面***100。***100包括第一衬底102、第二衬底104、第三衬底106、第四衬底108以及第五衬底110。衬底104、106、108和110可以包括例如硅或者其他半导体材料。此外，例如衬底102的衬底可以包括非半导体材料，例如、双马来酰亚胺三嗪(BT)等。
衬底104-110可以包括一或多个导电层。例如可以存在形成在衬底104-110内部的多个金属化层，并且衬底104-110可以包括多个其他层，例如多晶硅间(inter-poly)氧化物(IPO)或者金属间电介质(IMD)层(图中未显示)。衬底104-110还可以包括其他有源元件或电路。此外，***100中可以包括附加衬底(图中未显示)。下文中，“衬底”一词通常指示半导体衬底，包括上面形成有各种层和结构的半导体衬底。
请注意，虽然在整个说明书和权利要求中使用了词语“层”，但是使用层形成的对应结构不应当一起解释为仅是连续的或者不中断的结构。通过阅读说明书清楚可知，上述层可以被划分到不同和单独的结构(例如有源区域)中，部分或者全部的结构包括部分半导体层。在另一实施例中，层可以表示具有不均匀外观的连续结构，但其可以包括具有不同物理或化学特性的区域。
此外，任意或所有的衬底1-4-110可以包括穿透衬底通孔(TSV)112，TSV 112从衬底的第一侧突出，并且在衬底的第一侧和第二侧之间提供电连接。
图2A-2K显示了堆叠接合界面结构的制造方法剖视图。现在参考图2A，图中显示了处理中的衬底201。衬底201包括体硅202和互连层204，衬底201包括形成在前段线(FEOL)中的有源元件或电路，例如元件206。体硅202例如可以包括硅、其他半导体材料或者单晶硅上氧化硅。化合物半导体，例如GaAs、InP、Si/Ge或者SiC可以用来代替硅。衬底201可以包括其他导电层或者其他半导体元件，例如晶体管、二极管等。
正如在通常电路处理过程中，衬底201的第一侧210方向朝下，其第二侧212方向朝上。TSV开口208方向朝下地位于衬底201中，其中TSV开口208内部形成有TSV结构。例如互连层204、元件206及器件的其他层如图所示位于衬底201中。
为了形成TSV开口208，例如可以通过在衬底201的第二侧212上方沉积光致抗蚀剂(图中未显示)对衬底201进行图案化。利用具有透明区和不透明区的标线片，可以使用公知技术图案化光致抗蚀剂或硬掩模(图中未显示)。
例如使用反应离子等离子体工艺，可以对TSV开口208进行蚀刻。在实施例中，可以执行能够获得高纵横比结构的博施工艺(Bosch process)。或者实施例中可以采用湿蚀刻。产生的横剖面如图2A所示。在一个实施例中，TSV开口208可以是大约85μm到大约95μm深，并且直径为大约20μm到大约30μm。但是，其他深度和直径的TSV开口208也落在本发明实施例的范围内。
这样蚀刻的TSV开口208被涂覆有介电层，例如原硅酸四乙酯(TEOS)、SiO2、SiN、低k电介质、它们的组合或者其他用来形成隔离衬垫214的电介质，如图2B所示。隔离衬垫214可以在例如化学气相沉积(CVD)工艺中沉积，并且例如可以是大约
Figure G2009101193246D0000051
到大约的Si3N4，紧跟着是
Figure G2009101193246D0000053
到大约
Figure G2009101193246D0000054
的SiO2。隔离衬垫214可以作为体硅202与后面填入TSV开口208的金属导体之间的钝化层。
现在参考图2C，图2B显示的TSV开口208中被填充有导电材料，从而形成TSV结构216。可以溅镀、电镀或丝网印刷例如Al、Cu、合金等金属来填充TSV结构216。优选地，该处理包括将例如Cu的金属种子层溅射到TSV开口208中。然后，例如利用Cu对TSV开口208进行电镀。或者可以使用其他导电材料。在设置导电材料之后，可以通过化学机械抛光(CMP)工艺将衬底201整平。此外，在CMP工艺之后可以形成导电垫218，导电垫218可以通过已知的工艺，例如沉积、图案化和蚀刻处理形成。
下面参考图2D，然后可以将聚酰亚胺材料设置在衬底201上，并进行图案化以形成下金属化凸块(UMB)型结构220。然后，利用粘合剂222或者其它类似物将载体224结合到衬底201的第二侧212上，如图2E所示。
将衬底201倒置，进而可以将第一侧210变薄(见图2F)。可以将第一侧210变为几微米薄，因而除去部分的体硅202。可以在研磨、磨光、蚀刻、抛光或它们的组合的工艺中使得衬底201变薄。在实施例中，在一个单独处理步骤中，衬底201可以变薄以及第一侧210可以凹进。
但是，在优选实施例中，可以在多步骤工艺中执行凹进处理，例如通过CMP工艺、湿蚀刻工艺、以及接着的干蚀刻工艺。下面参考图2G，湿蚀刻工艺最好具有高的体硅202与隔离衬垫214的选择性。可以采用大于10∶1的选择性，但是体硅202与隔离衬垫214的蚀刻选择性最好大于20∶1。高选择性的蚀刻导致第一侧210的体硅202相比隔离衬垫214以更快的速率蚀刻。因此，TSV结构216上的隔离衬垫214从体硅202上突出。隔离衬垫214防止TSV结构216被蚀刻。
湿蚀刻之后可以是干蚀刻，其中TSV结构216的顶部从隔离衬垫214上清除，留下部分的TSV结构216由隔离衬垫214保护。图2G产生的结构显示衬底201的体硅202具有从表面突出的TSV结构216。第一部分突出TSV结构226包括暴露的Cu或者其他导电材料。另外，第二部分突出TSV结构228仍由隔离衬垫214保护。隔离衬垫214从体硅202延伸高度H，其中H可以从大约5μm到大约15μm。被保护的TSV侧壁是实施例的优点，因为Cu或者其他材料的TSV结构216可防止被未蚀刻的隔离衬垫214氧化，从而消除导致电流泄漏的原因。
现在参考图2H，利用湿润层，例如无电镀镍/浸金(ENIG)227或者其他金属抛光工艺，对第一部分突出TSV 226进行电镀。在本实施例中，ENIG 227包括覆盖有用来防止镍氧化的浸金薄层的非电解镍镀层，其中非电解镍镀层提供良好的湿材料用于焊料232(图2H中未显示，请参考图2J)。ENIG 227阻止氧化，并且对湿润层有抗性，因此防止或者最大程度地减小Cu腐蚀。此外，该结构提供与焊料232或者TSV结构216中使用的其他材料较好的接合。ENIG 227对TSV结构216任何暴露的Cu部分进行电镀，因此基本上可以防止突出TSV结构216被隔离衬垫214或者ENIG 227氧化。ENIG 227可以包括Ni浸镀和随后的Au浸镀的两部分浸镀工艺中实现。
参考图2I，衬底201被涂覆有底层填料230，底层填料230例如可以包括聚合物。这里存在具有不同热传输和机械特性的几种类型的底层填充材料，所有的底层填充材料均落在本发明实施例的保护范围内。
接着请参考图2J，在回流焊工艺中，将管芯234和236键合到TSV结构216上。通过将管芯234和236的导电垫键合到衬底201的TSV结构216的ENIG 227上，焊料232将管芯234和236结合到衬底201上。键合工艺可以通过热压、热超声压或其他类似工艺完成。
现在参考图2K，该图给出了相应的结构250。可以看作底层填料230增加了结构支撑。利用本领域公知的技术可以对衬底进行进一步的处理，或者然后可以结束该处理。
图3为局部堆叠接合界面的详细示意图。衬底300包括体硅301，图示TSV 304从体硅301上突出。隔离衬垫305可以包括多个层，例如第一层308或者原硅酸四乙酯(TEOS)层、热生长二氧化硅层、其他介电层等。第一层308的厚度可以位于大约
Figure G2009101193246D0000071
到大约
Figure G2009101193246D0000072
之间。第二层306可以是氮化硅或其他类似物，第二层306的厚度可以位于大约
Figure G2009101193246D0000073
到大约之间。
隔离衬垫305从衬底301上突出高度H，其中高度H可以位于大约4μm到大约15μm之间。注意TSV 304具有凸起形状。凸起形状的TSV 304可以有助于提供良好的电性和结构结合。TSV 304还具有剩余的突出部312，其中剩余突出部312没有被隔离衬垫305保护。剩余突出部312的高度为T，其中T可以位于大约4μm到大约15μm之间。无电镀镍/浸金(ENIG)层310设置在剩余突出部312上，并包括厚度在大约1μm到大约4μm之间的非电解镍镀层，其中该非电解镍镀层被浸没在Au中。ENIG层310为有效的反扩散/湿润层。由于可以防止导电TSV材料(本实施例中为Cu)发生腐蚀和氧化，因此包括例如图3所示实施例的衬底、管芯或晶片可以被存储用于进一步的处理，或者被运输用于进一步的处理。
因此，本发明提出了一种可以包括管芯、部分晶片和晶片的堆叠衬底***、此外，描述了一种部分堆叠接合界面，显示了一种实施例，即在键合之前管芯、部分晶片或晶片可以被存储或运输。再者，本发明提出了一种制造实施例堆叠衬底的方法。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (15)

1.一种堆叠半导体衬底的***，所述***包括：
第一衬底，所述第一衬底包括：
第一侧与第二侧；
从所述第一侧突出的穿透衬底通孔，其中所述穿透衬底通孔的第一突出部具有导电保护涂层，并且所述穿透衬底通孔的第二突出部具有隔离衬垫；
第二衬底；和
在所述穿透衬底通孔的第一突出部的导电保护涂层处将所述第二衬底键合到所述第一衬底上的接合界面结构。
2.如权利要求1所述的***，其中所述导电保护涂层为无电镀镍/浸金(ENIG)，其中所述ENIG的厚度为大约1μm到大约4μm之间。
3.如权利要求1所述的***，其中位于键合接点处的键合金属选自包括Cu、W、Au、Ag、Sn、Pb、它们的组合及其合金的组。
4.如权利要求1所述的***，其中所述隔离衬垫包括氧化物、氮化物或者低k电介质。
5.如权利要求1所述的***，其中所述穿透衬底通孔包括电镀铜。
6.如权利要求1所述的***，其中所述隔离衬垫突出所述第一侧上方大约4μm到大约15μm。
7.如权利要求1所述的***，其中所述穿透衬底通孔的第一突出部具有凸起形状。
8.如权利要求1所述的***，还包括具有n-1个接合界面结构的n个衬底。
9.一种部分接合结构，包括：
具有第一侧和第二侧的衬底；
从所述第一侧突出的穿透衬底通孔；
具有导电保护涂层的所述穿透衬底通孔的第一突出部；以及
具有隔离衬垫的所述穿透衬底通孔的第二突出部，其中所述第二突出部在所述第一侧上方突出大约4μm到大约15μm。
10.如权利要求9所述的部分接合结构，其中所述导电保护涂层为无电镀镍/浸金(ENIG)，其中所述ENIG的厚度为大约1μm到大约4μm之间。
11.如权利要求9所述的部分接合结构，其中所述穿透衬底通孔的第一突出部具有凸起形状。
12.一种堆叠集成电路结构，所述结构包括：
部分接合结构，所述部分接合结构包括：
具有第一侧和第二侧的第一衬底；
从所述第一侧突出的穿透衬底通孔；
具有导电保护涂层的所述穿透衬底通孔的第一突出部；以及
具有隔离衬垫涂层的所述穿透衬底通孔的第二突出部；和
利用焊料键合到所述第一衬底的穿透衬底通孔的第一突出部的第二衬底。
13.如权利要求12所述的结构，其中所述导电保护涂层为无电镀镍/浸金。
14.如权利要求9、12所述的结构，其中所述穿透衬底通孔的第二突出部在所述第一侧的上方突出大约4μm到大约15μm。
15.如权利要求9、12所述的结构，其中所述部分接合结构在键合到所述第二衬底之前被存储或运输大于10小时。
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