CN101694648B - Fourier transform processing method and device - Google Patents
Fourier transform processing method and device Download PDFInfo
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Abstract
The invention provides Fourier transform processing method and device, wherein the method comprises the following steps: a first-stage computing element of multiple-stage computing elements, which is involved in computing, receives computing data, computes data to be computed and outputs computing results in batch; except for the first-stage computing element, each computing element involved in the computing receives computing results output by a superior computing element, computes the received computing results and outputs computing results in batch. The invention can realize processing methods of streamlines among modules or in modules, and not only can support all scales of computation, but also can ensure that new data are input all the time in computing and result data can be output without a break, thereby realizing real streamline computation and effectively improving the efficiency of FFT processing.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of Fourier transform processing method and device.
Background technology
At present, the processing of Fourier transform (Fourier transform abbreviates FFT as) mainly realizes through software.
But, in the common FFT processing procedure that adopts, there is not the acceleration on the algorithm in software processes FFT; Only be to let CPU handle; Under the very big situation of operand, can increase the occupancy of CPU, and because CPU needs it constantly to carry out the memory read-write operation; Therefore can make FFT calculation process speed and treatment effeciency all very low, take for a long time.
Carry out the problem that the FFT processing can cause cpu resource to be taken in a large number to software; Proposed at present through DSP being carried out the scheme that software programming realizes that FFT handles; But when the operand of handling was very big, this mode realized that the time of FFT computing is longer, caused data throughput to reduce; Treatment effeciency also can correspondingly decrease, big limitations the dirigibility of this method of software programming DSP.
Also proposed at present to realize the method for FFT through FPGA; Wherein a kind of method is to utilize two data storeies alternately to read and write and carry out butterfly computation; This mode will surpass the mode of software programming DSP on operation efficiency, but owing to can not when two storeies carry out butterfly computation, import new data in this method, promptly; Have only and after one group of data processing is intact, could organize new data and handle next; This mode is not proper line production, and when the operational data amount was very big, its processing speed will reduce owing to the wait of new data input.
At present, the problem that the FFT treatment effeciency is low, the cpu resource occupancy is big to existing in the correlation technique does not propose effective solution as yet.
Summary of the invention
To the problem that the FFT treatment effeciency is low, the cpu resource occupancy is big that exists in the correlation technique, the object of the present invention is to provide a kind of Fourier transform processing scheme, with in addressing the above problem one of at least.
For realizing above-mentioned purpose, according to an aspect of the present invention, a kind of Fourier transform processing method is provided, the multistage computing unit that is used for through series connection is realized Fourier transform with the mode of flowing water.
Fourier transform processing method according to the present invention comprises: the first order computing unit of participating in the multistage computing unit calculating receives data to be calculated, calculates data to be calculated, and exports result of calculation in batches; For in other computing units that participate in to calculate outside the first order computing unit each; Receive the result of calculation of its higher level's computing unit output; Result of calculation is calculated and exported in batches to result of calculation to receiving; Wherein, the calculating scale of every grade of computing unit is 1/4th of its upper level computing unit calculating scale.
This method can also comprise: as required calculating scale is confirmed the computing unit that needs in a plurality of computing units participate in calculating and the way of output of final calculation result in advance.
In the method, the processing that receives and calculate data to be calculated of first order computing unit comprises: four of the data total amount to be calculated that first order computing unit will import/third-class is divided into three parts and distinguish buffer memorys; For residue 1/4th data of data total amount to be calculated, whenever receive butterfly that one of them data just inputs to first order computing unit with each data in three piece of data of these data and buffer memory simultaneously and calculate the unit and calculate.
And; The processing that first order computing unit is exported result of calculation in batches comprises: after butterfly is calculated a butterfly calculating of the every completion in unit; First order computing unit is directly inputted to data in these four data that calculate the next stage computing unit of first order computing unit; And remaining three data are buffered in three buffer areas; Wherein, each buffer area after each the calculating in these three buffer areas is data of buffer memory only, and the data total amount in each buffer area reaches 1/4th of calculation result data total amount; Reach under 1/4th the situation of result of calculation total amount to the data total amount of its next stage computing unit output at first order computing unit, first order computing unit exports the data in three buffer areas to the next stage computing unit successively.
Correspondingly; Each reception in other computing units that participate in to calculate and the processing of calculating the result of calculation of its higher level's computing unit output comprise: each in other computing units is to its higher level's computing unit directly output or the result of calculation from each buffer area of output afterwards, and four of data total amount/third-class is divided into three parts and buffer memorys; For residue 1/4th data of every batch of output of higher level's computing unit, whenever receive butterfly that one of them data just inputs to current computing unit with each data in three piece of data of these data and buffer memory simultaneously and calculate the unit and calculate.
Next; The processing that in other computing units each is exported result of calculation in batches comprises: after the butterfly of other computing units is calculated a butterfly calculating of the every completion in unit; Data in these four data that calculate are directly inputted to the next stage computing unit of current computing unit; And remaining three data are buffered in three buffer areas; Wherein, each buffer area after each the calculating in these three buffer areas is data of buffer memory only, and the data total amount in each buffer area reaches 1/4th of current computing unit calculation result data total amount;
Reach under 1/4th the situation of result of calculation total amount to the data total amount of its next stage computing unit output at current computing unit, current computing unit exports the data in three buffer areas to the next stage computing unit successively.
According to a further aspect in the invention, a kind of Fourier transform treating apparatus is provided, has comprised the multistage computing unit that is connected in series.
Each grade computing unit according in the Fourier transform treating apparatus of the present invention comprises: the first buffer area group is used for the data that input to its place computing unit are carried out buffer memory; Butterfly is calculated the unit, is used for that the data that input to its place computing unit are carried out butterfly and calculates; The second buffer area group is used for the data after the computing unit calculating at its place are carried out buffer memory; Control module; 3/4ths the data that are used for inputing to the data total amount of its place computing unit are divided into three parts and be buffered in the first buffer area group; And will remain 1/4th data and be directly inputted into butterfly and calculate the unit; Wherein, for each data in the data of residue 1/4th, control module is together imported butterfly with each data in three piece of data of these data and buffer memory and is calculated the unit; And; Be used for directly exporting butterfly and calculate 1/4th of data total amount after the unit calculates; And being buffered in the second buffer area group of the residue 3/4ths of the data total amount after will calculating, accomplish the back in 1/4th data output of directly output and export data in buffer in the second buffer area group.
Wherein, The first buffer area group can comprise first buffer area, second buffer area and the 3rd buffer area; Wherein, each in first buffer area, second buffer area and the 3rd buffer area be used under the control of control module buffer memory input to the place computing unit the data total amount 1/4th.
And; The second buffer area group can comprise the 4th buffer area, the 5th buffer area and the 6th buffer area; Wherein, each in the 4th buffer area, the 5th buffer area and the 6th buffer area be used under the control of control module buffer memory calculate by butterfly unit output the data total amount 1/4th.
Also comprise in the computing unit of this device: basic 2 decimation in frequency computing units, be used for the result of calculation that a plurality of computing units of participating in calculating are exported is carried out the calculating of basic 2 decimations in frequency, and output result of calculation.
By above-mentioned at least one technical scheme of the present invention; Through adopting the disposal route of flowing water in intermodule flowing water and the module; Not only can support the calculating of various scales, can also guarantee has new data input all the time when calculating, guarantee continual result data output simultaneously; Realized that flowing water truly calculates, can effectively improve the efficient that FFT handles.
Description of drawings
Fig. 1 is the process flow diagram according to the Fourier transform processing method of the inventive method embodiment;
Fig. 2 is the synoptic diagram of realization according to an instantiation of the multistage computing unit series connection of the Fourier transform processing method of the inventive method embodiment;
Fig. 3 is the block diagram according to basic 4 decimation in frequency computing units in the Fourier transform treating apparatus of apparatus of the present invention embodiment;
Fig. 4 is the block diagram of the concrete structure instance of basic 4 decimation in frequency computing units in the Fourier transform treating apparatus according to apparatus of the present invention embodiment.
Embodiment
Functional overview
Consider there is the problem that the FFT treatment effeciency is low, the cpu resource occupancy is big in the correlation technique that the present invention proposes to utilize the computing unit of a plurality of series connection to carry out flowing water FFT processing, wherein; Its computing scale data volume of each (every grade) unit storage 3/4 (promptly; The calculative data volume of this grade computing unit 3/4), in the data transfer cycle of residue 1/4 row, carry out butterfly computation (that is, export the calculative data volume of this grade computing unit 3/4); Thereby realized that flowing water truly calculates; Guarantee the continuous input and output of data, effectively improved the efficient that FFT handles, especially can under the situation of macrooperation amount, guarantee treatment effeciency.
To describe embodiments of the invention in detail below.
Method embodiment
In the present embodiment, a kind of Fourier transform processing method is provided, this method can be used for realizing Fourier transform through the multistage computing unit of series connection with the mode of flowing water.
Fig. 1 is the process flow diagram of the Fourier transform processing method of present embodiment; Need to prove; The step of in following method, describing can be carried out in the computer system such as a set of computer-executable instructions, and, though logical order has been shown in Fig. 1; But in some cases, can carry out step shown or that describe with the order that is different from here.As shown in Figure 1, comprise following processing according to the Fourier transform processing method of the embodiment of the invention:
Step S102, the first order computing unit of participating in the multistage computing unit calculating receives data to be calculated, calculates data to be calculated, and exports result of calculation in batches;
Step S104; For in other computing units that participate in to calculate outside the first order computing unit each; Receive the result of calculation of its higher level's computing unit output; Result of calculation is calculated and exported in batches to result of calculation to receiving, and wherein, the calculating scale of every grade of computing unit is 1/4th of its upper level computing unit calculating scale.
Before calculating; Need in advance as required calculating scale need in a plurality of computing units to confirm to participate in the computing unit that calculates and the way of output of final calculation result; That is, confirm it is that back output is calculated in basic 2 decimations in frequency or back output is calculated in basic 4 decimations in frequency.
Wherein, The aforementioned calculation unit can be the computing unit that base 4 extracts; Through these computing units can the realization scale be the calculating of 4n; If the realization scale is the calculating of 2n rather than 4n, carry out the calculating of basic 2 decimations in frequency to the result of calculation of before a plurality of computing units outputs, and output result of calculation.
Through above-mentioned processing, can realize that flowing water truly calculates, guaranteed the continuous input and output of data, effectively improved the efficient that FFT handles, especially can under the situation of macrooperation amount, guarantee treatment effeciency.
Particularly, the structure of multistage computing unit series connection can be with reference to Fig. 2.
Fig. 2 is a concrete instance can realizing the multistage computing unit series connection of above-mentioned processing.Fig. 2 shows 7 (level) computing unit stage1 to stage7, and every grade of computing unit all is provided with butterfly and calculates the unit, and wherein the first six grade computing unit adopts basic 4 decimations in frequency, and the 7th grade of processing unit adopts basic 2 decimations in frequency; The calculating scale of each grade computing unit is 1/4th of its upper level computing unit calculating scale; Wherein, For each basic 4 decimation in frequency computing unit (for example, the stage1 to stage6 among Fig. 2), its structure is mutually the same; And the computing unit of basic 2 decimations in frequency need not carry out buffer memory to data, so 26S Proteasome Structure and Function is comparatively simple; The gating that is connected to of stage1 to stage4 connects, and like this, just can the realization scale is 8192 calculating through 7 grades of computing units (calculating through basic 2 decimations in frequency); And just can the realization scale be 4096 calculating through preceding 6 grades of computing units (calculating without basic 2 decimations in frequency); Wherein each grade computing unit all has fixing separately calculating scale, and for example, the scale that stage1 supports is 8192 and 4096; The scale that stage2 supports is 2048 and 1024, by that analogy.Preferably; In order to guarantee to support the calculating of multiple scale; As shown in Figure 2, can stage1 to stage3 between and the connection of stage3 to stage4 be set to gating and connect, (only stage4 to stage6 participates in calculating thereby make 7 grades of computing units among Fig. 2 can support 64; By supporting that 64 scale stage4 are as input end) calculating of (stage1 to stage7 all participates in calculating, by supporting that 8192 and 4096 is that the stage1 of scale is as input end) scale to 8192.Similarly, the scale of carrying out is 1024 calculating if desired, just exports result of calculation after then can calculating through any stage2 in preceding 6 grades.
Alternatively, the connection among Fig. 2 between the stage1 to stage7 can be set to gating entirely, thereby can support the calculating of more scales.Carry out calculating if desired greater than 8192 scales; Can before stage1 shown in Figure 2, (for example connect more computing unit; The computing unit of 16384 scales is supported in series connection before stage1), and the connected mode between per two computing units can connect for gating.Except 7 level structures shown in Figure 2, also have a lot of mapping modes, this paper enumerates no longer one by one.
Alternatively, after the calculating of carrying out 8192 scales, the FFT that carries out two dimension if desired handles, and then can carry out address translation and be input to stage1 calculating once more and getting final product to the result of calculation of the final output of stage7.
To describe the computation process of every grade of computing unit below in detail.
In step S102, when first order computing unit received and calculates data to be calculated, four of the data total amount to be calculated that first order computing unit will import/third-class was divided into three parts and distinguish buffer memorys; For residue 1/4th data of data total amount to be calculated, whenever receive butterfly that one of them data just inputs to first order computing unit with each data in three piece of data of these data and buffer memory simultaneously and calculate the unit and calculate.That is to say; First order computing unit at first carries out buffer memory with the data (its calculative data total amount 3/4ths) of input; Particularly; / 4th of a calculative data total amount of its that at first will receive is buffered in first buffer area, and 1/4th of the calculative data total amount that next receives is buffered in second buffer area, and 1/4th of the calculative data total amount that next receives is buffered in the 3rd buffer area.Afterwards; When beginning to import last 1/4th data, whenever imported data, just data in these data and first buffer area, data in second buffer area, data in the 3rd buffer area are inputed to butterfly with data in buffer and calculate the unit; Calculating the unit by butterfly unifiedly calculates these 4 data; That is, calculate 4 numbers at every turn, finish until all data computation.
For example; In when storage, suppose that this computing unit supports the calculating of 1024 scales, then 256 data will at first importing of this computing unit are buffered in first buffer area; The the 257th to 512 data are buffered in second buffer area; The the 513rd to 768 data are buffered in the 3rd buffer area, the 769th to 1024 data are inputed to butterfly successively calculate the unit, particularly; In input during the 769th data, the 1st data (data of 513 inputs of this order) of storing in the 1st data (data of 257 inputs of this order) of storing in the 1st data that need these data are stored with first buffer area in and second buffer area and the 3rd buffer area input to butterfly calculation unit; Afterwards; When the 770th data of input; The 2nd data (data of 514 inputs of this order) of storing in the 2nd data (data of 258 inputs of this order) of storing in the 2nd data that need these data are stored with first buffer area in and second buffer area and the 3rd buffer area input to butterfly calculation unit, and the like.
Afterwards; When first order computing unit is exported result of calculation in batches; After butterfly is calculated a butterfly calculating of the each completion in unit; First order computing unit is directly inputted to the next stage computing unit of first order computing unit with data in these four data that calculate, and remaining three data are buffered in three buffer areas, wherein; Each buffer area after each the calculating in these three buffer areas is data of buffer memory only, and the data total amount in each buffer area reaches 1/4th of calculation result data total amount; Reach under 1/4th the situation of result of calculation total amount to the data total amount of its next stage computing unit output at first order computing unit, first order computing unit exports the data in three buffer areas to the next stage computing unit successively.
That is to say; For 4 numbers that calculate at every turn; First order computing unit can directly export one of them number to the next stage computing unit, and three numbers for remaining are stored to one of them in the 4th buffer area; Another is stored to the 5th buffer area, last is stored to the 6th buffer area; When calculating next time; Equally the number in this result of calculation is directly inputted into the next stage computing unit, three numbers for remaining are stored to one of them in the 4th buffer area; Another is stored to the 5th buffer area; Last is stored to the 6th buffer area, reciprocal with this, all stored 1/4th of first order computing unit calculation result data total amount until the 4th buffer area, the 5th buffer area and the 6th buffer area.In output during result of calculation, first order computing unit can at first be exported 1/4th result of calculation without buffer memory, can export the data in the 4th buffer area, the 5th buffer area and the 6th buffer area afterwards successively.
Then, ensuing one-level computing unit just can receive and calculate the result of calculation of its higher level's computing unit output.
Particularly; To the result of calculation of every batch of output of first order computing unit (the directly result of calculation of the result of calculation of the result of calculation of the result of calculation of output, the output of the 4th buffer area, the output of the 5th buffer area, the output of the 6th buffer area), can be all at first four of calculation result data total amount/third-class be divided into three parts and buffer memorys; For residue 1/4th data of every batch of output of higher level's computing unit, whenever receive butterfly that one of them data just inputs to current computing unit with each data in three piece of data of these data and buffer memory simultaneously and calculate the unit and calculate.That is to say; / 4th results that directly export for first order computing unit; Can with wherein 3/4ths carry out trisection and buffer memory, the data for remaining 1/4th can input to the butterfly of this computing unit directly, successively and calculate the unit, and are similar with first order computing unit; The butterfly of other computing units is calculated the unit and only calculates 4 numbers equally at every turn, comprises 1 in this 4 number without the number of current computing unit buffer memory and from every part of each number in 3 piece of data of buffer memory; Afterwards; For the data of exporting in the 4th buffer area, equally can be according to similar processing, promptly; With 3/4ths metadata cache in the 4th buffer area; Directly the butterfly in computing unit at the corresponding levels is calculated the unit and exports and remain 1/4th data in the 4th buffer area afterwards, calculates the unit to butterfly at every turn and directly imports a number, all need from 3 piece of data of buffer memory, respectively extract a number and calculate.Can carry out buffer memory in a comparable manner for the 5th buffer area, the 6th buffer area army,, can receive the result of calculation of higher level's computing unit equally in this manner for other computing unit.That is, the treatment scale of next stage computing unit is 1/4th of a upper level computing unit treatment scale, only calculate at every turn upper level output as a result total amount of data 1/4th.
In step S104; When exporting result of calculation in other computing units in batches; The way of output of result of calculation is identical with the way of output of first order computing unit; Can data in these four data that calculate directly be outputed to the next stage computing unit (or as net result output) of current computing unit, and remaining three data are buffered in three buffer areas, wherein; Each buffer area after each the calculating in these three buffer areas is data of buffer memory only, and the data total amount in each buffer area reaches 1/4th of current computing unit calculation result data total amount; Reach under 1/4th the situation of result of calculation total amount to the data total amount of its next stage computing unit output (or as net result output) at current computing unit, current computing unit is exported three data in the buffer area successively.
Through above-mentioned processing; Not only can support the calculating of various scales; Can also guarantee has new data input all the time when calculating, guarantee continual result data output simultaneously, has realized that flowing water truly calculates; The efficient that FFT handles be can effectively improve, one dimension or Two-dimensional FFT processing in the short clock period, accomplished.
Device embodiment
In the present embodiment; A kind of Fourier transform treating apparatus is provided; Comprise the multistage computing unit (its structure can also can or remove computing unit based on structure increase shown in Figure 2, to adapt to various calculating scales with reference to Fig. 2) that is connected in series in this device; For each computing unit, its treatment scale is four times of its next stage computing unit treatment scale.
Fig. 3 shows the brief configuration according to each grade computing unit in the Fourier transform treating apparatus of present embodiment (computing units of basic 4 decimations in frequency).As shown in Figure 3, each grade computing unit (computing units of basic 4 decimations in frequency) can comprise:
The first buffer area group 1 is used for the data that input to its place computing unit are carried out buffer memory;
Butterfly is calculated unit 2, is connected to the first buffer area group 1, is used for that the data that input to its place computing unit are carried out butterfly and calculates;
The second buffer area group 3 is connected to butterfly and calculates unit 2, is used for the data after the computing unit calculating at its place are carried out buffer memory;
In addition; This device can also comprise the computing unit of basic 2 decimations in frequency; This unit is positioned at the afterbody of all computing units, and it is connected serially to the computing unit of last basic 4 decimation in frequency alternatively, can carry out the calculating of basic 2 decimations in frequency to the result of the last output of basic 4 computing units; Thereby make that Fourier transform treating apparatus scale support according to the present invention is the calculating of 4n, or scale is the calculating of 2n rather than 4n.
Before calculating; Need special control and management unit and confirm that according to the scale of calculating calculating with structure as shown in Figure 2 by those computing units is example; Carry out the calculating of 8192 scales if desired; Then need stage1 to stage7 all to participate in calculating, by support 8192 and 4096 be the stage1 of scale as input end, and need be with the computing unit stage7 of basic 2 decimations in frequency as output terminal; Carry out the calculating of 4096 scales if desired; Then need stage1 to stage6 to participate in calculating; By supporting 8192 and 4096 to be that the stage1 of scale is as input end; And need be with the computing unit stage6 of basic 4 decimations in frequency as output terminal, the gating between the stage6 to stage7 connected be changed to disconnection.
Carry out calculating if desired greater than 8192 scales; Can before stage1 shown in Figure 2, (for example connect more computing unit; The computing unit of 16384 scales is supported in series connection before stage1), and the connected mode between per two computing units can connect for gating.Except 7 level structures shown in Figure 2, also have a lot of mapping modes, this paper enumerates no longer one by one.
Fig. 4 is the synoptic diagram according to the preferred structure of the computing unit of base 4 decimations in frequency of present embodiment.Start from clearly purpose; Omitted the line between control module and other modules among Fig. 4; In practical application; This control module should be calculated the unit with butterfly with each buffer area (the first buffer area group (buffer area in the input-buffer district group) and the second buffer area group (buffer area in the output buffers district group)) among Fig. 4 and be connected; And this control module can be carried out the selection of input channel and the selection of output channel, and particularly, control module is used for which the buffer area output that which buffer area and/or control data that control data need input to the first buffer area group need be from the second buffer area groups.
As shown in Figure 4; The first buffer area group can be made up of the first buffer area RAM 0 (corresponding to first buffer area among the method embodiment), the second buffer area RAM 1 (corresponding to second buffer area among the method embodiment) and the 3rd buffer area RAM 2 (corresponding to the 3rd buffer area among the method embodiment); Wherein, each among the first buffer area RAM 0, the second buffer area RAM 1 and the 3rd buffer area RAM 2 be used under the control of control module 4 buffer memory input to the place computing unit the data total amount 1/4th.
The second buffer area group 3 can be made up of the 4th buffer area RAM 3 (corresponding to the 4th buffer area among the method embodiment), the 5th buffer area RAM 4 (corresponding to the 5th buffer area among the method embodiment) and the 6th buffer area RAM 5 (corresponding to the 6th buffer area among the method embodiment); Wherein, each among the 4th buffer area RAM 3, the 5th buffer area RAM 4 and the 6th buffer area RAM 5 be used under the control of control module 4 buffer memory calculate by butterfly unit output the data total amount 1/4th.
The principle of work of these buffer areas and flow process can no longer repeat referring to the process described in the method embodiment here.
As shown in Figure 4, when realizing that FFT handles, also need be rotated the factor for the data of calculating unit 2 outputs from butterfly and carry out buffer memory again after taking advantage of, preferably, the processing that twiddle factor is taken advantage of also should be accomplished under the control of control module.
Preferably; Module in the Fourier transform treating apparatus of the present invention in each computing unit can realize through FPGA; Those skilled in the art should be understood that the mode that FPGA is programmed, and makes each module can realize above-mentioned functions and the corresponding processing of realization.
Pass through said apparatus; Not only can support the calculating of various scales; Can also guarantee has new data input all the time when calculating, guarantee continual result data output simultaneously, has realized that flowing water truly calculates; The efficient that FFT handles be can effectively improve, one dimension or Two-dimensional FFT processing in the short clock period, accomplished.
In sum, by above-mentioned at least one technical scheme of the present invention, through adopting the disposal route of flowing water in intermodule flowing water and the module; Not only can support the calculating of various scales, can also guarantee has new data input all the time when calculating, guarantee continual result data output simultaneously; Realized that flowing water truly calculates; Can effectively improve the efficient of FFT processing, in the short clock period, accomplish one dimension or Two-dimensional FFT processing, make when carrying out the FFT processing continuously; There is not extra delay; No matter can be in the new data of each clock input, the data of having calculated in each clock output simultaneously to much scales (for example, can support 64 floating-point plural numbers (each 32 of real part imaginary parts) scale of 2048*2048).
Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the memory storage and carry out, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize by calculation element.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. Fourier transform processing method, the multistage computing unit that is used for through series connection is realized Fourier transform with the mode of flowing water, it is characterized in that said method comprises:
The first order computing unit of participating in the said multistage computing unit calculating receives data to be calculated, calculates said data to be calculated, and exports result of calculation in batches;
For in other computing units that participate in to calculate outside the said first order computing unit each; Receive the result of calculation of its higher level's computing unit output; Result of calculation is calculated and exported in batches to result of calculation to receiving, and wherein, the calculating scale of every grade of computing unit is 1/4th of its upper level computing unit calculating scale; Wherein
The processing that computing units at different levels in the said multistage computing unit received and calculated said data to be calculated comprises:
Four of the data total amount to be calculated that said computing unit at different levels will be imported/third-class is divided into three parts and buffer memorys respectively;
For residue 1/4th data of said data total amount to be calculated, whenever receive butterfly that one of them data just inputs to said computing units at different levels with each data in three piece of data of these data and buffer memory simultaneously and calculate the unit and calculate, and
The processing that said computing unit at different levels is exported result of calculation in batches comprises:
After said butterfly is calculated a butterfly calculating of the every completion in unit; Said computing unit at different levels is directly inputted to data in these four data that calculate the next stage computing unit of said computing units at different levels; And remaining three data are buffered in three buffer areas; Wherein, each buffer area after each the calculating in these three buffer areas is data of buffer memory only, and the data total amount in each buffer area reaches 1/4th of calculation result data total amount;
Reach under 1/4th the situation of result of calculation total amount to the data total amount of its next stage computing unit output at current computing unit, active cell exports the data in said three buffer areas to the next stage computing unit successively.
2. method according to claim 1 is characterized in that, also comprises:
As required calculating scale need in the said multistage computing unit to confirm to participate in the computing unit that calculates and the way of output of final calculation result in advance.
3. a Fourier transform treating apparatus comprises the multistage computing unit that is connected in series, and it is characterized in that, each grade computing unit in the said device comprises:
The first buffer area group is used for the data that input to its place computing unit are carried out buffer memory;
Butterfly is calculated the unit, is used for that the data that input to its place computing unit are carried out butterfly and calculates;
The second buffer area group is used for the data after the computing unit calculating at its place are carried out buffer memory;
Control module; 3/4ths the data that are used for inputing to the data total amount of its place computing unit are divided into three parts and be buffered in the said first buffer area group; And will remain 1/4th data and be directly inputted into said butterfly and calculate the unit; Wherein, for each data in the data of said residue 1/4th, said control module is together imported said butterfly with each data in three piece of data of these data and buffer memory and is calculated the unit; And; Be used for the direct said butterfly of output and calculate 1/4th of data total amount after the unit calculates; And being buffered in the said second buffer area group of the residue 3/4ths of the data total amount after will calculating, accomplish the back in 1/4th data output of directly output and export data in buffer in the said second buffer area group.
4. device according to claim 3; It is characterized in that; The said first buffer area group comprises first buffer area, second buffer area and the 3rd buffer area; Wherein, each in said first buffer area, said second buffer area and said the 3rd buffer area be used under the control of said control module buffer memory input to the place computing unit the data total amount 1/4th.
5. device according to claim 3; It is characterized in that; The said second buffer area group comprises the 4th buffer area, the 5th buffer area and the 6th buffer area; Wherein, each in said the 4th buffer area, said the 5th buffer area and said the 6th buffer area be used under the control of said control module buffer memory calculate by said butterfly unit output the data total amount 1/4th.
6. device according to claim 3 is characterized in that, also comprises:
Base 2 decimation in frequency computing units are used for the result of calculation that a plurality of computing units of participating in calculating are exported is carried out the calculating of basic 2 decimations in frequency, and output result of calculation.
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| CN104142811B (en) * | 2014-07-18 | 2017-02-01 | 中国电子科技集团公司第三十八研究所 | High-efficient parallel processing optimization method based on digital signal processing |
| CN108197074B (en) * | 2018-03-01 | 2021-05-04 | 天津芯海创科技有限公司 | Fast Fourier Transform (FFT) data processing method and device |
| CN115080503A (en) * | 2022-07-28 | 2022-09-20 | 中国人民解放军63921部队 | Systolic array reconfigurable processor aiming at FFT (fast Fourier transform) base module mapping |
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| CN101154215A (en) * | 2006-09-27 | 2008-04-02 | 上海杰得微电子有限公司 | Fast Fourier transform method and hardware structure based on three cubed 2 frequency domain sampling |
| CN100390782C (en) * | 2005-07-15 | 2008-05-28 | 北京大学深圳研究生院 | Real-time fast Fourier transform circuit |
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| CN100390782C (en) * | 2005-07-15 | 2008-05-28 | 北京大学深圳研究生院 | Real-time fast Fourier transform circuit |
| CN101154215A (en) * | 2006-09-27 | 2008-04-02 | 上海杰得微电子有限公司 | Fast Fourier transform method and hardware structure based on three cubed 2 frequency domain sampling |
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