CN108628805A - A kind of butterfly processing element and processing method, fft processor of low-power consumption - Google Patents
A kind of butterfly processing element and processing method, fft processor of low-power consumption Download PDFInfo
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Abstract
A kind of butterfly processing element and processing method of low-power consumption, fft processor, the butterfly processing element includes four registers, two pairs of plural plus/minus musical instruments used in a Buddhist or Taoist mass, data selector and complex multiplier, four registers include regA, regB, regC and regD, regA, regC and regB, regD is divided into 2 groups and is connect respectively with 4 road input terminals of first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, 4 road output ends of first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass are connect with 4 road input terminals of second pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, in 4 road output ends of the second plural plus/minus musical instruments used in a Buddhist or Taoist mass, first via output end directly exports, its excess-three road output end is connect with the input terminal of data selector respectively, the output end of data selector, twiddle factor Wnk is connect with the input terminal of complex multiplier respectively.The present invention compares traditional MDC frameworks, improves hardware utilization, reduces delay, increases handling capacity, while reducing power consumption.
Description
Technical field
The present invention relates to a kind of butterfly processing element and FFT devices more particularly to a kind of butterfly processing elements of low-power consumption
And processing method, fft processor.
Background technology
Since Digital Signal Processing has the advantage that do not replace in flexibility, precision, reliability etc., it obtains
To being widely applied, in many fields instead of traditional analog signal processing.Fast Fourier Transform (FFT) FFT is digital letter
A kind of algorithms most in use in number process field, is widely used in video broadcasting, speech recognition, image procossing, biomedicine, thunder
It reaches, orthogonal frequency division multiplexing digital communication system etc..
There are two types of common pipelined architectures by FFT:One-way delay feeds back SDF frameworks and multipath delay exchanger MDC framves
Structure.At some in the higher application of requirement of real-time, as high-throughput orthogonal frequency division multiplex OFDM digital communication system or
Person's ultra-wide band UWB systems etc., carrying out parallel processing to sampled data seems particularly significant.
The intelligent mobiles such as smart mobile phone, tablet computer, portable medical device product generally uses battery as power supply, by
It is limited and the requirement of working time in by battery capacity, power consumption is made to become an important very important factor of evaluation, it is existing
There are technology and product to focus on the speed of intelligent mobile product signal processing more, cannot be satisfied its requirement for power consumption.
As Chinese patent (application publication number CN105608055A) discloses a kind of " butterfly computation list based on bit string framework
Member, fft processor and method ", the butterfly processing element based on bit string framework of the invention, including time delay compensator, multiplier,
First adder, subtracter, the time delay compensator connect the first adder, the subtracter, for the number to input
According into line delay, the output to match the multiplier is delayed;The multiplier connects the first adder, the subtraction
Device carries out multiplying for that will input data therein with corresponding twiddle factor;The first adder is used for according to institute
Output first after the data that time delay compensator exports are added with the data that the multiplier exports is stated as a result, in each calculating cycle
For the first time when operation, the carry flag bit of the first adder is set as 0;The subtracter is used for according to the time delay compensator
The data of output and the data of multiplier output export the second result after subtracting each other;Any one clock cycle, the time delay
Compensator, the multiplier only receive the data input of a bit.The butterfly computation list based on bit string framework of the invention
Although member can realize faster treatment effeciency, belong to traditional butterfly processing element, power consumption is still larger.
Invention content
The present invention proposes a kind of butterfly processing element and processing method, fft processor of low-power consumption, existing for solving
Butterfly processing element, the still larger problem of power consumption.
The present invention is achieved by the following technical programs:
A kind of butterfly processing element of low-power consumption, the butterfly processing element include four registers, two pairs of plural plus/minus
Musical instruments used in a Buddhist or Taoist mass, data selector and complex multiplier, four registers include regA, regB, regC and regD, regA, regC and
RegB, regD are divided into 2 groups and are connect respectively with 4 road input terminals of first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, first pair of plural plus/minus
4 road output ends of musical instruments used in a Buddhist or Taoist mass are connect with 4 road input terminals of second pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, and 4 tunnels of the second plural plus/minus musical instruments used in a Buddhist or Taoist mass are defeated
In outlet, first via output end directly exports, and excess-three road output end is connect with the input terminal of data selector respectively, data choosing
Select the output end of device, twiddle factor Wnk is connect with the input terminal of complex multiplier respectively.
A kind of butterfly processing element of low-power consumption as described above, the twiddle factor are stored in the ROM, single by controlling
Member generates the address for obtaining twiddle factor.
A kind of butterfly processing element of low-power consumption as described above, described control unit are realized by finite state machine.
The present invention also provides a kind of butterfly processing element processing methods of low-power consumption, including butterfly computation as described above
Unit, processing method:
One, the butterfly processing element reads in 4 sampled datas, is sequentially stored into register regA, regB, regC, regD
In;
Two, sampled data exports A+C, A-C, B+D and B-D by first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass;
Three and then using second couple of plural plus/minus musical instruments used in a Buddhist or Taoist mass output (A+C)+(B+D), (A-C)-j (B-D), (A+C)-
(B+D) and (A-C)+j (B-D);
Four, second pair of plural plus/minus first item data of musical instruments used in a Buddhist or Taoist mass will be passed through directly to export, excess-three item passes through data selector
Defeated such as complex multiplier, and the data exported with the rotation fac-tor of input afterwards.
A kind of butterfly processing element processing method of low-power consumption as described above, the twiddle factor are stored in the ROM,
The address for obtaining twiddle factor is generated by control unit.
A kind of butterfly processing element processing method of low-power consumption as described above, described control unit pass through finite state machine
It realizes.
The present invention also provides a kind of fft processors of low-power consumption, including butterfly processing element as described above and data
Converter;Butterfly processing element and data converter are spaced to be provided with multistage, and the data adapter unit is used for previous stage
Operation result rearrangement, obtain the input of next stage butterfly computation, multistage butterfly processing element and data converter it
Between be provided with multichannel data use point.
A kind of fft processor of low-power consumption as described above, the twiddle factor are stored in the ROM, and pass through control unit
It is then closed by control unit when certain level-one butterfly processing element does not need twiddle factor the address for generating acquisition twiddle factor
Close twiddle factor address generator.
A kind of fft processor of low-power consumption as described above, described control unit is realized by finite state machine, for controlling
The working condition of butterfly processing element processed.
Compared with prior art, it is an advantage of the invention that:
1, the present invention for existing butterfly processing element, fft processor cannot meet some special dimensions to power consumption and
The requirement of real-time carries out innovative design.Compared to traditional MDC frameworks, the present invention improves hardware utilization, reduces delay,
Handling capacity is increased, while reducing power consumption.
2, fft processor of the invention is expandable structure, can be not only used for 256 point FFT and calculates, is also applied for 16
Point, 64 points, 1024 point FFT calculate etc., enhance practicability.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described.
Fig. 1 is the radix 4 butterflies schematic diagram of the embodiment of the present invention;
Fig. 2 is the parallel base 4MDC fft processor schematic diagrams in 256: 8 tunnels of the embodiment of the present invention.;
Fig. 3 is the flow chart of processing method of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.
As shown in Figure 1, a kind of butterfly processing element of low-power consumption disclosed in the present embodiment, which includes four
A register, two pairs of plural plus/minus musical instruments used in a Buddhist or Taoist mass, data selector and complex multiplier, four registers include regA, regB,
RegC and regD, regA, regC and regB, regD are divided into 2 groups and 4 tunnels with first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass input respectively
End connection, 4 road output ends of first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass are connect with 4 road input terminals of second pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, the
In 4 road output ends of two plural plus/minus musical instruments used in a Buddhist or Taoist mass, first via output end directly exports, and excess-three road output end is selected with data respectively
The input terminal connection of device is selected, output end, the twiddle factor Wnk of data selector are connect with the input terminal of complex multiplier respectively.
Specifically, the present embodiment is illustrated by taking radix 4 butterflies as an example, butterfly processing element is used for sampling
Data carry out corresponding butterfly computation, are the significant element of fft processor and the critical path of FFT structures, power consumption is whole
Significant portion is accounted in a fft processor, so the power consumption for reducing butterfly processing element is most important.Butterfly processing element is mainly
It is made of multiplier and adder, and in hardware circuit, the power consumption of multiplier is far longer than the power consumption of adder, the present invention
The structure of butterfly processing element is optimized, the quantity of multiplier is reduced, achievees the purpose that reduce power consumption.
As shown in Figure 1, in the state of calculating, butterfly processing element reads in 4 sampled datas, is sequentially stored into register
In regA, regB, regC, regD;By first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, A+C, A-C, B+D, B-D are exported;Then, pass through
Second pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, (A+C)+(B+D), (A-C)-j (B-D), (A+C)-(B+D), (A-C)+j (B-D) are exported,
In, first item needs not move through complex multiplier and directly exports, and excess-three item enters complex multiplier by data selector Mux
Mul is multiplied with the twiddle factor Wnk of input to be exported.
The present embodiment also discloses a kind of butterfly processing element processing method of low-power consumption, includes the following steps:
One, the butterfly processing element reads in 4 sampled datas, is sequentially stored into register regA, regB, regC, regD
In;
Two, sampled data exports A+C, A-C, B+D and B-D by first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass;
Three and then using second couple of plural plus/minus musical instruments used in a Buddhist or Taoist mass output (A+C)+(B+D), (A-C)-j (B-D), (A+C)-
(B+D) and (A-C)+j (B-D);
Four, second pair of plural plus/minus first item data of musical instruments used in a Buddhist or Taoist mass will be passed through directly to export, excess-three item passes through data selector
Defeated such as complex multiplier, and the data exported with the rotation fac-tor of input afterwards.
Specifically, as shown in Figure 1, the present embodiment is illustrated by taking the processing method of radix 4 butterflies as an example,
Butterfly processing element reads in 4 sampled datas when calculating state, is sequentially stored into register regA, regB, regC, regD;Through
First pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass is crossed, A+C, A-C, B+D, B-D are exported;Then, by second pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, (A is exported
+ C)+(B+D), (A-C)-j (B-D), (A+ C)-(B+D), (A-C)+j (B-D), wherein first item needs not move through complex multiplication
Musical instruments used in a Buddhist or Taoist mass directly exports, and excess-three item enters twiddle factor Wnk phases of the complex multiplier Mul with input by data selector Mux
It is multiplied to arrive output.
Butterfly processing element is used to carry out corresponding butterfly computation to sampled data, is the significant element of fft processor,
It is the critical path of FFT structures, power consumption accounts for significant portion in entire fft processor, so reducing butterfly processing element
Power consumption is most important.What butterfly processing element was mainly made of multiplier and adder, and in hardware circuit, multiplier
Power consumption is far longer than the power consumption of adder, and the present invention optimizes the structure of butterfly processing element, reduces the quantity of multiplier,
Achieve the purpose that reduce power consumption.
The present embodiment also discloses a kind of fft processor of low-power consumption, including butterfly processing element and data converter;
Butterfly processing element and data converter are spaced to be provided with multistage, and data adapter unit is used for the operation result weight of previous stage
New sort obtains the input of next stage butterfly computation, multichannel is provided between multistage butterfly processing element and data converter
Data use point.
Specifically, as shown in Fig. 2, used in the embodiment of the present invention is the base 4FFT processors of decimation in frequency, for 8 tunnels
Parallel base 4MDC FFT frameworks, the parallel processing of 8 tunnel sampled datas is realized using 2 road butterfly structures, realizes 256 point FFT fortune
It calculates.Butterfly processing element and data converter are spaced to be provided with multistage, and data adapter unit is used for the operation knot of previous stage
Fruit is resequenced, and is obtained the input of next stage butterfly computation, is provided between multistage butterfly processing element and data converter
Multichannel data uses point.
In the state of calculating butterfly processing element read in 4 sampled datas, be sequentially stored into register regA, regB,
In regC, regD;By first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, A+C, A-C, B+D, B-D are exported;Then, by second pair of plural number
Plus/minus musical instruments used in a Buddhist or Taoist mass, export (A+C)+(B+D), (A-C)-j (B-D), (A+C)-(B+D), (A-C)+j (B-D), wherein, first item
It needs not move through complex multiplier directly to export, excess-three item enters complex multiplier Mul and input by data selector Mux
Twiddle factor Wnk be multiplied and exported.
Twiddle factor is stored in the ROM, and is obtained by look-up table, and calculating speed is improved.In entire calculating process, lead to
The address for crossing control unit generation acquisition twiddle factor then passes through control when certain level-one butterfly computation does not need twiddle factor
Unit closes twiddle factor address generator, reduces power consumption.
Control unit is realized by finite state machine, controls the working condition of remaining module, need not participate in the mould of calculating
Block in a dormant state, when needing to participate in calculating, then is waken up by control unit, achievees the purpose that reduce power consumption.
The buffer being arranged in the present invention carries gated clock, when can effectively reduce unnecessary inside fft processor
Clock activity;Using gray code counter, switch activity is reduced, achievees the purpose that reduce power consumption drop.
The technology contents of the not detailed description of the present invention are known technology.
Claims (9)
1. a kind of butterfly processing element of low-power consumption, which is characterized in that the butterfly processing element include four registers, two pairs
Plural plus/minus musical instruments used in a Buddhist or Taoist mass, data selector and complex multiplier, four registers include regA, regB, regC and regD, regA,
RegC and regB, regD are divided into 2 groups and are connect respectively with 4 road input terminals of first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, first pair of plural number
4 road output ends of plus/minus musical instruments used in a Buddhist or Taoist mass are connect with 4 road input terminals of second pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass, and the 4 of the second plural plus/minus musical instruments used in a Buddhist or Taoist mass
In the output end of road, first via output end directly exports, and excess-three road output end is connect with the input terminal of data selector respectively, number
It is connect respectively with the input terminal of complex multiplier according to the output end of selector, twiddle factor Wnk.
2. a kind of butterfly processing element of low-power consumption according to claim 1, which is characterized in that the twiddle factor storage
In ROM, the address for obtaining twiddle factor is generated by control unit.
3. a kind of butterfly processing element of low-power consumption according to claim 2, which is characterized in that described control unit passes through
Finite state machine is realized.
Include the butterfly fortune as described in claim 1-3 4. a kind of butterfly processing element processing method of low-power consumption, spy are
Calculate unit, processing method:
One, the butterfly processing element reads in 4 sampled datas, is sequentially stored into register regA, regB, regC, regD;
Two, sampled data exports A+C, A-C, B+D and B-D by first pair of plural plus/minus musical instruments used in a Buddhist or Taoist mass;
Three and then using second couple of plural plus/minus musical instruments used in a Buddhist or Taoist mass output (A+C)+(B+D), (A-C)-j (B-D), (A+C)-(B+D)
(A-C)+j (B-D);
Four, second pair of plural plus/minus first item data of musical instruments used in a Buddhist or Taoist mass will be passed through directly to export, excess-three item is defeated after data selector
Such as complex multiplier, and the data exported with the rotation fac-tor of input.
5. a kind of butterfly processing element processing method of low-power consumption according to claim 4, which is characterized in that the rotation
The factor is stored in the ROM, and the address for obtaining twiddle factor is generated by control unit.
6. a kind of butterfly processing element processing method of low-power consumption according to claim 5, which is characterized in that the control
Unit is realized by finite state machine.
7. a kind of fft processor of low-power consumption, which is characterized in that include the butterfly processing element as described in claim 1-3 with
And data converter;Butterfly processing element and data converter are spaced to be provided with multistage, and the data adapter unit is used for will
The operation result of previous stage is resequenced, and the input of next stage butterfly computation is obtained, and multistage butterfly processing element turns with data
It is equipped with multichannel data between parallel operation and uses point.
8. a kind of fft processor of low-power consumption according to claim 7, which is characterized in that the twiddle factor is stored in
In ROM, the address for obtaining twiddle factor is generated by control unit, when certain level-one butterfly processing element does not need twiddle factor
When, then twiddle factor address generator is closed by control unit.
9. a kind of fft processor of low-power consumption according to claim 7, which is characterized in that described control unit is by having
It limits state machine to realize, the working condition for controlling butterfly processing element.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112231626A (en) * | 2020-10-19 | 2021-01-15 | 南京宁麒智能计算芯片研究院有限公司 | FFT processor |
WO2021189710A1 (en) * | 2020-03-24 | 2021-09-30 | 深圳职业技术学院 | Feedback apparatus and fft/ifft processor |
CN117892694A (en) * | 2024-03-14 | 2024-04-16 | 中国石油大学(华东) | FFT twiddle factor index generation circuit and design method thereof |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101729463A (en) * | 2008-10-24 | 2010-06-09 | 中兴通讯股份有限公司 | Hardware device and method for implementing Fourier transform and Fourier inverse transform |
CN101937332A (en) * | 2010-08-19 | 2011-01-05 | 复旦大学 | Multiplier multiplexing method in base 2<4> algorithm-based multi-path FFT processor |
CN102012800A (en) * | 2010-12-01 | 2011-04-13 | 华东师范大学 | Mixed base 2/4 butterfly processing core |
CN201993753U (en) * | 2011-01-19 | 2011-09-28 | 东南大学 | Radix-4 butterfly unit circuit applied to FFT/IFFT |
CN102768654A (en) * | 2011-05-05 | 2012-11-07 | 中兴通讯股份有限公司 | Device with FFT-base (fourier transform) 2-butterfly operation handling ability and method for achieving operation |
CN103970718A (en) * | 2014-05-26 | 2014-08-06 | 苏州威士达信息科技有限公司 | Quick Fourier transformation implementation device and method |
CN104268122A (en) * | 2014-09-12 | 2015-01-07 | 安徽四创电子股份有限公司 | Point-changeable floating point FFT (fast Fourier transform) processor |
CN105608055A (en) * | 2016-01-27 | 2016-05-25 | 南京阿尔法莱瑞通信技术有限公司 | Butterfly operation unit based on bit string architecture, FFT (Fast Fourier Transform) processor and method |
CN107480099A (en) * | 2017-08-21 | 2017-12-15 | 叶军 | Fast Fourier Transform (FFT) device based on Programmable logical controller |
-
2018
- 2018-04-02 CN CN201810280617.1A patent/CN108628805A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101729463A (en) * | 2008-10-24 | 2010-06-09 | 中兴通讯股份有限公司 | Hardware device and method for implementing Fourier transform and Fourier inverse transform |
CN101937332A (en) * | 2010-08-19 | 2011-01-05 | 复旦大学 | Multiplier multiplexing method in base 2<4> algorithm-based multi-path FFT processor |
CN102012800A (en) * | 2010-12-01 | 2011-04-13 | 华东师范大学 | Mixed base 2/4 butterfly processing core |
CN201993753U (en) * | 2011-01-19 | 2011-09-28 | 东南大学 | Radix-4 butterfly unit circuit applied to FFT/IFFT |
CN102768654A (en) * | 2011-05-05 | 2012-11-07 | 中兴通讯股份有限公司 | Device with FFT-base (fourier transform) 2-butterfly operation handling ability and method for achieving operation |
CN103970718A (en) * | 2014-05-26 | 2014-08-06 | 苏州威士达信息科技有限公司 | Quick Fourier transformation implementation device and method |
CN104268122A (en) * | 2014-09-12 | 2015-01-07 | 安徽四创电子股份有限公司 | Point-changeable floating point FFT (fast Fourier transform) processor |
CN105608055A (en) * | 2016-01-27 | 2016-05-25 | 南京阿尔法莱瑞通信技术有限公司 | Butterfly operation unit based on bit string architecture, FFT (Fast Fourier Transform) processor and method |
CN107480099A (en) * | 2017-08-21 | 2017-12-15 | 叶军 | Fast Fourier Transform (FFT) device based on Programmable logical controller |
Non-Patent Citations (4)
Title |
---|
HAINING JIANG等: "Design of an Efficient FFT Processor for OFDM Systems", 《IEEE TRANSACTIONS ON CONSUMER ELECTRONICS》 * |
刘真等: "OFDM***中256点基-4 IFFT模块的设计与FPGA实现", 《广东通信技术》 * |
周加铳等: "一种适用于DVB-T***的新型FFT处理器设计", 《计算机工程与应用》 * |
陈媚媚等: "一种高性能的基-4FFT蝶形运算单元", 《电子工程师》 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021189710A1 (en) * | 2020-03-24 | 2021-09-30 | 深圳职业技术学院 | Feedback apparatus and fft/ifft processor |
CN112231626A (en) * | 2020-10-19 | 2021-01-15 | 南京宁麒智能计算芯片研究院有限公司 | FFT processor |
CN117892694A (en) * | 2024-03-14 | 2024-04-16 | 中国石油大学(华东) | FFT twiddle factor index generation circuit and design method thereof |
CN117892694B (en) * | 2024-03-14 | 2024-05-28 | 中国石油大学(华东) | FFT twiddle factor index generation circuit and design method thereof |
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Application publication date: 20181009 |