CN101692611A - Multi-standard LDPC encoder circuit base on SIMD architecture - Google Patents
Multi-standard LDPC encoder circuit base on SIMD architecture Download PDFInfo
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Abstract
The invention provides a multi-standard low density parity check (LDPC) encoder circuit base on a single instruction multiple data (SIMD) architecture. The LDPC encoder circuit comprises an input buffer unit, a master controller, an instruction memory, an intrinsic information memory, a posterior information memory, an external information memory, a parity check and output buffer unit and a processing unit array, wherein the processing unit array is composed of a plurality of concurrent processing units, and the processing unit adopts very large scale integrated circuits (VLSI) hardware architecture. The encoder adopts a novel two-phase message passing (TPMP) decoding algorithm, ensures that the hardware architecture is not limited by a special architecture of a block matrix, and realizes the separation of the hardware architecture and the block LDPC code check matrix architecture. The invention provides a flexible and configurable design circuit of the processing unit, effectively improves the use ratio of the hardware, reduces design area of chips, provides a dedicated and simplified SIMD instruction set which is suitable for various block LDPC codes, realizes the separation of the hardware architecture and the block LDPC code check matrix architecture, and meets the demands of multi-standard communication.
Description
Technical field
The present invention relates to a kind of decoder circuit, relate in particular to a kind of multi-standard LDPC encoder circuit based on SIMD (singleinstruction multiple data) structure.
Technical background
In the high-speed radio digital communication system, LDPC sign indicating number (Low Density Parity Check Codes low density parity check code) is as important a kind of in the forward error correction (Forward Error Correction), has decoding performance near shannon limit, and it has the high data throughput that parallel processing can provide, be widely applied in numerous wireless communication standards, and be expected to become topmost channel error correction encoding scheme in the following wireless communication standard.The IEEE 802.11n (WLAN) in broadband wireless access field and IEEE 802.16e (WiMAX), the European Digital Television satellite transmits standard (DVB-S2) in DMB field, China Digital TV ground transmission standard (DTMB) and be applicable to the appearance of China Mobile multimedia broadcasting standard numerous wireless communication standards such as (CMMB) of handheld mobile device, require current user terminal receiving equipment can support multiple communication standard, receive signal from the distinct communication standards transmission.Therefore, can support the ldpc decoder of many standards also just to become the focus and the demand of present research gradually in the terminal receiving equipment.
Current most ldpc decoder all adopts single communication standard, and by adopting TPMP (Two Phase Message Passing) algorithm or TDMP (Turbo Decoding MessagePassing) hardware algorithm to realize.Be broadly divided into following three kinds of hardware configuration designs: serve as the full parallel organization ldpc decoder implementation that launch fully on the basis 1. with the LDPC code check matrix; 2. serve as that the basis adopts part parallel to launch with piecemeal LPDC sign indicating number (Block-LDPC Codes), processing unit adopts parallel implementation; 3. serve as that the basis adopts part parallel to launch with piecemeal LDPC sign indicating number, processing unit adopts the implementation of serial process.But above three kinds of hardware design methods all have its shortcomings and deficiencies at the multi-standard LDPC encoder design direction: 1. method only is applicable to the TPMP algorithm, be not suitable for variable code rate, become the design of code length hardware configuration, and hardware is realized along with the code length increase is got over complicated; Method is the concurrency of middle processing unit 2., realizing also there is defective on the multi code Rate of Chinese character structure, is subjected to the restriction of piecemeal LDPC code structure simultaneously; Method is applicable to variable code rate, becomes the code length hardware designs, but its hardware configuration lacks flexibility 3. because processing unit adopts serial process, has difficulties in the multi-standard LDPC encoder design.
Application number is that disclosed technology is put in the case in 200710044715.7 1 kinds of multi-code rate irregular LDPC code decoders, adopt VLSI (very large scale integration) the entire system framework of part parallel, its arithmetic logic adopts the implementation of lateral processes unit and vertical processing unit, and system adopts 12 groups of lateral processes unit, 59 vertical processing units and other inputs, output buffers, intermediate data storage device etc.This kind scheme only is applicable to single communication standard application, and has the problem that is unfavorable for simplifying circuit design.
Based on above-mentioned variety of problems, the present invention proposes a kind of multi-standard LDPC encoder of basic SIMD structure, can realize that code check, code length are configurable flexibly, satisfy the demand of many standard application, simultaneously can guarantee to improve the utilance of hardware circuit, reduce the demand of decoder chip design area.
Summary of the invention
The object of the invention is for providing a kind of many standards communication that is fit to, and code check, code length flexible configuration guarantee the ldpc decoder circuit of the utilance of decoder hardware circuit simultaneously.
For achieving the above object, the invention provides a kind of multi-standard LDPC encoder circuit of SIMD structure, constitute by input buffer cell, master controller, command memory, intrinsic information-storing device, posterior information memory, external information memory, parity check sum output buffer cell and pe array.Pe array is made of a plurality of parallel processing unit PU (processing unit), and processing unit PU adopts the VLSI hardware structure of serial process mode.
Input buffer cell is used to receive the intrinsic information quantization value of self-channel.
Master controller is used to realize the controlled function of whole decoder.As from the instruction control unit reading command, send instructions to control unit, control input end data buffering, iterative decoding, data output etc.
Command memory is used to store the special-purpose SIMD of simplification instruction and matrix information.
The intrinsic information-storing device is used to store the intrinsic information (IntrinsicMessages) that obtains of separating after the mapping.
The posterior information memory is used for storing the more newly-generated posterior information (Posterior Messages) of decode procedure variable node processing unit VNU.
The external information memory is used for storing the more newly-generated external information of decode procedure check node processor CNU (Extrinsic Messages).
Parity check sum output buffer cell is used for the parity arithmetic of whole decoding iterative process, and will decipher the code word buffering output that finishes.
A plurality of parallel processing unit PU arrays are made of a plurality of parallel processing unit PU, are used for according to the required arithmetic operation of finishing of decoding.Processing unit PU circuit adopts pipelining and time-division multiplex technology, improves the system peak clock frequency.
Above-mentioned a plurality of parallel processing unit PU (as shown in Figure 2), it realizes that circuit constitutes code check node processing unit CNU and variable node processing unit VNU by configurable cyclic shifter RCS (Reconfigurable Cyclic Shifter), data recovery unit DRU (DataRecovery Unit), minimum value scanning element MSU (Minimum Scan Unit) and adder unit ADDER four parts.A kind of modified model TPMP decoding algorithm that the present invention adopts, make the hardware configuration of design not limited by the matrix in block form special construction, decode procedure is divided into row renewal and row two stages of renewal, corresponding code check node processing unit CNU (as shown in Figure 3) and two arithmetic elements of variable node processing unit VNU (as shown in Figure 4).
When the decoding iterative process is handled the check-node renewal, adopt less relatively NMS (Normalized Min-Sum) algorithm of computational complexity, reduce the memory span of preserving external information in the pilot process.
Based on the multi-standard LDPC encoder circuit based on the SIMD structure provided by the present invention, the SIMD instruction set (as listed in the table 1) of special-purpose simplification also is provided, this instruction set can realize separating of decoder hardware configuration and piecemeal LDPC code check matrix structure.When many standards merge, can be the basic engineering instruction code with this instruction set according to the different check matrix information of distinct communication standards, decoder be by the whole decoder work of instruction code controlling.
Table 1
| The instruction name | Instruction description |
| ??RSS | The line scanning enabled instruction |
| The instruction name | Instruction description |
| ??CNSS | The instruction of check-node sweep start |
| ??CNS | The check-node scan instruction |
| ??CNSO | The instruction of the check-node end of scan |
| ??RSO | The line scanning END instruction |
| ??CSS | The column scan enabled instruction |
| ??VNSS | The instruction of variable node sweep start |
| ??VNS | The variable node scan instruction |
| ??VNSO | The instruction of the variable node end of scan |
| ??CSO | The column scan END instruction |
| ??CFGP | The configuration parameter instruction |
| ??STDBY | The idle condition instruction |
| ??HDO | The output state instruction |
| ??PIDLE | The pipeline latency status command |
The foregoing invention content, the ldpc decoder that has effectively satisfied based on the SIMD structure carries out many standards communication need, and code check, code length are configurable flexibly, can save the decoder hardware circuit design simultaneously, reduce chip area.
Description of drawings
Fig. 1 is based on the whole hardware structure diagram of the ldpc decoder of SIMD structure;
Fig. 2 is based on the ldpc decoder processing unit structure chart of SIMD structure;
Hardware circuit diagram when Fig. 3 processing unit is operated in the check-node update stage;
Hardware circuit diagram when Fig. 4 processing unit is operated in the variable node update stage;
Specific embodiments
According to the solution that provides in the summary of the invention, as follows based on the embodiment of the multi-standard LDPC encoder of SIMD structure:
Before the decoding, master controller at first reads parameter configuration from command memory, carry out initialization operation.Notice master controller data were ready to after input buffer cell was whenever received complete frame length data, waited to be decoded.After master controller was with data read, input buffer entered the accepting state of next frame data again automatically.
The decoding beginning, internal state machine is controlled whole decoder data flow according to decoding mode, and master controller reads the row or column scan instruction and sends to pe array.The instruction stream that a plurality of parallel processing elements receive autonomous controller to send simultaneously judges whether to carry out this instruction.Master controller masks the section processes unit selectively according to LDPC code check matrix neutron matrix size, and the processing unit of conductively-closed is not carried out the instruction that master controller sends.
It is to enter the serial scan state after line scanning or the column scan that processing unit PU decoding identifies this operation.Adopt follow-on TPMP algorithm, whole decode procedure is broken down into the row renewal and row upgrade two stages, respectively corresponding code check node processing unit CNU and variable node processing unit VNU.
Upgrading data flow with row is example, and (wherein, suppose that processing unit PU degree of parallelism is Z, promptly corresponding one group of data are made of the Z circuit-switched data, and the row of the capable piece of check matrix m heavily is r to describe the specific embodiments that each hardware module participates in the decoding iterative process in detail
m):
As shown in Figure 3, row update stage hardware comprises 2 memory blocks, is respectively posterior information memory and external information memory, Z configurable cyclic shifter RCS, Z parallel adder Adder, Z that parallel data recovery unit DRU, exponent number are a Z parallel minimum value searcher MSU.
1) master controller at first reads out the required posterior information of certain row piece from the posterior information memory, and each clock cycle reads out one group posterior value under the serial operation pattern, and every group of data are to going the piece non-zero submatrices, and then whole capable block operations needs r
mThe individual continuous clock cycle.
2) the rm group posterior information serial that reads out is the configurable cyclic shifter RCS of Z by exponent number, and the side-play amount of configurable cyclic shifter derives from command memory.Master controller reads the side-play amount of the corresponding non-zero submatrices of this row piece and sends cyclic shifter to from command memory, this side-play amount is corresponding with the posterior information value of non-zero submatrices.
3) read r with serial
mThe group posterior information is synchronous, and master controller is the disposable one group of compression external information that reads out this row piece correspondence from the external information memory.
4) the 3rd) go on foot the compression external information that reads out and be retained among Z the parallel data recovery unit DRU, and recover this laterally needed r of renewal according to the serial of submatrix position
mThe group external information.
5) by the 2nd) step and the 4th) resulting r
mGroup posterior information and r
mThe serial of group external information is r by Z parallel adder Adder
mObtain r after the inferior subtraction with serial operation operation
mThe prior information that group is upgraded.
6) Z parallel minimum value search unit MSU serial scan the 5th) r of step generation
mPrior information after group is upgraded obtains the external information after the capable renewal of the Z of this row piece correspondence, and main controller controls should be got back in the external information memory by value write once, and this row piece upgrades EO afterwards, enters next going the blocks of data renewal operation cycle.
The data that obtain after will upgrading after a row or column scanning is finished send back to foreign channels intrinsic information-storing device, posterior information memory and external information memory.So move in circles, finish to enter output state, by output buffer output decoding data up to decoding.The defeated preceding idle condition of decoding next time that enters again after rolling of decoding is waited for decoding next time.
When the decoding iterative process is handled the check-node renewal, adopt computational complexity lower, and decoding performance almost lose very little NMS (Normalized Min-Sum) algorithm.When this algorithm upgrades at check-node external information can the boil down to minimum value, sub-minimum, minimum value position and symbol four category informations and preserve, effectively reduce the memory span of external information in the middle of being used to preserve.
In the present embodiment, processing unit PU (Fig. 3 and shown in Figure 4) adopts pile line operation, and the one-level register has been inserted to constitute multi-stage pipeline in each arithmetic unit inside.Code check node processing unit and variable node processing unit are configured to 6 level production lines (inner 4 grades add 2 grades of water operations of reading and writing external memory storage) according to four arithmetic unit timesharing.Because of adding multi-stage pipeline, shortened critical path, improved the peak value clock frequency, and only selected 1 MUX by increasing corresponding 2, realized CNU and a plurality of arithmetic units of VNU time-sharing multiplex, improved the hardware utilance of arithmetic unit.
In the above-described embodiment, adopt hardware circuit provided by the invention, the special-purpose SIMD of simplification instruction and improved TPMP algorithm, effectively reduce the Average visits of unit interval built-in storage, thereby reduced whole decoder power consumption.Decoding is divided into the row renewal to the TPMP algorithm and row upgrade two stages, thereby make whole decode procedure have more flexibility.Simultaneously, above-mentioned hardware circuit is realized, has reduced hardware design circuit, has improved the hardware utilance, thereby has significantly reduced the area of decoder chip design.
Claims (7)
1. multi-standard LDPC encoder circuit based on the SIMD structure, be made of input buffer cell, master controller, command memory, intrinsic information-storing device, posterior information memory, external information memory, parity check sum output buffer cell and pe array, it is characterized in that: described pe array is made of a plurality of parallel processing unit PU:
Input buffer cell is used to receive the intrinsic information quantization value of self-channel;
Master controller is used to realize the controlled function of whole decoder;
The intrinsic information-storing device is used to store the intrinsic information that obtains after the mapping of separating;
The posterior information memory is used for storing the more newly-generated posterior information of decode procedure variable node processing unit;
The external information memory is used for storing the more newly-generated external information of decode procedure check node processor;
Parity check sum output buffer cell is used for the parity arithmetic of whole decoding iterative process, and will decipher the code word buffering output that finishes.
2. a kind of multi-standard LDPC encoder circuit based on the SIMD structure as claimed in claim 1 is characterized in that: decoder circuit adopts the hardware designs framework of part parallel.
3. a kind of multi-standard LDPC encoder circuit based on the SIMD structure as claimed in claim 1 is characterized in that: described processing unit adopts the VLSI hardware designs framework of serial process mode.
4. want 1 and the processing unit of the described ldpc decoder circuit of claim 3 as right, it is characterized in that: described processing unit circuit is made of configurable cyclic shifter, data recovery unit, minimum value scanning element and adder unit.
5. as claim 1,3,4 described ldpc decoder circuit and processing units thereof, it is characterized in that, adopt improved TPMP decoding algorithm, decode procedure is divided into row renewal and row two stages of renewal, corresponds to code check node processing unit CNU and two arithmetic elements of variable node processing unit VNU respectively.
6. as the processing unit of claim 1,3,4,5 described ldpc decoder circuit, it is characterized in that described processing unit adopts pipelining and time-sharing multiplexing technology circuit design, and processing unit is divided multistage stream treatment.
7. based on above-mentioned ldpc decoder circuit, the present invention also provides a kind of instruction set that is applied to this decoder circuit, it is characterized in that: described instruction set is applicable to various piecemeal LDPC sign indicating numbers.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102244519A (en) * | 2010-05-10 | 2011-11-16 | 上海华虹集成电路有限责任公司 | Low-power consumption low density parity check (LDPC) decoding device and implementation method |
| CN103501210A (en) * | 2013-09-30 | 2014-01-08 | 复旦大学 | High-performance multistandard FEC (Forward Error Correction) decoder |
| CN108365849A (en) * | 2018-01-10 | 2018-08-03 | 东南大学 | The long LDPC code coding/decoding method of multi code Rate of Chinese character multi-code based on SIMD instruction collection |
| CN112187286A (en) * | 2020-09-24 | 2021-01-05 | 复旦大学 | Multi-mode LDPC decoder applied to CCSDS satellite deep space communication |
| CN112636767A (en) * | 2020-12-03 | 2021-04-09 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN113014270A (en) * | 2021-02-22 | 2021-06-22 | 上海大学 | Partially folded polarization code decoder with configurable code length |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102244519A (en) * | 2010-05-10 | 2011-11-16 | 上海华虹集成电路有限责任公司 | Low-power consumption low density parity check (LDPC) decoding device and implementation method |
| CN103501210A (en) * | 2013-09-30 | 2014-01-08 | 复旦大学 | High-performance multistandard FEC (Forward Error Correction) decoder |
| CN103501210B (en) * | 2013-09-30 | 2017-05-10 | 复旦大学 | High-performance multistandard FEC (Forward Error Correction) decoder |
| CN108365849A (en) * | 2018-01-10 | 2018-08-03 | 东南大学 | The long LDPC code coding/decoding method of multi code Rate of Chinese character multi-code based on SIMD instruction collection |
| CN108365849B (en) * | 2018-01-10 | 2021-03-09 | 东南大学 | Multi-code-rate multi-code-length LDPC code decoding method based on SIMD instruction set |
| CN112187286A (en) * | 2020-09-24 | 2021-01-05 | 复旦大学 | Multi-mode LDPC decoder applied to CCSDS satellite deep space communication |
| CN112636767A (en) * | 2020-12-03 | 2021-04-09 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN112636767B (en) * | 2020-12-03 | 2023-04-07 | 重庆邮电大学 | Layered semi-parallel LDPC decoder system with single replacement network |
| CN113014270A (en) * | 2021-02-22 | 2021-06-22 | 上海大学 | Partially folded polarization code decoder with configurable code length |
| CN113014270B (en) * | 2021-02-22 | 2022-08-05 | 上海大学 | Partially folded polarization code decoder with configurable code length |
| CN113055025A (en) * | 2021-03-12 | 2021-06-29 | 上海大学 | Reconfigurable polar code and low density parity check code decoder |
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Application publication date: 20100407 |