CN115694513A - Ultra-high throughput rate LDPC decoder based on shift-type base graph - Google Patents
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Abstract
The invention discloses an LDPC decoder, belonging to the technical field of channel coding and decoding. The LDPC decoder used in a part of scenes in the modern communication field requires high throughput rate, but the hardware resource consumption is large. The invention has the following effective effects: the decoder architecture is designed by using the LDPC check matrix based on the shift-type base graph, so that the hardware resource consumption of a reading and writing-back module in the decoder grouped according to rows is reduced, the area of the decoder is reduced, the throughput rate obtained in unit area is effectively improved, and the decoding throughput rate is greatly improved by a multi-core parallel decoding mode.
Description
Technical Field
The invention belongs to the technical field of channel coding and decoding in the communication field, and particularly relates to an LDPC decoder based on a shift-type base graph, which is applied to channel decoding and has low hardware resource consumption and high throughput rate.
Background
With the increasing degree of informatization of the present society, communication technologies in China are also rapidly developing, for example, technical research related to fifth generation and more advanced mobile communication is continuously advancing, wherein high transmission efficiency and high reliability in the communication technologies are targets that are increasingly refined and pursued.
Low Density Parity Check code (LDPC) is a channel coding and decoding method for forward error correction proposed by Gallager in 1962, and has excellent soft decoding performance, but cannot be applied in time due to limitations of computer computation capability and semiconductor process at the same time. But the excellent error correction performance has been found again by the industry and the scholars in the nineties of the last century and has been widely noticed and researched. Also, the LDPC code has been currently applied to the fields of high-speed memory, optical communication, mobile communication, etc. due to high reliability provided by its superior performance. These fields also require high transmission efficiency, i.e. throughput, and cost of decoder hardware implementation.
The LDPC decoder implemented based on the full parallel mode may have a serious blocking problem on the wiring, and the serial decoding architecture generally cannot provide a higher decoding throughput and has a higher decoding delay. The more used architecture is therefore a partially parallel architecture, which is able to balance throughput and hardware complexity well. However, for the scenario with an extremely high throughput rate, a part of parallel architectures still need to be improved continuously, and a higher throughput rate and area ratio is pursued, so as to improve the transmission efficiency of the encoding and decoding.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the defects of the current LDPC decoder, the invention discloses an LDPC decoder with low hardware area and high throughput rate based on a shift base graph. In particular, the decoder is applicable to, but not limited to, the fields of mobile communication and the like;
the technical scheme is as follows: an ultra-high throughput rate LDPC decoder based on a shift-type base graph is characterized in that: the decoder uses LDPC code base diagram with fixed cyclic shift relation in rows between adjacent rows. The base graph represents the positions of all non-zero elements in the check matrix of the LDPC code. The other rows except the first row in the shift-type base map are obtained by circularly shifting the first row of the base map by a certain number of bits. A decoder core used in the decoder is based on a partial parallel framework, decoding is carried out by adopting a decoding time sequence and a minimum sum decoding algorithm which are grouped according to rows, and the grouping width is the dimension of a quasi-cyclic LDPC code submatrix.
The system comprises an input data bit width conversion module, a bit width conversion memory, an input arbitration module, a shift register, an posterior information reading module, a variable node processing module, a check node processing module, a barrel shifter, an posterior information processing module, an posterior information writing back module, an output selection module, a shift value storage module, a check node information memory, a check node information decompression module, an early termination control module and a selector;
the decoding internal instantiates a plurality of decoder cores, the bit width conversion module is used for receiving external channel information and converting the external channel information into bit width required by the decoder cores, and the output selection module is used for outputting data decoded by the decoder cores in a time-sharing manner.
The decoding process is as follows:
the channel information of the input decoder firstly enters an input data bit width conversion module according to blocks, full frame data is collected and stored into a bit width conversion memory, and the frame information is transmitted to a shift register of a corresponding decoder core after the input arbitration module arbitrates the idle state of the current decoder core. The input arbitration module uses an arbitration mode with fixed priority, and a core with high priority preferentially receives frame information in the same idle state. The internal non-idle decoding core is in a decoding state while receiving the external information.
And the posterior information reading module of the decoder core selects posterior information in a part of registers from the shift register according to the LDPC code base diagram, the selected position is fixedly selected according to the position of a nonzero element in the first row of the LDPC code base diagram, and the selected part of information can be used for subsequent calculation and updating. The input of the reading module is all posterior information blocks, and the output is maximum row repeated block information.
After the decoding is started, the barrel shifter shifts the read information to align to the check node. The number of barrel shifters is the maximum row weight.
The variable node processing module receives the channel information read from the shift register by the posterior information reading module and the check node information read from the check node information memory after being decompressed by the check node information decompressing module, and calculates to obtain the updated variable node information. The variable node processing module of the decoder comprises a plurality of variable node processing units, variable node information is calculated in parallel, and the number of the variable node processing units is the dimension of a quasi-cyclic LDPC code submatrix multiplied by the maximum row weight of an LDPC check matrix.
After the variable node processing module finishes updating, the check node processing module receives the updated variable node information and calculates the updated check node information, including the amplitude and the symbol of the information. The check node processing module of the decoder comprises a plurality of check node processing units, the check node processing units calculate check node information in parallel, and the number (namely parallelism) of the check node units is the dimensionality of the quasi-cyclic LDPC code submatrix. The input end number of the check node unit is the maximum row weight, the output is the first minimum value, the second minimum value and the first minimum value subscript, and the output of the whole check node processing module also comprises the symbol of each check node information.
And after the updating of the check node is finished, storing the updated check node information into a check node information memory. The updated check node information is compressed information, and the compressed information content comprises: the first minimum value, the second minimum value, the first minimum value subscript and the sign bit of the check node information. The data needs to be decompressed by the check node information decompression module and then transmitted to the posterior information processing module.
And the posterior information processing module receives the updated and decompressed check node information and the updated variable node information and calculates to obtain the updated posterior information. The posterior information processing module of the decoder comprises a plurality of variable node processing units, posterior information is calculated in parallel, and the number of the posterior information processing units is the dimension of a quasi-cyclic LDPC code submatrix multiplied by the maximum row weight of an LDPC check matrix. And the posterior information module also updates the line check result at the same time, confirms whether the check of the current decoding line is satisfied and whether the check of all lines is satisfied, and the result is used for decoding to terminate decoding in advance.
And after the posterior information obtained by updating the posterior information module is shifted by the barrel shifter, the posterior information write-back module performs certain shift processing on the posterior information according to the shift parameters of the LDPC code base map and writes the posterior information back to the shift register. The posterior information write-back module of the decoder writes back the updated posterior information to the shift register according to the LDPC code base graph, and the write-back position is fixedly selected according to the position of the non-zero element in the first line of the LDPC code base graph.
When all rows are decoded, all the posterior information is updated, and one iteration is completed. The decoder traverses all rows of the check matrix by using a loop sequence, namely after the decoding of the last row is finished, the next decoding row is the second row to the last. If the decoder core completes decoding within the specified iteration times, the decoder core terminates decoding in advance and outputs the result through the selector and the output selection module; otherwise, if the decoder has not completed decoding for the maximum number of iterations, the decoder core will also terminate decoding, but declare decoding to fail.
The output selection module uses an output selection mode with fixed priority, and the core with high priority outputs data preferentially under the condition that each decoder has data to be output. If all the row checks meet the condition that the decoding is terminated in advance or the iteration times reach the maximum decoding iteration times to cause the decoding to be terminated, the decoder enters a state to be output. The decoding core does not receive new outside channel information until the decoding result is not completely output in the core in advance.
The decoder has the beneficial effects that: the decoder has a fixed row-by-row cyclic shift relation between adjacent rows of the LDPC code base graph, and when a decoding time sequence grouped by rows is adopted, the hardware resource consumption of a reading and writing-back module in the decoder grouped by rows is reduced by using the property of the LDPC check matrix of the shift base graph, the area of the decoder is reduced, the efficiency of unit area is effectively improved, and the decoding throughput rate is greatly improved in a multi-core parallel decoding mode.
Drawings
FIG. 1a is a schematic diagram of a shifted base diagram of a quasi-cyclic LDPC code;
FIG. 1b is a diagram illustrating a check matrix of a quasi-cyclic LDPC code in an embodiment;
FIG. 1c is a schematic diagram of the positions of the posterior information to be selected for decoding each row;
FIG. 1d is a schematic diagram of data shift of a shift register;
FIG. 2 is a diagram of the overall architecture of the present decoder;
FIG. 3 is a block diagram of a decoder core in the present decoder;
Detailed Description
The present invention is further illustrated by the following figures and specific examples, which are to be understood as illustrative only and not as limiting the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalent modifications thereof which may occur to those skilled in the art upon reading the present specification.
The shift pattern base map is a more specific LDPC code base map, using S pg It is shown that each element in the shift-type base graph is 0 or 1, where the element of 1 indicates that there is a connection between the variable node and the check node corresponding to the current position, and the element of 0 indicates that there is no connection between the variable node and the check node corresponding to the current position. S pg The number of rows and columns of (1) is set to M and N, respectively. S pg N lines, all derived from line 1 cyclic shift, are the basic properties and constraints of the shifted base map. The S is pg For illustration only, S pg Flexible transformations may be performed based on the basic properties and constraints of the shifted base map. Using S pcm Represents the LDPC code base graph S pg And (4) a corresponding LDPC code check matrix. S. the pcm The size of the used sub-matrix is set to z. In the following explanation, we set specific parameters M =4,n =16, specifically S pg As shown in fig. 1a, the number of decoder cores is set to 2, the channel information quantization bit is set to 6 bits, the size of the submatrix is set to z =128, the bit width of the input/output interface of the decoder is set to 512bits, and the LDPC check matrix S specifically used for decoding is set pcm As shown in FIG. 1b, S pcm The maximum row weight of the input data bit width conversion module is 12, the working clock frequency of the decoding core is set to be 200MHz, the working frequency of the input data bit width conversion module can be set to be 1200MHz due to the fact that the channel information quantization bit number is 6, and the working frequency can be determined according to the specific required throughput rate.
Based on the above parameter settings, the working flow of the LDPC decoder is as follows, and the decoder receives decoding parameters, that is, the number of rows of the decoder, the maximum number of iterations, and the like, before actual decoding starts. And receiving channel information after the parameters are received, wherein the length of the whole code word channel information is 16 × 128 × 6 bits, so that the input data bit width conversion module needs 24 clock cycles to receive a frame of complete code word channel information, and after the receiving is finished, the frame of code word channel information is stored in a bit width conversion memory and waits to be distributed to a decoder core.
The overall architecture diagram of the decoder is shown in fig. 2, in an initial state, decoder cores are all in an idle state, and an input arbitration module directly transmits codeword channel information of a bit width conversion memory into a shift register of the decoder core 1, so that iterative decoding is started until a data receiving stage is completed. When the decoder core 1 decodes, the input data bit width conversion module receives the channel information of the next frame of code words, receives the channel information of a frame of complete code words and then distributes the channel information to the decoder core 2. And when receiving the complete code word channel information of a frame, starting to distribute the complete code word channel information to the corresponding decoder core according to the idle state of the decoder core.
For a specific decoding process in a single decoder core, in the 1 st clock cycle in the 1 st iteration, the posterior information reading module reads the code word channel information in the shift register, and uses the LDPC check matrix according to the decoding, and the posterior information reading module can send S to the decoder core pcm And reading out partial block information corresponding to the first row, and directly selecting the partial block information in a direct connection mode based on a shift base map posterior information module.
It should be understood that selecting data in a direct connection manner can save a large number of selectors for data selection, and for line 1, the a posteriori information module uses the a posteriori information identified in the first line of fig. 1c to perform LLR selection in the shift register 1 ，LLR 2 ，LLR 4 ，LLR 5 ，LLR 7 ，LLR 9 ，LLR 10 ，LLR 11 ，LLR 13 ，LLR 14 ，LLR 15 ，LLR 16 And 12 segments are directly selected, the data width of each segment is 128 x 6 bits, LLRn is used for representing initial channel information or posterior information of a corresponding column, and n is a column index. The 12 pieces of data are input to a barrel shifter for shifting and aligning to the check nodes. The number of the barrel-type shifters is the same as the maximum row weight, and the number of the barrel-type shifters is 12. The variable node processing module receives the information shifted by the barrel shifter, and the check node information memory decompresses the compressed information and stores the decompressed informationAnd the samples are transmitted to a variable node processing module, and a basic unit variable node processing unit in the variable node processing module subtracts the corresponding posterior information from the corresponding check node information to obtain new variable node information required by the iteration of the current line. In the 1 st iteration process, valid data are not stored in the check node information memory, and the check node information decompression module outputs all-zero data. Each row of the check node information memory only stores 128 pieces of compressed information, and the data format of each piece of compressed information is as follows: the first minimum value, the second minimum value, the first minimum value subscript, and the sign bit of the check node information. After decompression, the number of the information becomes 12 × 128, and the number of the variable node information processed by the variable node processing module is also 12 × 128. And after the variable node information is regrouped into 128 groups according to the corresponding intra-group subscripts, each group contains 12 pieces of information and is input into the check node processing module. The check node processing module comprises 128 check node processing units. And the check node processing unit is used for solving the first minimum value, the subscript and the second minimum value in each group of information and outputting 1 piece of compressed information. The 128 groups of compressed information output by the check node processing module are stored in the check node information memory according to the corresponding lines, and are transmitted to the check node information decompression module to generate new check node information, wherein the number of the new check node information is 12 × 128. The posterior information processing module receives the new check node information and the new variable node information, the posterior information processing module comprises 12 posterior information processing units, and each unit processes and adds 1 pair of the new check node information and the new variable node information to obtain the new posterior information. The number of new a posteriori messages is 12 x 128, and the messages are sent to 12 sets of barrel shifters, shifted again, and aligned to variable nodes. And the shifted information is directly written back into the shift register by a posterior information writing back module in a direct connection mode. In order to decode the next line, the posterior information reading module can continue to read the posterior information in a direct connection mode, and according to the bit width (128 x 6 bits) of the sub-matrix, which is needed to shift the shift register to the high bit when the shift-type base map is written back, the posterior information stored in the shift register is shifted to the high bit, as shown in fig. 1d, after the decoding of the first line is finished, the relative bit of the posterior information is stored in the shift registerAs shown in the second row of fig. 1 d.
It will be appreciated that writing back in a straight-through manner saves a large number of multi-selectors for data selection. When the posterior information module calculates and obtains new posterior information, whether a check equation corresponding to the whole check matrix is satisfied or not can be judged according to the symbol of the new posterior information, and the result is used for a function of jumping out in advance in the decoding process.
The above process completes the decoding of the 1 st row of the corresponding check matrix in the 1 st iteration in fig. 1b, the decoding of the 2 nd, 3 rd and 4 th rows of the corresponding check matrix in the 1 st iteration is consistent with the above decoding process, and the a posteriori information to be selected from the 2 nd, 3 rd and 4 th rows is shown in fig. 1c 2,3 rd and 4 th rows. Because the shift register can carry out shift operation when each row of decoding is finished, the posterior information reading module only needs to read LLR when the posterior information is read in the 2 nd, 3 rd and 4 th rows of decoding 1 ，LLR 2 ，LLR 4 ，LLR 5 ，LLR 7 ，LLR 9 ，LLR 10 ， LLR 11 ，LLR 13 ，LLR 14 ，LLR 15 ，LLR 16 And selecting 12 segments directly. And after the 4 th line decoding is finished, 2 nd iteration is carried out. The 2 nd iteration starts to decode from the 3 rd line, and it should be understood that the data output by the check node information decompression module received by the variable node processing module in the 2 nd iteration and later iterations is no longer all-zero data, but effective data obtained by decompressing the information written into the check node information memory in the last iteration. When the 2 nd iteration proceeds to line 1, the iteration ends. Then proceed to decoding for 3 rd and more iterations. Before the maximum iteration times are met, the condition of jumping out in advance is met, the decoding is terminated in advance, and the decoding success is declared; otherwise, when the decoding iteration times reach the maximum, the decoding is also terminated, and whether the decoding is successful is judged according to the satisfaction condition of all check matrixes corresponding to the check matrixes.
Claims (5)
1. An ultra-high throughput rate LDPC decoder based on a shift-type base graph is characterized in that: the LDPC code base graph used by the decoder has a fixed cyclic shift relation according to rows between adjacent rows, and the base graph represents the relative positions of all non-zero elements in the LDPC code check matrix. The decoder core used in the decoder adopts a decoding time sequence and a minimum sum decoding algorithm which are grouped according to rows, and the width of each row is the dimension of a quasi-cyclic LDPC code submatrix.
The system comprises an input data bit width conversion module, a bit width conversion memory, an input arbitration module, a shift register, an a posteriori information reading module, a variable node processing module, a check node processing module, a barrel shifter, an a posteriori information processing module, an a posteriori information writing back module, an output selection module, a check node information memory, a shift value storage module, a check node information decompression module, an early termination control module and a selector, wherein the input data bit width conversion module is used for converting the input data bit width into the input data bit width;
the decoder is internally instantiated with a plurality of decoder cores, an input data bit width conversion module is used for receiving external information and converting the external information into bit width required by the decoder cores, and an output selection module is used for outputting data decoded by the decoder cores in a time-sharing manner.
Decoding process
The channel information of the input decoder firstly enters an input data bit width conversion module according to blocks, full frame data is collected and stored into a bit width conversion memory, and the frame information is transmitted to a shift register of a corresponding decoder core by an input arbitration module according to the idle state of the current decoder core.
After the decoding starts, the variable node processing module receives and processes two parts of information, namely, a posterior information reading module reads channel information from the shift register and then shifts through the barrel shifter, and a check node information memory reads the check node information which is decompressed by the check node information decompressing module and then is processed to obtain updated variable node information. After the variable node processing module finishes updating, the check node processing module receives the updated variable node information and calculates the updated check node information including the amplitude and the symbol of the check node information. The shift values of the barrel shifter are all derived from the shift value storage module.
And after the updating of the check nodes is finished, the updated check node information is stored into the check node information memory, and meanwhile, the posterior information processing module receives the updated check node information and the updated variable node information and calculates to obtain the updated posterior information. The posterior information processing module also updates the line checking result at the same time, and confirms whether the checking of the current decoding line is satisfied and whether the checking of all lines is satisfied, and the result is used for decoding and terminating decoding in advance. The early termination control module receives the check result of the current row, carries out contraposition comparison on the sign bit of the updated posterior information and the sign bit of the old posterior information, and the comparison result is used for early jump-out judgment.
After the posterior information obtained by updating of the posterior information processing module is shifted by the barrel shifter, the posterior information write-back module performs certain shift processing on the posterior information according to the shift parameters of the LDPC code base map and writes the posterior information back to the shift register, and at this moment, decoding of a row of check matrixes is completed.
When all the rows are decoded, all the posterior information is updated, namely one iteration is completed, and the channel information stored in the shift register is updated to the posterior information. According to the property of the shift-type base map, the decoder core traverses all rows of the check matrix by using a loop sequence, namely after the decoding of the last row is finished, the next decoding row is the second row from the last. If the decoder core completes decoding within the specified iteration times, the decoder core terminates decoding in advance, and the result is output through the selector and the output selection module; otherwise, if the decoder has not completed decoding for the maximum number of iterations, the decoder core will also terminate decoding, but declare decoding to fail.
2. The ultra-high throughput LDPC decoder based on a shifted base pattern of claim 1 wherein: the decoder comprises a plurality of decoder cores for parallel decoding.
3. The ultra-high throughput LDPC decoder based on a shifted base pattern of claim 1 wherein: the posterior information reading module of the decoder core selects posterior information in a part of registers from the shift register according to the LDPC code base diagram, the selected position is fixedly selected according to the position of non-zero elements in the first line of the LDPC code base diagram, and the selected part of information can be used for subsequent calculation and updating.
4. The ultra-high throughput LDPC decoder based on a shifted base pattern of claim 1 wherein: the posterior information write-back module of the decoder core writes back the updated posterior information to the shift register according to the LDPC code base diagram, and the write-back position is fixedly selected according to the position of non-zero elements in the first line of the LDPC code base diagram.
5. The ultra-high throughput LDPC decoder based on a shifted base pattern of claim 1 wherein: the decoder core can support the existence of a shifting relation among partial LDPC code base diagram rows, namely a part of columns can not participate in shifting.
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