CN101673214B - Subdivision information collection system and collection method thereof - Google Patents
Subdivision information collection system and collection method thereof Download PDFInfo
- Publication number
- CN101673214B CN101673214B CN 200910308761 CN200910308761A CN101673214B CN 101673214 B CN101673214 B CN 101673214B CN 200910308761 CN200910308761 CN 200910308761 CN 200910308761 A CN200910308761 A CN 200910308761A CN 101673214 B CN101673214 B CN 101673214B
- Authority
- CN
- China
- Prior art keywords
- module
- subdivision
- counter
- fundamental block
- executable program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention relates to a subdivision information collection system and a collection method thereof, belonging to the technical field of computer optimization processing. The subdivision information collection system comprises a memory mapping loading module, a searching module, a target buffer module, an intermediate command target basic block module, a target command basic block module, a link target basic block module, a context switching module, an optimizing module, a counter mapping table, a first-in first-out buffer zone module and a subdivision module. The invention improves the traditional method for collecting the subdivision information, inserts a storage command of a target system mechanism and maintains a counter mapping table by all target basic blocks in a source executable program to collect subdivision information compared with the prior art, uses two hardware modules to form a hardware part of the system and completes the collection work of the subdivision information of the whole subdivision system by a software and hardware collaborative design with less hardware overhead, thus being capable of collecting accurate subdivision information with less system overhead completely and greatly improving the performance of the whole system.
Description
Technical field
What the present invention relates to is a kind of system and method for computer optimization processing technology field, specifically a kind of subdivision information collection system and collection method thereof.
Background technology
Profile (program summary) information is collected by profiling (subdivision) process, the subdivision process is exactly that the program of moving is collected specific instruction and data, then add up into subdivision information, these subdivision input informations of adding up are to the usefulness of program as code optimization.Generally speaking, why Optimization Work can rely on the work of subdivision process, that the characteristics of program have just determined that the operation action in its past often can affect the behavior that program is moved in the future because the operation of program has predictability, so optimization that can tutorial program.
Traditionally, a kind of method that feeds back to program compiler that provides is provided the subdivision process of code.Compiler at first decomposes the controlled flow graph of source program, and then the various aspects of routine analyzer are inserted detector and collected subdivision information.One section short code sequence that so-called detector is exactly the information recording/ in internal memory program carried out in the subdivision daily record can be placed in the Output rusults that some jump instructions (such as the BRANCH branch instruction) locate to record jump instruction such as detector.The subdivision daily record can return to compiler to the result behind the off-line analysis, and compiler uses these information to produce Optimized code.When using this traditional mode, program can be by complete analysis, the subdivision detector also can be placed into according to the structure of program best position, but this subdivision collection method also is not suitable for dynamic improving process, different with this traditional static optimization method, the structure of program structure self and unclear when the program dynamic optimization begins, because can not insert detector everywhere in program, this statistical information that just means the program that Optimization Work must have been carried out take part is as the basis.
Collect subdivision information several different methods is arranged, but following two kinds of methods commonly used are collected subdivision information: the first is by surveying the mode of (instrumentation), mainly be for specific relevant with program activity or calculate ratio shared in this activity based on the subdivision information collection of surveying, the contrast between the number of times is carried out and is not carried out in the number of times that is performed such as a target fundamental block or conditional jump instruction, and these activities can be recorded simultaneously, and the implementation of record can be collected data by insert probe instructions in code.The second is to pass through sample collection, the program of collecting in this way subdivision information is in operation can not needed program is carried out any modification, only need to be in fixing or the arbitrarily time interval, catch the activity relevant with program by the mode of interrupting, the hot-zone that the value of programmable counter when carrying out such as the jump instruction of program, the information of then collecting by analysis tool analysis exist in just can discovery procedure.The subdivision information of collecting in this method has the characteristics of inaccuracy.
Because these two kinds of methods respectively have characteristics and use occasion, when therefore using these two kinds of methods to collect subdivision information, usually to weigh both pros and cons.Use detection method can within a relatively short time, collect the subdivision information of some, but owing to usually realize by means of software, so the travelling speed of the program that when collecting subdivision information, can slow down; Only can slow down the slightly operation of program of sample collection, but because to collect subdivision information be interruption gap in program, so usually need the longer time.Generally speaking, dynamic optimization system is usually collected subdivision with detection method, because it can be so that whole optimizing process from slow to fast, be optimized to slight optimized code the code of height optimization; The sample collection method need to be moved the long period program to those, perhaps initial optimization has been arranged but still the program that needs to be optimized is very effective.
When collecting subdivision information, weigh the expense of bringing thus.For using traditional static offline optimization method, only need an expense.But for using dynamic optimization method, every operation once just needs an expense, because subdivision information is collected in the program implementation process.Traditional detection mode will insert the instrumentation code sequence of one group of weak point in program, in the binary translation process, this section code can be by execution repeatedly, and the overall performance of dynamic binary translator is had a significant impact.
Find through the retrieval to existing document, the people such as Anderson are in " Proceedings of the 16th ACMSymposium on Operating Systems Principles " (" the 16th computer operating system principle symposial "), in October, 1997, P357-390 writes articles " Continuous Profiling:Where Have ALL theCycles Gone? " (" continuous subdivision: all where all clock period "), summed up the performance of a variety of subdivision system in this article, expense and application scenarios and accurate rank, wherein the expense that causes of nine systems that use pure software to collect the subdivision information is all greater than 20% of whole system expense.These systems can collect subdivision information and higher accuracy is arranged in clock period rank and instruction-level.Also have five systems to use the methods of samplings to collect expense that the subdivision information cause less than 20%.But because collection subdivision information is the interruption gap in program, so usually need the longer time.Simultaneously, their accuracy also can not be guaranteed.In general, to piece or limit subdivision and path subdivision, obtain subdivision information with instrumentation code and can cause respectively 30% and 40% expense.On Itanium (Anthem) processor, to SPECint95 (95 editions shaping benchmarks) benchmark program, Intel (Intel) researchist's experiment shows the expense scope from 14% to 42% of based target fundamental block subdivision.
But in the prior art, although the system that uses detection method to collect subdivision information can guarantee certain accuracy, the very high expense that causes owing to the instrumentation code of adding is inevitable.Although and the expense that the system that uses the method collection subdivision information of sampling causes is very little, these systems need long time and have the characteristics of inaccuracy.
Summary of the invention
The present invention is directed to the prior art above shortcomings, a kind of subdivision information collection system and collection method thereof are provided, collect accurately subdivision information with very little expense.
The present invention is achieved by the following technical solutions:
The present invention relates to subdivision information collection system, comprise: the memory mapping load-on module, search module, the target cache module, metainstruction target fundamental block module, target instruction target word target fundamental block module, hyperlink target fundamental block module, the context handover module, optimize module, the counter mapping table, FIFO buffer module and subdivision module, wherein: the memory mapping load-on module with search module and be connected to transmit the initial address message (IAM) that can carry out target fundamental block in the binary source program, search module and be connected to transmit translation judgement information with context handover module and metainstruction target fundamental block module, metainstruction piece module is connected with transmission objectives fundamental block information with target instruction target word target fundamental block module, target instruction target word target fundamental block module is connected with the FIFO buffer module with transmission objectives fundamental block first address information with hyperlink target fundamental block module respectively, hyperlink target fundamental block module is connected to transmit the first address chain information with the context handover module, the context handover module is connected with the transmission objectives storage address information with the target cache module, the optimization module is connected with target cache sum counter mapping table and transmits process information to be optimized, the FIFO buffer module is connected with the subdivision module with transmission sources programmable counter value information, and the subdivision module is connected with transmission sources programmable counter value information with the counter mapping table.
Judgment value of storage in the described translation judgement information, this judgment value has represented the information whether the target instruction target word target fundamental block corresponding with the source program Counter Value has been translated
Described hyperlink target fundamental block module generates the first address chain information with the link of the first address in the target fundamental block first address information after receiving target fundamental block first address information.
The present invention relates to the collection method of above-mentioned subdivision information collection system, may further comprise the steps:
The first step, source architecture executable program is carried out the memory mapping loading processing, then divide the source architecture executable program after loading take the target fundamental block as unit, generate the target fundamental block, between last two instructions of each target fundamental block, insert the storage instruction of an objective architecture reduced instruction level microprocessor;
Described target fundamental block refers to: the instruction of pointing to the address take jump instruction is as beginning, the code take next bar jump instruction as one section source architecture executable program finishing.
Second step, region of memory of distribution are deposited a counter mapping table, transmit the first address value of described counter mapping table to the FIFO buffer module by dynamic binary translator, catch the first address of this counter mapping table by the FIFO buffer module, then from the first in first out buffer zone module, get the first address of this counter mapping table by the subdivision module;
Described counter mapping table comprises: source architecture programmable counter and conventional counter, wherein: source architecture programmable counter item is the item of depositing the source architecture programmable counter first address value of each target fundamental block, and what the conventional counter item was deposited is the Counter Value of corresponding source architecture program counter value.
The 3rd goes on foot, moves successively each target fundamental block and corresponding save command thereof, this storage instruction triggers FIFO buffer module, the counter first address value of the source architecture executable program of each target fundamental block is stored in the FIFO buffer module, and the subdivision module is taken out the Counter Value of described source architecture executable program as the input of subdivision module from buffer zone module;
The 4th step, subdivision module obtain the Counter Value of described source architecture executable program from the first in first out buffer zone module, this Counter Value is deposited in the first register in the comparison module in the subdivision module, simultaneously, deposit in the comparison module in the subdivision module in the second register from the counter mapping table carries sources architecture program counter value of local internal memory according to hash function, then to the comparison that conflicts of the value in the first register and the second register;
Described local internal memory refers to: on the multi-purpose computer in order to store the physical memory of FIFO buffer module and subdivision module.
Described conflict relatively refers to: when result relatively equates, just upgrade the Counter Value of local internal memory; Unequal as result relatively, judged whether that again conflict occurs: when clashing, processing then conflicts; When not clashing, source architecture program counter value is write the Counter Value that goes in the corresponding local internal memory and upgrade correspondence;
Described conflict is processed and is referred to: the value in the first register is written in the next afterwards unequal memory address of 16 place values in local internal memory corresponding to the second register;
Described renewal refers to: if upgrade for the first time, then write 1 in the counter item of corresponding register mapping table, if not upgrading for the first time, then the value of the counter item of former register mapping table added 1.
The present invention has improved the method for traditional collection subdivision information, compared with prior art collect subdivision information by storage instruction and counter mapping table of maintenance of inserting an objective architecture in each target fundamental block in the executable program of source, the hardware components that forms this system with two hardware modules, finish the collection work of the subdivision information of whole subdivision system with the software and hardware cooperating design method of less hardware spending, thereby can intactly collect accurately subdivision information with less system overhead, thereby greatly improve the performance of whole system.
Description of drawings
Fig. 1 is the overall framework figure of native system.
Fig. 2 is the storage instruction of PowerPC architecture.
Fig. 3 is subdivision module logical schematic.
Fig. 4 is the counter mapping table.
Embodiment
The below elaborates to embodiments of the invention, and present embodiment is implemented under take technical solution of the present invention as prerequisite, provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
The general structure of subdivision information collection system is divided into two parts as shown in Figure 1: present embodiment comprises: comprising: the memory mapping load-on module, search module, the target cache module, metainstruction target fundamental block module, target instruction target word target fundamental block module, hyperlink target fundamental block module, the context handover module, optimize module, the counter mapping table, FIFO buffer module and subdivision module, wherein: the memory mapping load-on module with search module and be connected to transmit the initial address message (IAM) that can carry out target fundamental block in the binary source program, search module and be connected to transmit translation judgement information with context handover module and metainstruction target fundamental block module, metainstruction piece module is connected with transmission objectives fundamental block information with target instruction target word target fundamental block module, target instruction target word target fundamental block module is connected with the FIFO buffer module with transmission objectives fundamental block first address information with hyperlink target fundamental block module respectively, hyperlink target fundamental block module is connected to transmit the first address chain information with the context handover module, the context handover module is connected with the transmission objectives storage address information with the target cache module, the optimization module is connected with target cache sum counter mapping table and transmits process information to be optimized, the FIFO buffer module is connected with the subdivision module with transmission sources programmable counter value information, and the subdivision module is connected with transmission sources programmable counter value information with the counter mapping table.
Judgment value of storage in the described translation judgement information, this judgment value has represented the information whether the target instruction target word target fundamental block corresponding with the source program Counter Value has been translated
Described hyperlink target fundamental block module generates the first address chain information with the link of the first address in the target fundamental block first address information after receiving target fundamental block first address information.
Such as Fig. 2, Fig. 3 and shown in Figure 4, present embodiment is achieved by following steps:
1) executable program that loads MIPS architecture (front-end architecture, the reduced instruction level microprocessor that has MIPS company to develop) obtains the entry address of this executable program in the process space of CrossBit.Then, take the target fundamental block as the unit partition program, target fundamental block usually take the instruction of a jump instruction or system call address pointed as beginning, take next bar jump instruction as end.Finish after the division of target fundamental block, insert the storage instruction of an objective architecture in each target fundamental block, the form of save command as shown in Figure 2.Wherein, the value in source-register territory is for loading the local register number of each target fundamental block first address source architecture program counter value, and the value in address register territory is the register number that is mounted with buffer zone module first address value, and the value of side-play amount is zero.After being to have been obtained to be mounted with the register number of first address source architecture program counter value of target fundamental block by CrossBit, save command determines where inserting of target fundamental block that specifically this save command is inserted into article one location of instruction place after the instruction of register number of the first address source architecture program counter value that contains the target fundamental block.This register number distributes to satisfy by the register in the CrossBit.
2) in CrossBit, distribute a region of memory to deposit a counter mapping table, the counter mapping table as shown in Figure 4, the counter mapping table comprises two of active architecture programmable counter and conventional counter, source architecture programmable counter item is the item of depositing each target fundamental block first address source architecture program counter value, and what the conventional counter item was deposited is Counter Value.Before the special translating purpose fundamental block, in CrossBit, embed the first address value that a bit of assembly code sequence is come the transfer counter mapping table, this section code Exactly-once, the last item of this segment assembly code is the save command of target architecture, and wherein the value in source-register territory is the first address of counter mapping table.
Wherein conventional counter mt_baseaddr variable has been deposited the first address value of counter mapping table, and the FIFO_baseaddr variable has been deposited the first address of fifo buffer.This section embeds assembly code:
__asm__(
“：lwz％％r9，％0\n\t”
“：stw％％r9，％1\n\t”
：
：”m”(mt_baseaddr)，“m”(FIFO_baseaddr)
)
Obtain the first address value of this counter mapping table by the subdivision module, the subdivision module as shown in Figure 3, the value that the subdivision module is got from buffer zone module for the first time is exactly the first address of counter mapping table, in the subdivision module, preserve this value in a register, thereby can guarantee the search operation of ensuing source architecture program counter value.
3) when program is carried out the save command that inserts, this instruction triggers buffer zone module, the first address source architecture program counter value of each target fundamental block is stored in the buffer zone module, the size of this buffer zone module is made as 4K entrance, and each entrance is 32bit (position) size.The subdivision module is taken out this source architecture program counter value from buffer zone module, leave in the first register, add that according to rear 16 a hash function value of getting each source architecture program counter value the value of counter mapping table first address searches source architecture program counter value corresponding in the counter mapping table and whether equate with the source architecture program counter value of getting from buffer zone module; If equate, then upgrade the Counter Value in register mapping table corresponding to the second register intermediate value; If unequal, rear 16 values (greatly the 16th to the 31st in the end) that compare again the source architecture program counter value in the first register and the second register, if rear 16 place values are unequal, then conflict does not occur, source architecture program counter value in this first register is write in the corresponding list item of counter mapping table, and the value that the corresponding counts device is set is 1, if rear 16 of two source architecture program counter value relatively equate, then conflict occurs, and is written in next the rear unequal internal memory of 16 values in the local internal memory.Because the subdivision information of collecting is generally as the formation condition of superblock and path trace, and superblock and path trace all are in a very little zone, therefore the probability that clashes is very little, and several to tens command interval is arranged between each adjacent target fundamental block first address source architecture program counter value, so can be written to the source architecture program counter value that conflict is arranged in the next address of above-mentioned conflict address.
4) in the program process, after the subdivision information collection of a target fundamental block is complete, with the Counter Value of the corresponding target fundamental block in the counter mapping table and the threshold of setting, if less then jump to the subsequent target fundamental block and continue to carry out than threshold value, if variable surpasses threshold value, then generate corresponding superblock or path trace, thereby concentrate the dynamic optimization that carries out program.
Present embodiment comes the more execution number of times of fresh target fundamental block by the subdivision module, the software section of subdivision collection system utilizes the position of this information adjustment aim fundamental block, the target fundamental block of carrying out frequency and surpass threshold value coupled together consist of superblock or generation pass tracing (tracking), thereby can utilize the subdivision system accelerate whole system operation, finish the collection work of the subdivision information of whole subdivision system with the software and hardware cooperating design method of less hardware spending, thereby can intactly collect accurately subdivision information with less system overhead, thereby greatly improve the performance of whole system.
Claims (9)
1. a subdivision information collection system is characterized in that, comprises such as lower module:
The first processing module, be used for source architecture executable program is carried out the memory mapping loading processing, then divide the source architecture executable program after loading take the target fundamental block as unit, generate the target fundamental block, between last two instructions of each target fundamental block, insert the storage instruction of an objective architecture reduced instruction level microprocessor;
The second processing module be used for to distribute a region of memory to deposit the counter mapping table, and the first address value by dynamic binary translator transfer counter mapping table is to the FIFO buffer module;
The FIFO buffer module is for the first address of catching this counter mapping table;
The subdivision module is for the first address of getting this counter mapping table from the first in first out buffer zone module;
The 3rd processing module, be used for moving successively storage instruction corresponding to each target fundamental block and target fundamental block, this storage instruction triggers FIFO buffer module, the first address value of the counter mapping table of the source architecture executable program of each target fundamental block is stored in the FIFO buffer module, and the subdivision module is taken out the Counter Value of described source architecture executable program as the input of subdivision module from the first in first out buffer zone module;
Wherein, the subdivision module also is used for obtaining from the first in first out buffer zone module value of described source architecture executable program counter, this Counter Value is deposited in the first register in the comparison module in the subdivision module, simultaneously, deposit in the comparison module in the subdivision module in the second register from the described counter mapping table carries sources architecture executable program Counter Value of local internal memory according to hash function, then to the comparison that conflicts of the source architecture executable program Counter Value in the first register and the second register.
2. subdivision information collection system according to claim 1, it is characterized in that, judgment value of storage in the translation judgement information, this judgment value has represented the information whether the target instruction target word target fundamental block corresponding with source architecture executable program Counter Value has been translated.
3. subdivision information collection system according to claim 1 is characterized in that, hyperlink target fundamental block module generates the first address chain information with the link of the first address in the target fundamental block first address information after receiving target fundamental block first address information.
4. a subdivision information collection method is characterized in that, may further comprise the steps:
The first step, source architecture executable program is carried out the memory mapping loading processing, then divide the source architecture executable program after loading take the target fundamental block as unit, generate the target fundamental block, between last two instructions of each target fundamental block, insert the storage instruction of an objective architecture reduced instruction level microprocessor;
Second step, region of memory of distribution are deposited the counter mapping table, transmit the first address value of described counter mapping table to the FIFO buffer module by dynamic binary translator, catch the first address of this counter mapping table by the FIFO buffer module, then from the first in first out buffer zone module, get the first address of this counter mapping table by the subdivision module;
The 3rd goes on foot, moves successively storage instruction corresponding to each target fundamental block and target fundamental block, this storage instruction triggers FIFO buffer module, the first address value of the counter mapping table of the source architecture executable program of each target fundamental block is stored in the FIFO buffer module, and the subdivision module is taken out the Counter Value of described source architecture executable program as the input of subdivision module from the first in first out buffer zone module;
The 4th step, subdivision module obtain the value of described source architecture executable program counter from the first in first out buffer zone module, this Counter Value is deposited in the first register in the comparison module in the subdivision module, simultaneously, deposit in the comparison module in the subdivision module in the second register from the described counter mapping table carries sources architecture executable program Counter Value of local internal memory according to hash function, then to the comparison that conflicts of the Counter Value in the first register and the second register.
5. subdivision information collection method according to claim 4, it is characterized in that, described target fundamental block refers to: the instruction of pointing to the address take jump instruction is as beginning, the code take next bar jump instruction as one section source architecture executable program finishing.
6. subdivision information collection method according to claim 4, it is characterized in that, described counter mapping table comprises: source architecture executable program counter and conventional counter, wherein: source architecture executable program counter item is the item of depositing the source architecture executable program counter first address value of each target fundamental block, and what the conventional counter item was deposited is corresponding source architecture executable program Counter Value.
7. subdivision information collection method according to claim 4 is characterized in that, described local internal memory refers to: on the multi-purpose computer in order to store the physical memory of FIFO buffer module and subdivision module.
8. the subdivision information collection method of stating according to claim 4 is characterized in that, described conflict relatively refers to: when result relatively equates, just upgrade the Counter Value of local internal memory; Unequal as result relatively, judged whether that again conflict occurs: when clashing, processing then conflicts: when not clashing, source architecture executable program Counter Value is write the Counter Value that removes and upgrade this this locality internal memory in the corresponding local internal memory.
9. subdivision information collection method according to claim 8 is characterized in that, described renewal refers to: if upgrade for the first time, then write local internal memory counter to 1, if not upgrading for the first time, then the value of local internal memory counter added 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910308761 CN101673214B (en) | 2009-10-26 | 2009-10-26 | Subdivision information collection system and collection method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910308761 CN101673214B (en) | 2009-10-26 | 2009-10-26 | Subdivision information collection system and collection method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101673214A CN101673214A (en) | 2010-03-17 |
| CN101673214B true CN101673214B (en) | 2013-04-17 |
Family
ID=42020448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910308761 Expired - Fee Related CN101673214B (en) | 2009-10-26 | 2009-10-26 | Subdivision information collection system and collection method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101673214B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109324838B (en) * | 2018-08-31 | 2022-05-10 | 深圳市元征科技股份有限公司 | Execution method and execution device of single chip microcomputer program and terminal |
| CN112100054B (en) * | 2020-08-12 | 2021-07-20 | 北京大学 | Data management and control oriented program static analysis method and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1959829A (en) * | 2005-11-04 | 2007-05-09 | 联发科技股份有限公司 | Method and device for resuming interrupted recording on an optical storage media |
| CN101192302A (en) * | 2006-11-28 | 2008-06-04 | 国际商业机器公司 | Method for dispensing work load and image processing system |
| US20080235457A1 (en) * | 2007-03-21 | 2008-09-25 | Hasenplaugh William C | Dynamic quality of service (QoS) for a shared cache |
-
2009
- 2009-10-26 CN CN 200910308761 patent/CN101673214B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1959829A (en) * | 2005-11-04 | 2007-05-09 | 联发科技股份有限公司 | Method and device for resuming interrupted recording on an optical storage media |
| CN101192302A (en) * | 2006-11-28 | 2008-06-04 | 国际商业机器公司 | Method for dispensing work load and image processing system |
| US20080235457A1 (en) * | 2007-03-21 | 2008-09-25 | Hasenplaugh William C | Dynamic quality of service (QoS) for a shared cache |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101673214A (en) | 2010-03-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1332321C (en) | Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program | |
| CN100356327C (en) | Software managed cache optimization system and method for multi-processing systems | |
| CN101329638B (en) | Method and system for analyzing parallelism of program code | |
| CN101452396B (en) | Binary translation method combining static optimization | |
| CN104731719B (en) | Cache system and method | |
| Zhang et al. | Two fast and high-associativity cache schemes | |
| Merten et al. | An architectural framework for runtime optimization | |
| CN102483700B (en) | Lightweight service based on dynamic binary rewriter framework | |
| CN101630291B (en) | Virtual memory system and method thereof | |
| US20080184011A1 (en) | Speculative Throughput Computing | |
| CN101876934B (en) | Method and system for sampling input data | |
| CN103513958A (en) | High-performance instruction caching system and method | |
| CN101344865A (en) | CPU occupancy rate measuring method and apparatus | |
| CN108885579B (en) | Method and apparatus for data mining from kernel tracing | |
| CN102622260A (en) | Optimization method and optimization system of on-line iteration compiling | |
| CN102156634B (en) | Method for realizing value association indirect jump forecast | |
| US7577947B2 (en) | Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects | |
| CN103207772A (en) | Instruction prefetching content selecting method for optimizing WCET (worst-case execution time) of real-time task | |
| CN101673214B (en) | Subdivision information collection system and collection method thereof | |
| CN104424128A (en) | Variable-length instruction word processor system and method | |
| WO2023011236A1 (en) | Compilation optimization method for program source code, and related product | |
| CN114579479A (en) | Low-pollution cache prefetching system and method based on instruction flow mixed mode learning | |
| US20110145503A1 (en) | On-line optimization of software instruction cache | |
| CN101963907A (en) | Dynamic analysis mechanism for computer program hot spot | |
| CN102955709A (en) | Correction apparatus, correction method, and computer product |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130417 Termination date: 20201026 |