CN101673214A - Subdivision information collection system and collection method thereof - Google Patents
Subdivision information collection system and collection method thereof Download PDFInfo
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- CN101673214A CN101673214A CN 200910308761 CN200910308761A CN101673214A CN 101673214 A CN101673214 A CN 101673214A CN 200910308761 CN200910308761 CN 200910308761 CN 200910308761 A CN200910308761 A CN 200910308761A CN 101673214 A CN101673214 A CN 101673214A
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Abstract
The invention relates to a subdivision information collection system and a collection method thereof, belonging to the technical field of computer optimization processing. The subdivision informationcollection system comprises a memory mapping loading module, a searching module, a target buffer module, an intermediate command target basic block module, a target command basic block module, a linktarget basic block module, a context switching module, an optimizing module, a counter mapping table, a first-in first-out buffer zone module and a subdivision module. The invention improves the traditional method for collecting the subdivision information, inserts a storage command of a target system mechanism and maintains a counter mapping table by all target basic blocks in a source executableprogram to collect subdivision information compared with the prior art, uses two hardware modules to form a hardware part of the system and completes the collection work of the subdivision information of the whole subdivision system by a software and hardware collaborative design with less hardware overhead, thus being capable of collecting accurate subdivision information with less system overhead completely and greatly improving the performance of the whole system.
Description
Technical field
What the present invention relates to is a kind of system and method for computer optimization processing technology field, specifically is a kind of subdivision information collection system and collection method thereof.
Background technology
Profile (program summary) information is collected by profiling (subdivision) process, the subdivision process is exactly that the program of moving is collected specific instruction and data, add up into subdivision information then, these subdivision information of adding up input to the usefulness of program as code optimization.Generally speaking, why optimization work can rely on the work of subdivision process, be that the characteristics of program have just determined the operation action in its past often can influence the behavior that program is moved in the future because the operation of program has predictability, so optimization that can tutorial program.
Traditionally, a kind of method that feeds back to program compiler that provides is provided the subdivision process of code.Compiler at first decomposes the controlled flow graph of source program, and the various aspects of routine analyzer are inserted detector then and collected subdivision information.So-called detector is exactly that the information in internal memory program carried out records one section short code sequence in the subdivision daily record, can be placed in the output result that some jump instructions (as the BRANCH branch instruction) locate to note jump instruction such as detector.The subdivision daily record can return to compiler to the result behind the off-line analysis, and compiler uses these information to produce optimize codes.When using this traditional mode, program can be by complete analysis, the subdivision detector also can be placed into best position according to the structure of program, but this subdivision collection method also is not suitable for the dynamic optimization process, different with this traditional static optimization method, the structure of program structure self and unclear when the program dynamic optimization begins, because can not insert detector everywhere in program, this just means the statistical information of the program that optimization work must have been carried out based on part.
Collect subdivision information several different methods is arranged, but following two kinds of methods commonly used are collected subdivision information: first kind is by surveying the mode of (instrumentation), mainly be at the specific activity relevant or calculate ratio shared in this activity based on the subdivision information collection of surveying with program, the contrast between the number of times is carried out and is not carried out in the number of times that is performed such as a target fundamental block or condition jump instruction, and these activities can be recorded simultaneously, and the implementation of record can be collected data by insert probe instructions in code.Second kind is to pass through sample collection, the program of collecting subdivision information in this way is in operation can not needed program is carried out any modification, only need be in fixing or the time interval arbitrarily, catch the activity relevant by the mode of interrupting with program, the value of programmable counter when carrying out, the hot-zone that exists in just can discovery procedure of the information of collecting by analysis tool analysis then such as the jump instruction of program.The subdivision information of collecting in this method has the characteristics of inaccuracy.
Because these two kinds of methods respectively have characteristics and use occasion, when therefore using these two kinds of methods to collect subdivision information, usually to weigh both pros and cons.Use detection method can in a relatively short time, collect the subdivision information of some, but owing to realize by means of software usually, so the travelling speed of the program that when collecting subdivision information, can slow down; Only can slow down the slightly operation of program of sample collection, but because to collect subdivision information be interruption gap in program, so need the longer time usually.Generally speaking, dynamic optimization system usually uses detection method to collect subdivision, because it can be so that whole optimizing process from slow to fast, be optimized to slight optimized code the code of height optimization; The sample collection method need be moved the long period program to those, perhaps initial optimization has been arranged but still the program that needs to be optimized is very effective.
When collecting subdivision information, weigh the expense of bringing thus.For using traditional static offline optimization method, only need an expense.But for using dynamic optimization method, every operation once just needs an expense, because subdivision information is collected in the program implementation process.Traditional detection mode will insert the instrumentation code sequence of one group of weak point in program, in the binary translation process, this section code can be by repeatedly execution, and the overall performance of dynamic binary translator is had a significant impact.
Find through retrieval existing document, people such as Anderson are in " Proceedings of the 16th ACMSymposium on Operating Systems Principles " (" the 16th computer operating system principle symposial "), in October, 1997, P357-390 writes articles " Continuous Profiling:Where Have ALL theCycles Gone? " (" continuous subdivision: all where all clock period "), the a variety of performance of subsystems of cuing open have been summed up in this article, expense and application scenarios and accurate rank, wherein the expense that causes of nine systems that use pure software to collect the subdivision information is all greater than 20% of total system expense.These systems can collect subdivision information and higher accuracy is all arranged in clock period rank and instruction-level.Also have five systems to use the methods of samplings to collect expense that the subdivision information cause less than 20%.But because collection subdivision information is the interruption gap in program, so need the longer time usually.Simultaneously, their accuracy also can not get guaranteeing.In general, to piece or limit subdivision and path subdivision, use instrumentation code to obtain subdivision information and can cause 30% and 40% expense respectively.On Itanium (Anthem) processor, to SPECint95 (95 editions shaping benchmarks) benchmark program, Intel (Intel) researchist's experiment shows the expense scope from 14% to 42% of based target fundamental block subdivision.
But in the prior art, though the system that uses detection method to collect subdivision information can guarantee certain accuracy, the very high expense that causes owing to the instrumentation code of adding is inevitable.Though and the expense that the system that uses the method collection subdivision information of sampling causes is very little, these systems need long time and have the characteristics of inaccuracy.
Summary of the invention
The present invention is directed to the prior art above shortcomings, a kind of subdivision information collection system and collection method thereof are provided, collect subdivision information accurately with very little expense.
The present invention is achieved by the following technical solutions:
The present invention relates to subdivision information collection system, comprise: the memory mapping load-on module, search module, the target cache module, metainstruction target fundamental block module, target instruction target word target fundamental block module, hyperlink target fundamental block module, the context handover module, optimal module, the counter mapping table, FIFO buffer module and subdivision module, wherein: the memory mapping load-on module with search module and be connected and can carry out the initial address message (IAM) of target fundamental block in the binary source program with transmission, searching module is connected with metainstruction target fundamental block module with transmission translation judgement information with the context handover module, metainstruction piece module is connected with transmission objectives fundamental block information with target instruction target word target fundamental block module, target instruction target word target fundamental block module is connected with the FIFO buffer module with transmission objectives fundamental block first address information with hyperlink target fundamental block module respectively, hyperlink target fundamental block module is connected with the context handover module with transmission first address chain information, the context handover module is connected with the transmission objectives storage address information with the target cache module, optimal module is connected with target cache sum counter mapping table and transmits process information to be optimized, the FIFO buffer module is connected with the subdivision module with transmission sources programmable counter value information, and the subdivision module is connected with transmission sources programmable counter value information with the counter mapping table.
Judgment value of storage in the described translation judgement information, the information whether on behalf of the target instruction target word target fundamental block corresponding with the source program Counter Value, this judgment value translated
Described hyperlink target fundamental block module generates the first address chain information with the link of the first address in the target fundamental block first address information after receiving target fundamental block first address information.
The present invention relates to the collection method of above-mentioned subdivision information collection system, may further comprise the steps:
The first step, source architecture executable program is carried out the memory mapping loading processing, be that unit divides the source architecture executable program after loading with the target fundamental block then, generate the target fundamental block, between last two instructions of each target fundamental block, insert the storage instruction of a complex structure reduced instruction level microprocessor;
Described target fundamental block is meant: the instruction of pointing to the address with a jump instruction is beginning, is the code of one section source architecture executable program of end with next bar jump instruction.
Second step, region of memory of distribution are deposited a counter mapping table, transmit the first address value of described counter mapping table to the FIFO buffer module by dynamic binary translator, catch the first address of this counter mapping table by the FIFO buffer module, from the first in first out buffer zone module, get the first address of this counter mapping table then by the subdivision module;
Described counter mapping table comprises: source architecture programmable counter and conventional counter, wherein: source architecture programmable counter item is an item of depositing the source architecture programmable counter first address value of each target fundamental block, and what the conventional counter item was deposited is the Counter Value of corresponding source architecture program counter value.
The 3rd goes on foot, moves successively each target fundamental block and corresponding save command thereof, this storage instruction triggers the FIFO buffer module, the counter first address value of the source architecture executable program of each target fundamental block is stored in the FIFO buffer module, and the subdivision module is taken out the input of the Counter Value of described source architecture executable program as the subdivision module from buffer zone module;
The 4th step, subdivision module obtain the Counter Value of described source architecture executable program from the first in first out buffer zone module, this Counter Value is deposited in first register in the comparison module in the subdivision module, simultaneously, deposit in the comparison module in the subdivision module in second register from the counter mapping table carries sources architecture program counter value of local internal memory according to hash function, then to the comparison that conflicts of the value in first register and second register;
Described local internal memory is meant: on the multi-purpose computer in order to the physical memory of storage FIFO buffer module and subdivision module.
Described conflict relatively is meant: when result relatively equates, just upgrade the Counter Value of local internal memory; Unequal as result relatively, judged whether that again conflict takes place: when clashing, processing then conflicts; When not clashing, source architecture program counter value is write the Counter Value that goes in the corresponding local internal memory and upgrade correspondence;
Described conflict is handled and is meant: the value in first register is written in the next unequal memory address of 16 place values afterwards in the local internal memory of the second register correspondence;
Described renewal is meant: if upgrade for the first time, then write 1 in the counter item of relevant register mapping table, if not upgrading for the first time, then the value to the counter item of former register mapping table adds 1.
The present invention has improved the method for traditional collection subdivision information, compared with prior art collect subdivision information by storage instruction and counter mapping table of maintenance of inserting a complex mechanism in each target fundamental block in the executable program of source, use two hardware modules to form the hardware components of this system, finish the collection work of the subdivision information of whole subdivision system with the software and hardware cooperating design method of less hardware spending, thereby can intactly collect subdivision information accurately with less system overhead, thereby improve the performance of total system greatly.
Description of drawings
Fig. 1 is the overall framework figure of native system.
Fig. 2 is the storage instruction of PowerPC architecture.
Fig. 3 is a subdivision module logical schematic.
Fig. 4 is the counter mapping table.
Embodiment
Below embodiments of the invention are elaborated, present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
The general structure of subdivision information collection system is divided into two parts as shown in Figure 1: present embodiment comprises: comprising: the memory mapping load-on module, search module, the target cache module, metainstruction target fundamental block module, target instruction target word target fundamental block module, hyperlink target fundamental block module, the context handover module, optimal module, the counter mapping table, FIFO buffer module and subdivision module, wherein: the memory mapping load-on module with search module and be connected and can carry out the initial address message (IAM) of target fundamental block in the binary source program with transmission, searching module is connected with metainstruction target fundamental block module with transmission translation judgement information with the context handover module, metainstruction piece module is connected with transmission objectives fundamental block information with target instruction target word target fundamental block module, target instruction target word target fundamental block module is connected with the FIFO buffer module with transmission objectives fundamental block first address information with hyperlink target fundamental block module respectively, hyperlink target fundamental block module is connected with the context handover module with transmission first address chain information, the context handover module is connected with the transmission objectives storage address information with the target cache module, optimal module is connected with target cache sum counter mapping table and transmits process information to be optimized, the FIFO buffer module is connected with the subdivision module with transmission sources programmable counter value information, and the subdivision module is connected with transmission sources programmable counter value information with the counter mapping table.
Judgment value of storage in the described translation judgement information, the information whether on behalf of the target instruction target word target fundamental block corresponding with the source program Counter Value, this judgment value translated
Described hyperlink target fundamental block module generates the first address chain information with the link of the first address in the target fundamental block first address information after receiving target fundamental block first address information.
As Fig. 2, Fig. 3 and shown in Figure 4, present embodiment is achieved by following steps:
1) executable program that loads MIPS architecture (front-end architecture, the reduced instruction level microprocessor that has MIPS company to develop) obtains the entry address of this executable program in the process space of CrossBit.Then, be the unit partition program with the target fundamental block, a target fundamental block is beginning with the instruction of a jump instruction or system call address pointed usually, is end with next bar jump instruction.Finish after the division of target fundamental block, insert the storage instruction of a complex structure in each target fundamental block, the form of save command as shown in Figure 2.Wherein, the value in source-register territory is for loading the local register number of each target fundamental block first address source architecture program counter value, and the value in address register territory is the register number that is mounted with buffer zone module first address value, and the value of side-play amount is zero.After being to have been obtained to be mounted with the register number of first address source architecture program counter value of target fundamental block by CrossBit, save command determines where inserting of target fundamental block that specifically this save command is inserted into article one location of instruction place after the instruction of register number of the first address source architecture program counter value that contains the target fundamental block.This register number satisfies by its registers in the CrossBit.
2) in CrossBit, distribute a region of memory to deposit a counter mapping table, the counter mapping table as shown in Figure 4, the counter mapping table comprises two of active architecture programmable counter and conventional counter, source architecture programmable counter item is an item of depositing each target fundamental block first address source architecture program counter value, and what the conventional counter item was deposited is Counter Value.Before the special translating purpose fundamental block, in CrossBit, embed the first address value that a bit of assembly code sequence is come the transfer counter mapping table, this section code is only carried out once, the last item of this segment assembly code is the save command of target architecture, and wherein the value in source-register territory is the first address of counter mapping table.
Wherein conventional counter mt_baseaddr variable has been deposited the first address value of counter mapping table, and the FIFO_baseaddr variable has been deposited the first address of fifo buffer.This section embeds assembly code:
__asm__(
“：lwz％％r9，％0\n\t”
“：stw％％r9，％1\n\t”
：”m”(mt_baseaddr)，“m”(FIFO_baseaddr)
)
Obtain the first address value of this counter mapping table by the subdivision module, the subdivision module as shown in Figure 3, the value that the subdivision module is got from buffer zone module for the first time is exactly the first address of counter mapping table, in the subdivision module, preserve this and be worth in the register, thereby can guarantee the search operation of ensuing source architecture program counter value.
3) when program is carried out the save command that inserts, this instruction triggers buffer zone module, the first address source architecture program counter value of each target fundamental block is stored in the buffer zone module, and the size of this buffer zone module is made as 4K inlet, and each inlet is 32bit (position) size.The subdivision module is taken out this source architecture program counter value from buffer zone module, leave in first register, add that according to back 16 a hash function value of getting each source architecture program counter value the value of counter mapping table first address searches source architecture program counter value corresponding in the counter mapping table and whether equate with the source architecture program counter value of getting from buffer zone module; If equate, then upgrade the Counter Value in the register mapping table of the second register intermediate value correspondence; If it is unequal, back 16 values (the 16th to the 31st in the end greatly) that compare the source architecture program counter value in first register and second register again, if back 16 place values are unequal, then conflict does not take place, source architecture program counter value in this first register is write in the corresponding list item of counter mapping table, and the value that the corresponding counts device is set is 1, if back 16 of two source architecture program counter value relatively equate, then conflict takes place, and is written in the unequal internal memory of next back 16 value in the local internal memory.Because the subdivision information of collecting is generally as the formation condition of superblock and path trace, and superblock and path trace all are in a very little zone, therefore the probability that clashes is very little, and several to tens command interval is arranged between each adjacent target fundamental block first address source architecture program counter value, so can be written to the source architecture program counter value that conflict is arranged in the next address of above-mentioned conflict address.
4) in the program process, after the subdivision information collection of a target fundamental block finishes, the Counter Value and the preset threshold of the corresponding target fundamental block in the counter mapping table are compared, if it is littler then jump to the subsequent target fundamental block and continue to carry out than threshold value, if variable surpasses threshold value, then generate corresponding superblock or path trace, thereby concentrate the dynamic optimization that carries out program.
Present embodiment comes the more execution number of times of fresh target fundamental block by the subdivision module, the software section of subdivision collection system utilizes this information to adjust the position of target fundamental block, couple together and constitute superblock or generation pass tracing (tracking) carrying out target fundamental block that frequency surpasses threshold value, thereby can utilize the subdivision system quicken total system operation, finish the collection work of the subdivision information of whole subdivision system with the software and hardware cooperating design method of less hardware spending, thereby can intactly collect subdivision information accurately with less system overhead, thereby improve the performance of total system greatly.
Claims (10)
1. subdivision information collection system, it is characterized in that, comprise: the memory mapping load-on module, search module, the target cache module, metainstruction target fundamental block module, target instruction target word target fundamental block module, hyperlink target fundamental block module, the context handover module, optimal module, the counter mapping table, FIFO buffer module and subdivision module, wherein: the memory mapping load-on module with search module and be connected and can carry out the initial address message (IAM) of target fundamental block in the binary source program with transmission, searching module is connected with metainstruction target fundamental block module with transmission translation judgement information with the context handover module, metainstruction piece module is connected with transmission objectives fundamental block information with target instruction target word target fundamental block module, target instruction target word target fundamental block module is connected with the FIFO buffer module with transmission objectives fundamental block first address information with hyperlink target fundamental block module respectively, hyperlink target fundamental block module is connected with the context handover module with transmission first address chain information, the context handover module is connected with the transmission objectives storage address information with the target cache module, optimal module is connected with target cache sum counter mapping table and transmits process information to be optimized, the FIFO buffer module is connected with the subdivision module with transmission sources programmable counter value information, and the subdivision module is connected with transmission sources programmable counter value information with the counter mapping table.
2. subdivision information collection system according to claim 1 is characterized in that, judgment value of storage in the described translation judgement information, the information whether on behalf of the target instruction target word target fundamental block corresponding with the source program Counter Value, this judgment value translated.
3. subdivision information collection system according to claim 1 is characterized in that, described hyperlink target fundamental block module generates the first address chain information with the link of the first address in the target fundamental block first address information after receiving target fundamental block first address information.
4. the collection method according to arbitrary described subdivision information collection system in the claim 1 to 3 is characterized in that, may further comprise the steps:
The first step, source architecture executable program is carried out the memory mapping loading processing, be that unit divides the source architecture executable program after loading with the target fundamental block then, generate the target fundamental block, between last two instructions of each target fundamental block, insert the storage instruction of a complex structure reduced instruction level microprocessor;
Second step, region of memory of distribution are deposited a counter mapping table, transmit the first address value of described counter mapping table to the FIFO buffer module by dynamic binary translator, catch the first address of this counter mapping table by the FIFO buffer module, from the first in first out buffer zone module, get the first address of this counter mapping table then by the subdivision module;
The 3rd goes on foot, moves successively each target fundamental block and corresponding save command thereof, this storage instruction triggers the FIFO buffer module, the counter first address value of the source architecture executable program of each target fundamental block is stored in the FIFO buffer module, and the subdivision module is taken out the input of the Counter Value of described source architecture executable program as the subdivision module from buffer zone module;
The 4th step, subdivision module obtain the Counter Value of described source architecture executable program from the first in first out buffer zone module, this Counter Value is deposited in first register in the comparison module in the subdivision module, simultaneously, deposit in the comparison module in the subdivision module in second register from the counter mapping table carries sources architecture program counter value of local internal memory according to hash function, then to the comparison that conflicts of the value in first register and second register.
5. according to the collection method of arbitrary described subdivision information collection system in the claim 4, it is characterized in that, described target fundamental block is meant: the instruction of pointing to the address with a jump instruction is beginning, is the code of one section source architecture executable program of end with next bar jump instruction.
6. according to the collection method of arbitrary described subdivision information collection system in the claim 4, it is characterized in that, described counter mapping table comprises: source architecture programmable counter and conventional counter, wherein: source architecture programmable counter item is an item of depositing the source architecture programmable counter first address value of each target fundamental block, and what the conventional counter item was deposited is the Counter Value of corresponding source architecture program counter value.
7. according to the collection method of arbitrary described subdivision information collection system in the claim 4, it is characterized in that described local internal memory is meant: on the multi-purpose computer in order to the physical memory of storage FIFO buffer module and subdivision module.
8. according to the collection method of arbitrary described subdivision information collection system in the claim 4, it is characterized in that described conflict relatively is meant:, just upgrade the Counter Value of local internal memory when result relatively equates; Unequal as result relatively, judged whether that again conflict takes place: when clashing, processing then conflicts; When not clashing, source architecture program counter value is write the Counter Value that goes in the corresponding local internal memory and upgrade correspondence.
According to Claim 8 in the collection method of arbitrary described subdivision information collection system, it is characterized in that described conflict is handled and is meant: the value in first register is written in the next unequal memory address of 16 place values afterwards in the local internal memory of the second register correspondence.
According to Claim 8 in the collection method of arbitrary described subdivision information collection system, it is characterized in that described renewal is meant: if upgrade for the first time, then 1 counter that writes the relevant register mapping table.In, if not upgrading for the first time, then the value to the counter item of former register mapping table adds 1.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103713909A (en) * | 2014-01-22 | 2014-04-09 | 扬州大学 | Java program package profiling method for generating package diagram |
| CN109324838A (en) * | 2018-08-31 | 2019-02-12 | 深圳市元征科技股份有限公司 | Execution method, executive device and the terminal of SCM program |
| CN112100054A (en) * | 2020-08-12 | 2020-12-18 | 北京大学 | Data management and control oriented program static analysis method and system |
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| US20070104053A1 (en) * | 2005-11-04 | 2007-05-10 | Hsin-Cheng Chen | Method for controlling an optical disc drive to resume interrupted recording on an optical disc, circuit thereof, and optical disc drive capable of resuming interrupted recording on an optical disc |
| US9041713B2 (en) * | 2006-11-28 | 2015-05-26 | International Business Machines Corporation | Dynamic spatial index remapping for optimal aggregate performance |
| US7725657B2 (en) * | 2007-03-21 | 2010-05-25 | Intel Corporation | Dynamic quality of service (QoS) for a shared cache |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103713909A (en) * | 2014-01-22 | 2014-04-09 | 扬州大学 | Java program package profiling method for generating package diagram |
| CN109324838A (en) * | 2018-08-31 | 2019-02-12 | 深圳市元征科技股份有限公司 | Execution method, executive device and the terminal of SCM program |
| CN109324838B (en) * | 2018-08-31 | 2022-05-10 | 深圳市元征科技股份有限公司 | Execution method and execution device of single chip microcomputer program and terminal |
| CN112100054A (en) * | 2020-08-12 | 2020-12-18 | 北京大学 | Data management and control oriented program static analysis method and system |
| CN112100054B (en) * | 2020-08-12 | 2021-07-20 | 北京大学 | Data management and control oriented program static analysis method and system |
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