CN101667049B - Voltage reference circuit with micro power consumption - Google Patents

Abstract

The invention discloses a voltage reference circuit with micro power consumption, comprising a depletion type NMOS transistor M2, an enhanced NMOS transistor M5, an enhanced NMOS transistor M3 and a resistor R2. The circuit has extremely-low power consumption, simple structure and chip area saving. The circuit is free from a starting circuit, the depletion type NMOS transistor M2 can be conducted under the condition that VGS is equal to 0 and can provide extremely low current (nA grade); the current flows through the enhanced NMOS transistor M5 and generates constant grid-source voltage on the enhanced NMOS transistor M5; and the voltage is a voltage reference. The circuit consumes extremely low current (about 850nA) and can meet the requirement of low power consumption design.

Description

Voltage reference circuit with micro power consumption

Technical field

The present invention relates to a kind of voltage reference circuit, particularly voltage reference circuit with micro power consumption.

Background technology

With reference to Fig. 2, document " a kind of design [J] of subthreshold type bootstrapping bandgap voltage reference; Chinese integrated circuit; 2008,109, p51-54 " discloses a kind of voltage reference circuit, this circuit is by enhancement mode PMOS transistor M1, enhancement mode PMOS transistor M2, enhancement mode PMOS transistor M3, enhancement mode nmos pass transistor M4, enhancement mode nmos pass transistor M5, enhancement mode nmos pass transistor M6, enhancement mode nmos pass transistor M7, positive-negative-positive triode Q1, resistance R 1, resistance R 2, resistance R 3 are formed.The source electrode of enhancement mode PMOS transistor M1, enhancement mode PMOS transistor M2, enhancement mode PMOS transistor M3 connects positive supply VDD, and grid connects together.The drain electrode of enhancement mode PMOS transistor M1 connects the upper end of resistance R 1, and the lower end of resistance R 1 connects the drain electrode of enhancement mode nmos pass transistor M4, and the grid of enhancement mode nmos pass transistor M4 is connected to the upper end of resistance R 1, and source electrode is connected to negative supply VSS.Grid and the drain electrode of enhancement mode PMOS transistor M2 link together, and drain electrode connects the drain electrode of enhancement mode nmos pass transistor M5.The grid of enhancement mode nmos pass transistor M5 is connected to the lower end of resistance R 1, and the source electrode of enhancement mode nmos pass transistor M5 is connected to negative supply VSS.The drain electrode of enhancement mode PMOS transistor M3 is connected with an end of resistance R 2, and the other end of resistance R 2 connects the emitter of positive-negative-positive triode Q1, and the base stage of positive-negative-positive triode Q1 and collector link together and be connected to negative supply VSS.The last termination positive supply VDD of resistance R 3, the drain electrode of following termination enhancement mode nmos pass transistor M7, grid and the drain electrode of enhancement mode nmos pass transistor M7 link together, and source electrode connects negative supply VSS.The drain electrode of enhancement mode nmos pass transistor M6 connects positive supply VDD, and grid connects the lower end of resistance R 3, and source electrode is connected to the upper end of resistance R 1.The upper end of resistance R 2 is the exit point of voltage reference.The transistorized substrate of all enhancement mode PMOS all is connected to positive supply VDD, and the substrate of all enhancement mode nmos pass transistors all is connected to negative supply VSS.

Enhancement mode PMOS transistor M1 and enhancement mode PMOS transistor M2 all are operated in the saturation region, and its breadth length ratio can be made as (W/L) ₁: (W/L) ₂=P: 1.Enhancement mode nmos pass transistor M4 and enhancement mode nmos pass transistor M5 are operated in sub-threshold region, and its breadth length ratio can be made as (W/L) ₅: (W/L) ₄=N: 1.Resistance R 1 both end voltage V _R1Provide by (1) formula:

V _R1＝V _GS4-V _GS5 (1)

V in the formula _GS4The gate source voltage of expression enhancement mode nmos pass transistor M4, V _GS5The gate source voltage of expression enhancement mode nmos pass transistor M5.

Because enhancement mode nmos pass transistor M4 and enhancement mode nmos pass transistor M5 all are operated in sub-threshold region, so the gate source voltage of enhancement mode nmos pass transistor M4 and enhancement mode nmos pass transistor M5 uses (2) formula and (3) formula to represent respectively:

$V_{\mathrm{GS}4}=n\·V_T\·\ln \frac{I_4}{{(W/L)}_4}---\left(2\right)$

$V_{\mathrm{GS}5}=n\·V_T\·\ln \frac{I_5}{{(W/L)}_5}---\left(3\right)$

I in the formula ₄, I ₅Be respectively the drain current of enhancement mode nmos pass transistor M4, enhancement mode nmos pass transistor M5, V _TBe thermal voltage, n is the subthreshold value factor.Because I ₄: I ₅=P: 1 (enhancement mode PMOS transistor M1 and enhancement mode PMOS transistor M2 form current mirror), (W/L) ₅: (W/L) ₄=N: 1, can get resistance R 1 both end voltage V by (1) formula, (2) formula, (3) formula simultaneous _R1Satisfy the condition of (4) formula:

V _R1＝nV _Tln(N·P) (4)

Electric current I on the resistance R 1 _R1Satisfy the condition of (5) formula:

$I_{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H2009100235909E00012.png"\; state="\{\{state\}\}">R</figure-callout>}1}=\frac{V_{R1}}{R1}=\frac{n{V}_T\ln (N\&CenterDot;P)}{R1}---\left(5\right)$

This electric current after enhancement mode PMOS transistor M2 and enhancement mode PMOS transistor M3 current mirror coupled, the electric current I among the enhancement mode PMOS transistor M3 ₃Satisfy the condition of (6) formula:

$I_3=\frac{{(W/L)}_3}{{(W/L)}_2}\&CenterDot;\frac{n{V}_T\ln (N\&CenterDot;P)}{R1}---\left(6\right)$

So, voltage reference V _RefSatisfy the condition of (7) formula:

$V_{\mathrm{ref}}=n{V}_T\frac{{(W/L)}_3}{{(W/L)}_2}\&CenterDot;\frac{R2}{R1}\ln (N\&CenterDot;P)+V_{\mathrm{bel}}---\left(7\right)$

V wherein _RefThe output voltage of expression voltage reference, V _BelThe base-emitter voltage of expression triode Q1.

Enhancement mode nmos pass transistor M6, enhancement mode nmos pass transistor M7 and resistance R 3 are formed start-up circuit.Before the circuit start, the electric current of enhancement mode PMOS transistor M1, enhancement mode PMOS transistor M2 and enhancement mode PMOS transistor M3 is zero, and the last terminal voltage of resistance R 1 is negative supply VSS.During circuit start, the branch road that resistance R 3 and enhancement mode nmos pass transistor M7 form provides current potential for the grid of enhancement mode nmos pass transistor M6, because the source potential of enhancement mode nmos pass transistor M6 is negative supply VSS, enhancement mode nmos pass transistor M6 conducting, provide noble potential, enhancement mode nmos pass transistor M4 conducting for the grid of enhancement mode nmos pass transistor M4.There has been current potential the upper end of resistance R 1 after the circuit balancing, causes the threshold voltage of the gate source voltage of enhancement mode nmos pass transistor M6 less than enhancement mode nmos pass transistor M6, enhancement mode nmos pass transistor M6 by, start-up course is finished, start-up circuit is ineffective.

By reasonably being worth for the relative parameters setting in (7) formula, can make V _RefAcquisition is near zero-temperature coefficient, but the shortcoming of this circuit is to need start-up circuit, and complex structure, and will consume the electric current of about 4.5uA, start-up circuit current sinking still after startup is finished can not well satisfy requirement simple in structure, little power consumption.

Summary of the invention

In order to overcome prior art voltage reference circuit power consumption height, baroque deficiency, the invention provides a kind of voltage reference circuit with micro power consumption, this circuit does not need start-up circuit, and depletion type nmos transistor M2 is at V _GS2Be conducting under=0 the situation, constant electric current is provided, this electric current enhancement mode nmos pass transistor M5 that flows through produces constant gate source voltage on enhancement mode nmos pass transistor M5, and this voltage is voltage reference.The main effect of enhancement mode nmos pass transistor M3 is electric current to be provided for when circuit start right half branch road, produces the grid voltage that enhancement mode nmos pass transistor M5 conducting needs.Circuitry consumes utmost point low current can satisfy the requirement of low power dissipation design.

The technical solution adopted for the present invention to solve the technical problems: a kind of voltage reference circuit with micro power consumption, enhancement mode nmos pass transistor M5, resistance R 2, it is characterized in that, also comprise depletion type nmos transistor M2, enhancement mode nmos pass transistor M3, the drain electrode of depletion type nmos transistor M2 connects positive supply VDD, and grid connects source electrode, source electrode connects the drain electrode of enhancement mode nmos pass transistor M5, and substrate connects source electrode.The grid of enhancement mode nmos pass transistor M5 connects the upper end of resistance R 2, and source electrode connects power supply negative terminal VSS, and substrate connects source electrode.The drain electrode of enhancement mode nmos pass transistor M3 connects positive supply VDD, and grid connects the grid of depletion type nmos transistor M2, and source electrode connects the upper end of resistance R 2, and substrate connects source electrode.The lower end of resistance R 2 connects negative supply VSS.Resistance R 2 upper ends are the exit point of voltage reference.

The invention has the beneficial effects as follows: 1) circuit power consumption is extremely low.This circuit utilizes depletion type nmos transistor at V _GSThe characteristic of steady current can be provided under=0 the situation, provide the steady current of nA level, produce stable voltage reference at the grid of enhancement mode nmos pass transistor M5 by depletion type nmos transistor M2.And general circuit can not produce the steady current of nA level, also just can not obtain the extremely low voltage reference circuit of power consumption.The about 850nA electric current of circuitry consumes of the present invention, and the about 4.5uA electric current of the circuitry consumes of prior art, circuit power consumption of the present invention has only 19% of prior art; 2) save chip area.This circuit structure is simple, does not need start-up circuit, can obviously reduce number of transistors.When circuit powers on, because depletion type NMOS is at V _GSBut yet conducting under=0 the situation, circuit do not need other start-up circuit can produce voltage reference, and the circuit of prior art must add start-up circuit, otherwise circuit can not reach matching point.

Below in conjunction with drawings and Examples the present invention is elaborated.

Description of drawings

Fig. 1 is the circuit diagram of the embodiment of the invention 1.

Fig. 2 is the circuit diagram of prior art voltage reference circuit.

Embodiment

Embodiment 1: with reference to Fig. 1, the present embodiment voltage reference circuit is made up of a depletion type nmos transistor M2, enhancement mode nmos pass transistor M5, enhancement mode nmos pass transistor M3 and resistance R 2.The drain electrode of depletion type nmos transistor M2 connects positive supply VDD, and grid connects source electrode, and source electrode connects the drain electrode of enhancement mode nmos pass transistor M5, and substrate connects source electrode.The grid of enhancement mode nmos pass transistor M5 connects the upper end of resistance R 2, and source electrode connects negative supply VSS, and substrate connects source electrode.The drain electrode of enhancement mode nmos pass transistor M3 connects positive supply VDD, and grid connects the grid of depletion type nmos transistor M2, and source electrode connects the upper end of resistance R 2, and substrate connects source electrode.The lower end of resistance R 2 connects negative supply VSS.Resistance R 2 upper ends are the exit point of voltage reference.

The source electrode of depletion type nmos transistor M2, enhancement mode nmos pass transistor M5 and enhancement mode nmos pass transistor M3 is connected with substrate, reducing bulk effect, thereby reduces the threshold voltage of metal-oxide-semiconductor.This voltage reference circuit does not need additional start-up circuit.When circuit powered on, enhancement mode nmos pass transistor M5 was in cut-off state, and depletion type nmos transistor M2 is at V _GS2But also conducting under=0 the situation, GuN1Chu is a noble potential, enhancement mode nmos pass transistor M3 conducting this moment, electric current by positive supply VDD through enhancement mode nmos pass transistor M3, resistance R 2 to negative supply VSS, on resistance R 2, produce pressure drop, V _RefBegin to rise from zero potential, also conducting thereupon of enhancement mode nmos pass transistor M5, circuit finally reaches stable duty.Exportable stable, the voltage reference V of temperature influence not of circuit _Ref

For depletion type nmos transistor M2, its saturated drain current I flows through ₂Satisfy the condition of (11) formula:

I ₂＝K ₂(V _GS2-V _TD) ² (11)

K in the formula ₂The conductivity of expression depletion type nmos transistor M2, V _GS2The grid of expression depletion type nmos transistor M2 and the voltage between the source electrode, V _TDThe threshold voltage of expression depletion type nmos transistor M2.The saturated drain current I of enhancement mode nmos pass transistor M5 ₅Satisfy the condition of (12) formula:

I ₅＝K ₅(V _GS5-V _TE) ² (12)

K in the formula ₅The conductivity of expression enhancement mode nmos pass transistor M5, V _GS5The grid of expression enhancement mode nmos pass transistor M5 and the voltage between the source electrode, V _TEThe threshold voltage of expression enhancement mode nmos pass transistor M5.

Because I ₂=I ₅, V _GS2=0, so can get voltage reference V by (11) formula and (12) formula simultaneous _Ref=V _GS5Satisfy the condition of (13) formula:

$V_{\mathrm{ref}}=V_{\mathrm{GS}5}=\sqrt{\frac{K_2}{K_5}}\&CenterDot;\left|V_{\mathrm{TD}}\right|+V_{\mathrm{TE}}---\left(13\right)$

By (13) formula as can be seen, the temperature characterisitic of voltage reference only is subjected to depletion type nmos transistor M2 and two transistorized parameter influences of enhancement mode nmos pass transistor M5, K ₂, K ₅, V _TD, V _TEAll be the function of temperature, V _TD, V _TEBy the process conditions decision, K is set ₂And K ₅Value can obtain the voltage reference of approximate zero temperature coefficient.V _RefSize directly by V _TD, V _TEDetermine.The V that in different technology, obtains _RefValue meeting change, this is because the V of different process correspondence _TD, V _TEAlso different.Depletion type nmos transistor M2 links to each other with substrate with the source electrode of enhancement mode nmos pass transistor M5, can reduce V _TD, V _TEThereby, obtain littler voltage reference.

Obtaining voltage reference V _RefThe time, also determined the electric current of right half branch road of circuit, the electric current I of enhancement mode nmos pass transistor M3 ₃Satisfy the condition of (14) formula:

$I_3=\frac{V_{\mathrm{ref}}}{R2}---\left(14\right)$

Simultaneously by the saturated drain current formula of nmos pass transistor I as can be known ₃Satisfy the condition of (15) formula:

I ₃＝K ₃(V _GS3-V _TE) ²＝K ₃(V _N1-V _ref-V _TE) ² (15)

K wherein ₃The conductivity of expression enhancement mode nmos pass transistor M3, V _GS3The grid of expression enhancement mode nmos pass transistor M3 and the voltage between the source electrode, V _TEThe threshold voltage of expression enhancement mode nmos pass transistor M3.

The electric current of enhancement mode nmos pass transistor M3 is by V _RefDetermine with R2, work as V as can be known by (16) formula _RefAfter determining with R2, V _N1And K ₃Inversely proportional relation.The precondition that obtains (11) formula is that depletion type nmos transistor M2 is in the operate in saturation district, also is the condition that three terminal voltages of depletion type nmos transistor M2 should satisfy (16) formula:

V _GS2-V _TD＜VDD-V _N1 (16)

V _N1Must satisfy (16) formula, otherwise can cause depletion type nmos transistor M2 to be operated in linear zone, (13) formula is just incorrect to the derivation of voltage reference at this moment.So in circuit design, K ₃Be provided with and must guarantee V _N1Current potential satisfies (16) formula.

Claims (1)

1. voltage reference circuit with micro power consumption, enhancement mode nmos pass transistor M5, resistance R 2, it is characterized in that, also comprise depletion type nmos transistor M2, enhancement mode nmos pass transistor M3, the drain electrode of depletion type nmos transistor M2 connects positive supply VDD, grid connects source electrode, source electrode connects the drain electrode of enhancement mode nmos pass transistor M5, substrate connects source electrode, and the grid of enhancement mode nmos pass transistor M5 connects the upper end of resistance R 2, and source electrode connects negative supply VSS, substrate connects source electrode, the drain electrode of enhancement mode nmos pass transistor M3 connects positive supply VDD, and grid connects the grid of depletion type nmos transistor M2, and source electrode connects the upper end of resistance R 2, substrate connects source electrode, and the lower end of resistance R 2 connects negative supply VSS.

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