CN102609027B - Band-gap reference voltage source circuit - Google Patents
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- CN102609027B CN102609027B CN 201210088717 CN201210088717A CN102609027B CN 102609027 B CN102609027 B CN 102609027B CN 201210088717 CN201210088717 CN 201210088717 CN 201210088717 A CN201210088717 A CN 201210088717A CN 102609027 B CN102609027 B CN 102609027B
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Abstract
An embodiment of the invention discloses a band-gap reference voltage source circuit which comprises a first p-channel metal oxide semiconductor (PMOS) pipe, a second PMOS pipe, a third PMOS pipe, a fourth PMOS pipe, a first NPN type triode, a second NPN type triode, a first resistor and a second resistor. An error amplifier is not applied to the band-gap reference voltage source circuit, the influence of offset voltage and noise of the error amplifier on a system are omitted, and the power consumption and the area are reduced. In addition, independent generation of a branch circuit is not adopted in an output branch circuit of reference voltage Vref, the influence of the offset voltage caused by current image failure is avoided to some extent, and the area and the power consumption are reduced.
Description
Technical field
The invention belongs to integrated circuit power supply technique field, relate in particular to a kind of bandgap voltage reference circuit.
Background technology
In Analogous Integrated Electronic Circuits or mixed-signal designs field, reference voltage source is a very important module, for system provides voltage reference and current reference.Along with the raising of circuit level, reference voltage source also more and more is integrated into chip internal, to reduce system cost.
Traditional reference voltage source relies on the bandgap voltage reference circuit to produce usually, as shown in Figure 1, this bandgap voltage reference circuit comprises error amplifier, PMOS mirror current source, PNP pipe and resistance, and reference voltage is generated by the independent branch road (marking with dotted line in Fig. 1) of the mirror current source that comprises PMOS pipe PM3, resistance R 2 and PNP pipe Q3 usually.
But above-mentioned bandgap voltage reference circuit has number of drawbacks: because it comprises error amplifier and corresponding biasing circuit, therefore have the bigger problem of area; The offset voltage of error amplifier self and noise also can be added to reference voltage output end Vref, and, because reference voltage is generated separately by a branch road, therefore, the mirror image mismatch between PM3, PM1 and PM2 mirror current source also can strengthen the offset voltage of reference voltage in this bandgap voltage reference circuit.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of bandgap voltage reference circuit, to solve the problem that area is big, offset voltage is big that exists in the prior art.
For achieving the above object, the invention provides following technical scheme:
A kind of bandgap voltage reference circuit comprises PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, a NPN type triode, the 2nd NPN type triode, first resistance and second resistance; Wherein:
Source electrode and the substrate of described PMOS pipe and the 2nd PMOS pipe insert supply voltage;
The grid of the grid of a described PMOS pipe and the 2nd PMOS pipe is connected to the drain electrode of source electrode and described the 2nd PMOS pipe of described the 4th PMOS pipe simultaneously;
The drain electrode of a described PMOS pipe is connected to the source electrode of described the 3rd PMOS pipe;
The substrate of the substrate of described the 3rd PMOS pipe and the 4th PMOS pipe inserts supply voltage;
The grid of the grid of described the 3rd PMOS pipe and the 4th PMOS pipe is connected to the drain electrode of collector and described the 4th PMOS pipe of described the 2nd NPN type triode simultaneously;
The drain electrode of described the 3rd PMOS pipe is connected to the collector of a described NPN triode by described second resistance;
The base stage of the base stage of a described NPN type triode and the 2nd NPN type triode is connected to the collector of a described NPN type triode;
The grounded emitter of a described NPN type triode;
The emitter of described the 2nd NPN type triode is by described first resistance eutral grounding;
The drain electrode of described the 3rd PMOS pipe is as reference voltage output end.
Preferably, described PMOS pipe is identical with the device parameters of the 2nd PMOS pipe; Described the 3rd PMOS pipe is identical with the device parameters of the 4th PMOS pipe; The emitter area ratio of a described NPN type triode and the 2nd NPN triode is n:1,
Wherein,
Expression is differentiated, and Vbe1 represents the base-emitter junction voltage of a NPN type triode, and T represents absolute temperature, and q represents electronic charge, and K represents Boltzmann constant, and R2 represents the resistance value of second resistance, and R1 represents the resistance value of first resistance.
Therefore this shows that beneficial effect of the present invention is: do not use error amplifier in the bandgap voltage reference circuit disclosed by the invention, saved the offset voltage of error amplifier self and noise to the influence of system, and saved power consumption and area; In addition, the output branch road of reference voltage V ref does not adopt a branch road to produce separately, the influence of the offset voltage of also having avoided current mirror excuse me, but I must be leaving now to a certain extent causing, and saved area and power consumption.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural drawing of existing bandgap voltage reference circuit;
Fig. 2 is the structural drawing of a kind of bandgap voltage reference circuit disclosed by the invention;
Fig. 3 is the temperature variant Tcm curve map of the reference voltage V ref of bandgap voltage reference circuit shown in Figure 2.
Embodiment
For quote and know for the purpose of, the hereinafter explanation of the technical term of Shi Yonging, write a Chinese character in simplified form or abridge and be summarized as follows:
PMOS, positive channel Metal Oxide Semiconductor, the PMOS pipe refers to n type substrate, p raceway groove, by the mobile metal-oxide-semiconductor that transports electric current in hole.
The invention discloses a kind of bandgap voltage reference circuit, in order to solve the problem that the area that exists in the prior art is big, offset voltage is big.Its basic ideas are: utilize the positive temperature coefficient (PTC) of base-emitter voltage difference between the NPN pipe be in the amplification region, the negative temperature coefficient of base-emitter voltage, design a kind of low-power consumption, low area, low maladjustment voltage, low noise, bandgap voltage reference circuit simple for structure.
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Referring to Fig. 2, Fig. 2 is the structural drawing of a kind of bandgap voltage reference circuit disclosed by the invention.Comprise a PMOS pipe PM1, the 2nd PMOS pipe PM2, the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4, a NPN type triode Q1, the 2nd NPN type triode Q2, first resistance R 1 and second resistance R 2.Wherein:
Source electrode and the substrate of the one PMOS pipe PM1 and the 2nd PMOS pipe PM2 insert supply voltage VDDA.The grid of the grid of the one PMOS pipe PM1 and the 2nd PMOS pipe PM2 is connected to the drain electrode of source electrode and the 2nd PMOS pipe PM2 of the 4th PMOS pipe PM4 simultaneously.The drain electrode of the one PMOS pipe PM1 is connected to the source electrode of the 3rd PMOS pipe PM3.The substrate of the substrate of the 3rd PMOS pipe PM3 and the 4th PMOS pipe PM4 inserts supply voltage VDDA.The grid of the grid of the 3rd PMOS pipe PM3 and the 4th PMOS pipe PM4 is connected to the collector of the 2nd NPN type triode Q2 and the drain electrode of the 4th PMOS pipe PM4 simultaneously.The drain electrode of the 3rd PMOS pipe PM3 is connected to the collector of a NPN triode Q1 by second resistance R 2.The base stage of the base stage of the one NPN type triode Q1 and the 2nd NPN type triode Q2 is connected to the collector of a NPN type triode Q1.The grounded emitter of the one NPN type triode Q1.The emitter of the 2nd NPN type triode Q2 is by first resistance R, 1 ground connection.The drain electrode of the 3rd PMOS pipe PM3 is as reference voltage V ref output terminal.
In implementation process, can make PMOS pipe PM1 identical with the device parameters of the 2nd PMOS pipe PM2 by design, make the 3rd PMOS pipe PM3 identical with the device parameters of the 4th PMOS pipe PM4, and make the emitter area ratio of a NPN triode Q1 and the 2nd NPN triode Q2 be n:1.
The principle of work of above-mentioned bandgap voltage reference circuit is as follows:
When bandgap voltage reference circuit operate as normal, all PMOS pipes, NPN type triode are in saturation region and amplification region, and PM1, PM2 and PM3, PM4 form the cascade mirror current source.
Because the effect of current mirror, the branch current Id1 of PM1 place branch road equates with the branch current Id2 of PM2 place branch road, and Id1=Id2=Id, and wherein, Id is the channel current of PM1 and PM3.(therefore β=Ic/Ib) bigger flows through the collector current Ic1 of Q1 and flows through the collector current Ic2 approximately equal of Q2, Ic1 ≈ Ic2=Id because the current amplification factor β of Q1 and Q2.
Therefore, the base-emitter voltage difference dVbe of Q2, Q1 is:
dVbe=Vbe2-Vbe1=(KT/q)*ln(Ic2/Is2)-(KT/q)*ln(Ic1/Is1)
=(KT/q) * ln (Is1/Is2) (formula 1)
Wherein, Vbe1 is the base-emitter junction voltage of Q1, Vbe2 is the base-emitter junction voltage of Q2, K represents Boltzmann constant, and T is absolute temperature, and q represents electronic charge, Is1 is the reverse saturation current of Q1, Is2 is the reverse saturation current of Q2, and Ic1 is the collector current of Q1, and Ic2 is the collector current of Q2.
Because the emitter area of Q1, Q2 ratio is n:1, thus Is1/Is2=n/1, so formula 1 can be reduced to:
DVbe=Vbe2-Vbe1=(KT/q) * ln (n) (formula 2)
Above-mentioned dVbe is the voltage difference of resistance R 1, and the electric current I R1 that therefore flows through resistance R 1 satisfies following formula:
IR1=IQ1=IQ2=Id=(KT/q) * ln (n)/R1 (formula 3)
Therefore the voltage difference VR2 at resistance R 2 two ends satisfies following formula:
VR2=Id*R2=(KT/q) * ln (n) * R2/R1 (formula 4)
Reference voltage source Vref satisfies following formula:
Vref=Vbe1+VR2=Vbe1+ (KT/q) * ln (n) * R2/R1 (formula 5)
5 pairs of temperature T of formula are differentiated, for:
Because it is above-mentioned
Be positive temperature coefficient (PTC), (K/q) be negative temperature coefficient, therefore the resistance value of the numerical value of n and resistance R 1, R2 suitably is set according to formula 6, and can make Vref is zero at normal temperature formula 6 in season, thereby guarantees to have minimum reference voltage rate of change in operating temperature range.
In resistance one timing of resistance R 1 and resistance R 2, order
Thereby making formula 6 is zero.
Bandgap voltage reference circuit shown in Figure 2 itself has the function of single-stage error amplifier.Because PM4 forms the diode form, therefore can think that source electrode and the drain electrode of PM4 are error amplification output terminal, the source electrode of PM4 is linked to each other with the grid of PM1, PM2, drain electrode with PM4 simultaneously links to each other with the grid of PM3, PM4, to form feedback loop, the voltage signal that error is amplified is converted into current signal, thereby keeps the establishment of formula (5) and formula (6).
Therefore to sum up, in bandgap voltage reference circuit shown in Figure 2, do not use error amplifier, saved the offset voltage of error amplifier self and noise to the influence of system, and saved power consumption and area; In addition, the output branch road of reference voltage V ref is produced separately by a branch road (PM3 branch road) not as shown in Figure 1, the influence of the offset voltage of also having avoided current mirror excuse me, but I must be leaving now to a certain extent causing, and saved area and power consumption.
The temperature variant Tcm curve of the reference voltage V ref of bandgap voltage reference circuit shown in Figure 2 can be referring to Fig. 3.As seen, in the ordinary course of things, the conventional bandgap reference source of the supply-voltage rejection ratio of reference voltage V ref of the present invention, temperature coefficient Tcm and employing error amplifier shown in Figure 1 and PMOS mirror current source is close.
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the disclosed device of embodiment, because it is corresponding with the embodiment disclosed method, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (2)
1. a bandgap voltage reference circuit is characterized in that, comprises PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, a NPN type triode, the 2nd NPN type triode, first resistance and second resistance; Wherein:
Source electrode and the substrate of described PMOS pipe and the 2nd PMOS pipe insert supply voltage;
The grid of the grid of a described PMOS pipe and the 2nd PMOS pipe is connected to the drain electrode of source electrode and described the 2nd PMOS pipe of described the 4th PMOS pipe simultaneously;
The drain electrode of a described PMOS pipe is connected to the source electrode of described the 3rd PMOS pipe;
The substrate of the substrate of described the 3rd PMOS pipe and the 4th PMOS pipe inserts supply voltage;
The grid of the grid of described the 3rd PMOS pipe and the 4th PMOS pipe is connected to the drain electrode of collector and described the 4th PMOS pipe of described the 2nd NPN type triode simultaneously;
The drain electrode of described the 3rd PMOS pipe is connected to the collector of a described NPN triode by described second resistance;
The base stage of the base stage of a described NPN type triode and the 2nd NPN type triode is connected to the collector of a described NPN type triode;
The grounded emitter of a described NPN type triode;
The emitter of described the 2nd NPN type triode is by described first resistance eutral grounding;
The drain electrode of described the 3rd PMOS pipe is as reference voltage output end.
2. circuit according to claim 1 is characterized in that: described PMOS pipe is identical with the device parameters of the 2nd PMOS pipe; Described the 3rd PMOS pipe is identical with the device parameters of the 4th PMOS pipe; The emitter area ratio of a described NPN type triode and the 2nd NPN triode is n:1,
Wherein,
Expression is differentiated, and Vbe1 represents the base-emitter junction voltage of a NPN type triode, and T represents absolute temperature, and q represents electronic charge, and K represents Boltzmann constant, and R2 represents the resistance value of described second resistance, and R1 represents the resistance value of described first resistance.
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| CN103399612B (en) * | 2013-07-16 | 2015-04-15 | 江苏芯创意电子科技有限公司 | Resistance-less bandgap reference source |
| CN207601665U (en) * | 2017-10-12 | 2018-07-10 | 宁波德晶元科技有限公司 | A kind of novel band-gap reference source circuit |
| CN111796624B (en) * | 2020-07-27 | 2022-02-18 | 东南大学 | CMOS voltage reference circuit with ultrahigh power supply ripple rejection ratio |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5083079A (en) * | 1989-05-09 | 1992-01-21 | Advanced Micro Devices, Inc. | Current regulator, threshold voltage generator |
| US5155394A (en) * | 1991-02-12 | 1992-10-13 | National Semiconductor Corporation | Bias distribution circuit and method using FET and bipolar |
| CN102033564A (en) * | 2009-09-25 | 2011-04-27 | 精工电子有限公司 | Reference voltage circuit |
| CN102200797A (en) * | 2010-03-23 | 2011-09-28 | 精工电子有限公司 | Reference voltage circuit |
| CN202502430U (en) * | 2012-03-29 | 2012-10-24 | 北京经纬恒润科技有限公司 | Bandgap reference voltage source circuit |
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2012
- 2012-03-29 CN CN 201210088717 patent/CN102609027B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5083079A (en) * | 1989-05-09 | 1992-01-21 | Advanced Micro Devices, Inc. | Current regulator, threshold voltage generator |
| US5155394A (en) * | 1991-02-12 | 1992-10-13 | National Semiconductor Corporation | Bias distribution circuit and method using FET and bipolar |
| CN102033564A (en) * | 2009-09-25 | 2011-04-27 | 精工电子有限公司 | Reference voltage circuit |
| CN102200797A (en) * | 2010-03-23 | 2011-09-28 | 精工电子有限公司 | Reference voltage circuit |
| CN202502430U (en) * | 2012-03-29 | 2012-10-24 | 北京经纬恒润科技有限公司 | Bandgap reference voltage source circuit |
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Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |
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