CN101661202B

CN101661202B - Active array substrate

Info

Publication number: CN101661202B
Application number: CN2009101707644A
Authority: CN
Inventors: 林汉涂; 杨智钧; 廖金阅; 陈建宏
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2008-04-07
Filing date: 2008-04-07
Publication date: 2011-05-04
Anticipated expiration: 2028-04-07
Also published as: CN101661202A

Abstract

The invention discloses an active array substrate which comprises a substrate provided with at least one groove, at least one scanning line, at least one data line vertical to the scanning line, at least one thin film transistor electrically connected with the corresponding scanning line and the data line, at least one pixel electrode connected with the thin film transistor, and a connecting cushion electrode positioned in the groove.

Description

Active array substrate

Patented claim of the present invention for the applicant in the application number of on April 7th, 2008 application be 200810090659.5, denomination of invention divides an application for the application for a patent for invention of " thin film transistor (TFT), active array substrate and manufacture method thereof ".

Technical field

The invention relates to a kind of active array substrate and manufacture method thereof, particularly have an active array substrate that lead is imbedded the structure of substrate about a kind of.

Background technology

At improving rapidly of multimedia society, be indebted to the tremendous progress of semiconductor subassembly or display device mostly.With regard to display, have that high image quality, space utilization efficient are good, (Thin Film Transistor Liquid Crystal Display TFT-LCD) becomes the main flow in market to the Thin Film Transistor-LCD of low consumpting power, advantageous characteristic such as radiationless gradually.

Thin Film Transistor-LCD (TFT-LCD) mainly is made of thin film transistor (TFT) array, colored filter and liquid crystal layer, and wherein thin film transistor (TFT) array is formed by the thin film transistor (TFT) of a plurality of arrayed and with the pixel capacitors (pixel electrode) of the corresponding configuration of each thin film transistor (TFT).And thin film transistor (TFT) is used as the switch module of liquid crystal display.In addition, in order to control other pixel unit, usually can be via scan wiring (scan line) and data wiring (date line) choosing specific pixel, and by suitable operating voltage is provided, to show the video data of corresponding this pixel.

Along with being dimensioned to of Thin Film Transistor-LCD is increasing, the problem of capacitance-resistance sluggishness (RC delay) is just more and more serious, so the research that the lead of low resistance uses just becomes trend gradually.Wherein paid attention to the most, but can be produced problems, for example: the tack problem is arranged between (1) copper and glass in the technology of using copper conductor with the exploitation of copper conductor; (2) when copper is carried out etch process, have problems such as the residual or corner degree (taper) of copper is not good; (3) on carrying out copper conductor during the removing photoresistance technology of photoresistance, copper conductor is subject to the erosion of removing photoresistance agent; And the diffusion problem of (4) copper, for example be problems such as vertical direction puncture or parallel direction extension.

In addition, the active array substrate of Thin Film Transistor-LCD, by the multilayer layer body form and at present how the slimming Thin Film Transistor-LCD also be another trend, so how the slimming Thin Film Transistor-LCD is the subject under discussion of another investigation.

Summary of the invention

The invention provides a kind of thin film transistor (TFT), have a grid, have preferable tack between this grid and the substrate, wherein this substrate has a groove to hold this grid.

The invention provides a kind of thin film transistor (TFT); have one source pole and drain electrode; the material of source electrode and drain electrode is exemplified as copper, molybdenum, titanium, chromium or combinations thereof; a protective seam that is positioned in this source electrode and/or the drain electrode has opening; make discontinuous conductor layer contact with this source electrode and/or drain electrode via this opening, the material of this conductor layer is exemplified as copper, silver, aluminium or combinations thereof.

The invention provides a kind of thin film transistor (TFT), comprising: a substrate has a groove; One grid is positioned at this groove; One gate insulation layer is positioned on this grid, and wherein at least partly this gate insulation layer is positioned at this groove; One channel layer is positioned on this gate insulation layer; And an one source pole and a drain electrode, be positioned on this channel layer and respectively to both sides that should grid.

The invention provides a kind of active array substrate, comprise above-mentioned thin film transistor (TFT).

The invention provides a kind of method of making thin film transistor (TFT), comprising: a substrate is provided; Form a patterning photoresist layer in this substrate, this patterning photoresist layer has an opening; With this patterning photoresist layer is shielding, and this substrate of etching is to form a groove; Form a conductor material layer in this patterning photoresist layer and this substrate comprehensively; Removal is positioned at this conductor material layer on this patterning photoresist layer; Remove this patterning photoresist layer; Form a grid in this groove; Form a gate insulation layer on this grid, wherein at least partly this gate insulation layer is positioned at this groove; Form a channel layer on this gate insulation layer; And form an one source pole and a drain electrode, be positioned on this channel layer and respectively to both sides that should grid.

The invention provides a kind of method of making active array substrate, comprising: a substrate is provided; Form a patterning photoresist layer in this substrate, this patterning photoresist layer; With this patterning photoresist layer is shielding, and this substrate of etching is to form a groove; Form a conductor material layer in this patterning photoresist layer and this substrate comprehensively; Removal is positioned at this conductor material layer on this patterning photoresist layer; Remove this patterning photoresist layer; Form at least the one scan line in this groove; Form at least one data line, vertical with this sweep trace; Form at least one thin film transistor (TFT), with corresponding this sweep trace and the electric connection of this data line, this thin film transistor (TFT) comprises a gate insulation layer, and wherein at least partly this gate insulation layer is positioned at this groove; And form at least one pixel capacitors, be connected with this thin film transistor (TFT).

The purpose of this invention is to provide a kind of thin thin film transistor (TFT).

The purpose of this invention is to provide a kind of thin thin film transistor (TFT), have preferable tack between the grid of thin film transistor (TFT) and the substrate.

The purpose of this invention is to provide a kind of thin thin film transistor (TFT), the drain electrode of this thin film transistor (TFT) is a sandwich construction, and drain electrode can not punctured to doping semiconductor layer or channel layer.

The method for making that the purpose of this invention is to provide a kind of thin film transistor (TFT), when avoiding removing photoresistance technology, the problem of removing photoresistance agent meeting etching grid, source electrode and/or drain electrode.

The method for making that the purpose of this invention is to provide a kind of active array substrate, when avoiding removing photoresistance technology, the problem of removing photoresistance agent meeting etching grid, connection gasket electrode, connection electrode, sweep trace, source electrode, drain electrode and/or data line.

For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.

Description of drawings

Figure 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A and 11A are the top view of manufacture method step correspondence of the active array substrate of one embodiment of the invention;

Figure 1B and 1C are respectively the sectional view of Figure 1A along profile line I-I ' and II-II ';

Fig. 2 B and 2C are respectively the sectional view of Fig. 2 A along profile line I-I ' and II-II ';

Fig. 3 B and 3C are respectively the sectional view of Fig. 3 A along profile line I-I ' and II-II ';

Fig. 4 B and 4C are respectively the sectional view of Fig. 4 A along profile line I-I ' and II-II ';

Fig. 5 B and 5C are respectively the sectional view of Fig. 5 A along profile line I-I ' and II-II ';

Fig. 6 B and 6C are respectively the sectional view of Fig. 6 A along profile line I-I ' and II-II ';

Fig. 7 B, 7C and 7D are respectively the sectional view of Fig. 7 A along profile line I-I ', II-II ' and III-III ';

Fig. 8 B, 8C and 8D are respectively the sectional view of Fig. 8 A along profile line I-I ', II-II ' and III-III ';

Fig. 9 B, 9C and 9D are respectively the sectional view of Fig. 9 A along profile line I-I ', II-II ' and III-III ';

Figure 10 B, 10C and 10D are respectively the sectional view of Figure 10 A along profile line I-I ', II-II ' and III-III ';

Figure 11 B, 11C and 11D are respectively the sectional view of Figure 11 A along profile line I-I ', II-II ' and III-III '; And

Figure 12 is a display panels of the present invention.

[primary clustering symbol description]

1 display panels

10 active assembly array substrates

100 substrates

101 patterning photoresist layers

102 patterning photoresist layers

110,110a, 110b conductor material layer

The 111a sweep trace

The common line of 111b

112 gate insulation layers

113 channel layers

114 doping semiconductor layers

115 protective seams

120 data lines

130 conductor material layers

131 conductor layers

132 connection electrode

133 conductor layers

140 pixel capacitors

141 guard electrodes

142 guard electrodes

20 subtend substrates

30 liquid crystal layers

C1, C2 groove

C3, C4, C5 contact the hole

The D drain electrode

The D1 drain electrode layer

The G grid

L connection gasket electrode

P1, P2 atmosphere electric paste etching

The S source electrode

The S1 source layer

S, s " direction

Embodiment

1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A and 11A are the corresponding top view of the step of manufacturing of one embodiment of the invention active array substrate, reach understanding for convenience of description, and top view optionally shows with perspective fashion.

Please refer to Figure 1A to Fig. 1 C.Figure 1B and 1C are respectively the sectional view of Figure 1A along profile line I-I ' and II-II '.What must pay special attention to is that the position that profile line I-I ' is corresponding is manufacturing active array substrate thin film transistor (TFT) place.Shown in Figure 1B and 1C figure, at first, provide substrate 100, in substrate 100, form patterning photoresist layer 101 then.

Please refer to Fig. 2 A to Fig. 2 C.Fig. 2 B and 2C are respectively the sectional view of Fig. 2 A along profile line I-I ' and II-II '.With this patterning photoresist layer 101 is shielding, and this substrate 100 of etching is to form groove C1 and C2, the corresponding follow-up formation grid of groove C1, data line and connection gasket electrode, and the common line of the corresponding follow-up formation of groove C2.Wherein this substrate 100 of etching is to utilize dry ecthing or wet etching with the step that forms this groove C1, C2, in the present embodiment, this dry ecthing comprises atmosphere electric paste etching (atmospheric plasmaetching) otherwise P1 is along direction s or with direction s that direction s ' is to this substrate 100 scannings and carry out etching mutually, and it is with low cost and simple starching etched advantage with atmospheric electricity.This substrate 100 of etching is not limited to the etch species or the etching direction that form this groove C1, C2.The degree of depth of groove C1, C2 is approximately 2000

(dust) is to 7000

(dust).Finishing 101 pairs of patterning photoresist layers after this step should groove C1, the lower surface at C2 place is undercut (under-cut).

Please refer to Fig. 3 A to Fig. 3 C.Fig. 3 B and 3C are respectively the sectional view of Fig. 3 A along profile line I-I ' and II-II '.Form a conductor material layer 110 in this patterning photoresist layer 101 and this substrate comprehensively, the material of conductor material layer 110 is exemplified as copper, silver, aluminium or combinations thereof, so corresponding pattern photoresist layer 101 and groove C1, C2 place have discontinuous conductor material layer 110, shown in Fig. 3 B, 3C, have conductor material layer 110a in the groove C1, have conductor material layer 110b on the patterning photoresist layer 101, have conductor material layer 110c (shown in Fig. 4 A) in the groove C2.Conductor material layer 110 also can be two-layer or three-decker in addition, for example ground floor is positioned in this substrate and a second layer is positioned on this ground floor or adds the 3rd layer and is positioned on this second layer, ground floor and/or three-layer-material are exemplified as copper, molybdenum, titanium, chromium or combinations thereof, and second layer material is exemplified as copper, silver, aluminium or combinations thereof.

Please refer to Fig. 4 A to 4C.Fig. 4 B and 4C are respectively the sectional view of Fig. 4 A along profile line I-I ' and II-II '.Removal is positioned at this conductor material layer 110b on this patterning photoresist layer 101, in the present embodiment, the step that removal is positioned at this conductor material layer 110b on this patterning photoresist layer 101 is to utilize gas-solid-state bombardment technology (gas-solid shooting) for example, the advantage of utilizing gas-solid-state bombardment technology is for omitting the conventional wires wet etching process, and because the cause that groove C1, C2 exist does not have the problem that lead remains in non-conductor section.

Please refer to Fig. 5 A to 5C.Fig. 5 B and 5C are respectively the sectional view of Fig. 5 A along profile line I-I ' and II-II '.Remove this patterning photoresist layer 101, so grid G, sweep trace 111a, connection gasket electrode L and common line 111b just are formed, the upper surface of grid G, sweep trace 111a, connection gasket electrode L and common line 111b is arcuation substantially, because grid G, sweep trace 111a, connection gasket electrode L and common line 111b are arranged in groove C1, C2, so when utilizing the removing photoresistance agent to remove patterning photoresist layer 101, grid G, sweep trace 111a, connection gasket electrode L and common line 111b just are difficult for suffering erosion.Shown in Fig. 5 A, except the part of grid G, sweep trace 111a, connection gasket electrode L and common line 111b, substrate 100 is exposed.

Please refer to Fig. 6 A to Fig. 6 C.Fig. 6 B and 6C are respectively the sectional view of Fig. 6 A along profile line I-I ' and II-II '.Form gate insulation layer 112 in grid G, sweep trace 111a, connection gasket electrode L, common line 111b and substrate 100, at least partly gate insulation layer 112 is positioned at groove C1, C2; Form channel layer 113 then on the gate insulation layer 112 at corresponding thin film transistor (TFT) place, the material of channel layer 113 is exemplified as semiconductor material, for example is amorphous silicon.Next, both sides selectivity corresponding to grid G forms doping semiconductor layer 114, then, source layer S1 and drain electrode layer D1 are on doping semiconductor layer 114, source layer S1 and drain electrode layer D1 are positioned on this channel layer 113 and respectively to both sides that should grid G, and forming data line 120 and data connection gasket electrode (not indicating) simultaneously, the material of source layer S1, drain electrode layer D1 and data line 120 is exemplified as copper, molybdenum, titanium, chromium or combinations thereof.After finishing this step, thin film transistor (TFT) just is done, and grid G is connected with corresponding scanning line 111a, and source layer S1 is connected with corresponding data line 120.

Please refer to Fig. 7 A to Fig. 7 D.Fig. 7 B, 7C and 7D are respectively the sectional view of Fig. 7 A along profile line I-I ', II-II ' and III-III '.Form comprehensively protective seam 115 in data line 120, source layer S1, drain electrode layer D1 with door insulation course 112 on; on this protective seam 115, form patterning photoresist layer 102 then; in regular turn shown in Fig. 7 B to Fig. 7 D, contact hole C3, the contact hole C4 on the connection gasket electrode L of thin film transistor (TFT)-pixel capacitors 140 that a plurality of openings of patterning photoresist layer 102 are corresponding follow-up and the contact hole C5 on the data line 120 and be exposed to small part protective seam 115.

Please refer to Fig. 8 A to Fig. 8 D.Fig. 8 B, 8C and 8D are respectively the sectional view of Fig. 8 A along profile line I-I ', II-II ' and III-III '.Next; utilize similar above-mentioned formation groove C1; the notion of C2; with this patterning photoresist layer 102 is shielding; this protective seam 115 of etching is to form contact hole C3 and C5 to expose drain electrode layer D1 and data line 120 respectively; and this protective seam 115 of etching simultaneously exposes connection gasket electrode L to contact hole C4 with door insulation course 112 with formation; form contact hole C3; the step of C4 and C5 is to utilize dry ecthing or wet etching; in the present embodiment; this dry ecthing comprises that atmosphere electric paste etching (atmospheric plasma etching) P2 carries out etching along direction s or the direction s ' opposite with direction s scanning; it is with low cost and simple starching etched advantage with atmospheric electricity; etch species or etching direction are not limited to, and finish the patterning photoresist layer 102 corresponding contact hole C3 after this step; the lower surface at C4 and C5 place is undercut (under-cut).

Please refer to Fig. 9 A to Fig. 9 D.Fig. 9 B, 9C and 9D are respectively the sectional view of Fig. 9 A along profile line I-I ', II-II ' and III-III '.Form conductor material layer 130 on patterning photoresist layer 102, drain electrode layer D1, connection gasket electrode L and data line 120 comprehensively, drain electrode layer D1 and be positioned at the drain D that conductor layer 131 on the drain electrode layer D1 is defined as thin film transistor (TFT) wherein, conductor material layer on the connection gasket electrode L is a connection electrode 132, is conductor layer 133 on the data line 120.The material of conductor material layer 130 is exemplified as copper, silver, aluminium or combinations thereof.Optionally, also can form conductor material layer on source layer S1 makes it become the source S of sandwich construction., certainly, conductor material layer 130 also can be double-decker, and method is for forming ground floor in regular turn and the second layer gets final product, and ground floor is exemplified as copper, silver, aluminium or combinations thereof, and the second layer is exemplified as copper, molybdenum, titanium, chromium or combinations thereof.Because have source layer S1 or drain electrode layer D1 between conductor material layer 130 and doping semiconductor layer 114 or the channel layer 113, the generation probability can be avoided or be reduced to the problem that influences doping semiconductor layer 114 or channel layer 113 downwards so conductor material layer 130 punctures.

Please refer to Figure 10 A to Figure 10 D.Figure 10 B, 10C figure and 10D figure are respectively the sectional view of Figure 10 A along profile line I-I ', II-II ' and III-III '.Removal is positioned at this conductor material layer 130 on this patterning photoresist layer 102, in the present embodiment, the step that removal is positioned at this conductor material layer 130 on this patterning photoresist layer 102 is to utilize gas-solid-state bombardment technology (gas-solid shooting) for example, the advantage of utilizing gas-solid-state bombardment technology is for omitting the conventional wires wet etching process, and because the cause that contact hole C3, C4 and C5 exist does not have the problem that lead remains in non-conductor section.

Please refer to Figure 11 A to Figure 11 D.Figure 11 B, 11C and 11D are respectively the sectional view of Figure 11 A along profile line I-I ', II-II ' and III-III '.After utilizing the removing photoresistance agent to remove this patterning photoresist layer 102, shown in Figure 11 B, 11C and 11D, form pixel capacitors 140, guard electrode 141 and 142.Pixel capacitors 140, guard electrode 141 and 142 generation type can be comprehensive formation transparency conducting layer for example, are exemplified as tin indium oxide, indium zinc oxide or combinations thereof, utilize photoresistance exposure development etch process to form then.Pixel capacitors 140 is to contact with drain D to electrically connect by contact hole C3, and guard electrode 141 and 142 lays respectively on connection electrode 132 and the conductor layer 133.

So, active assembly array substrate 10 is just finished.Because having groove C1, C2, active assembly array substrate 10 holds lead, so but thinning active assembly array substrate 10, the conductor material problem that remains in non-conductor section also can solve in addition.

As shown in figure 12, display panels 1 comprises above-mentioned active assembly array substrate 10, subtend substrate 20 and is located in liquid crystal layer therebetween 30.Subtend substrate 20 is exemplified as colored filter substrate.

For the method for making active assembly array substrate 10, except each step of the foregoing description explanation, can optionally the preceding step of step of gate insulation layer 112 will be formed, make in existing mode, and do not form groove C1, C2, and only use as the step (corresponding diagram 6A to Figure 11 D) after the step of the formation gate insulation layer 112 in the above-mentioned embodiment explanation; Or, with the step after the step of formation gate insulation layer 112, make in existing mode, and only use as the step (corresponding Figure 1A to Fig. 5 C) after the step of the formation gate insulation layer 112 in the above-mentioned embodiment explanation generation type of reservation groove C1, C2.

Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.

Claims

1. active array substrate comprises:

One substrate has at least two grooves;

At least one sweep trace;

At least one data line is vertical with this sweep trace;

At least one thin film transistor (TFT) is with corresponding this sweep trace and the electric connection of this data line;

At least one pixel electrode is connected with this thin film transistor (TFT);

One connection gasket electrode; And,

One common line is arranged in a groove of these at least two grooves,

This sweep trace, this connection gasket electrode and a grid are arranged in another groove of these at least two grooves, and the upper surface of this grid, sweep trace, connection gasket electrode and common line is arcuation substantially.

2. active array substrate as claimed in claim 1, it is characterized in that, this sweep trace comprises that a ground floor is positioned in this substrate and a second layer is positioned on this ground floor, wherein the material of this second layer comprises copper, silver, aluminium or combinations thereof, and wherein the material of this ground floor comprises molybdenum, titanium, chromium or its combination.

3. active array substrate as claimed in claim 2 is characterized in that, this sweep trace comprises that also one the 3rd layer is positioned on this second layer, and the 3rd layer material comprises molybdenum, titanium, chromium or its combination.

4. active array substrate as claimed in claim 1 is characterized in that, also comprises:

One connection electrode is positioned on this connection gasket electrode; And,

One guard electrode is positioned on this connection electrode,

This connection gasket electrode and this sweep trace electrically connect, and are positioned at this another groove.

5. as claim 1 a described active array substrate, it is characterized in that, comprise that also a gate insulation layer is positioned on this connection gasket electrode, wherein at least partly this gate insulation layer is positioned at this another groove.