CN101645832B - Processing method of network data packets for virtual machine based on FPGA - Google Patents
Processing method of network data packets for virtual machine based on FPGA Download PDFInfo
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- CN101645832B CN101645832B CN200910083646XA CN200910083646A CN101645832B CN 101645832 B CN101645832 B CN 101645832B CN 200910083646X A CN200910083646X A CN 200910083646XA CN 200910083646 A CN200910083646 A CN 200910083646A CN 101645832 B CN101645832 B CN 101645832B
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Abstract
The invention relates to a processing method of network data packets for a virtual machine based on FPGA. The method comprises the following steps: unloading and filtering the data packets by FPGA hardware, transferring the data packets from PHY of a network card to MAC and a network filtering engine, filtering and allocating the data packets by the MAC and the network filtering engine, storing the data packets with the same virtual machine number in a corresponding memory queue, unloading and filtering the data packets in the memory queue by a protocol processor, rearranging and integrating the data packets in the same queue into a large data packet according to a port number, an IP address and a threading number, storing the large data packet in a large memory packet queue, and transmitting the large data packet to the virtual machine through a PCIe by a DMA controller when the large data packet in the large memory packet queue reaches a predetermined length. The method helps complete the work for unloading and filtering the data packets in the hardware, thus completely liberating a CPU and reducing CPU resource occupancy; and meanwhile the hardware processing speed is much higher than the software processing speed, thus greatly improving the network throughput speed, shortening the response time for data processing and reducing packet loss.
Description
Technical field
The utility model provides a kind of processing method of network packet, is specifically related to a kind of processing method of network data packets for virtual machine based on FPGA hardware.
Technical background
In the virtual machine network application, the packet overwhelming majority that is transferred to different virtual machine all is the small data packets about 1.5KB, be the application program of different port in the operating system these packet final purpose, application program is received that each packet all will respond and is handled this packet.In order to reduce the response times of application program, synthetic big packet of the data packet group of the same port that sequence number is continuous in the software, and then give application program and respond processing.But in each operating system, can exist several simultaneously even tens up to a hundred application programs are worked at the same time, and under the virtual machine network environment, have dozens or even hundreds of operating system again.Like this, need consume a large amount of cpu resources in order to make up these big bags, because cpu resource is consumed in a large number, also make the response time of packet increase, communication performance reduces.Especially in today that the 10G Ethernet is popularized gradually, CPU makes up the bottleneck that big bag has become network communication to the packet in the virtual machine network.
Summary of the invention
In order to solve above-mentioned shortcoming, reduce utilization rate and the response package time of CPU, the invention provides a kind of processing method of network data packets for virtual machine based on FPGA, be provided with FPGA on network interface card, described FPGA comprises: MAC module, network filtering engine, protocol processor, memory modules, describer engine, dma controller, PCIe module, flash module; Be characterised in that, create one group of former data packet queue and one group of new data packets formation in the described memory modules, described former data packet queue divides a reception area for a virtual machine, and described new data packing formation divides a reception area for each virtual machine, and described method adopts following steps:
A, network interface card are passed to described MAC module and network filtering engine with the packet that receives by the physical layer port of network interface card.
B, described MAC module and network filtering engine filter and send branch to the packet that receives, described MAC module filters out the virtual machine numbering of packet, described network filtering engine is assigned the packet that receives according to virtual machine numbering, will be stored in the packet of virtual machine numbering in the respective virtual machine reception area of former data packet queue of memory modules.
C, described protocol processor unload filtration to packet in the former packet receipts formation of memory modules, unloading filters out port numbers, IP address, the thread sequence number of described packet, packet in the same virtual machine reception area in the described former data packet queue is rearranged integration according to port numbers, IP address, thread serial number information, and the new data packets after will integrating is deposited in the respective virtual machine reception area of new data packets formation of described memory modules.
D, when the new data packets in the new data packets formation of described memory modules count to reach the predetermined length number after, described dma controller is uploaded to corresponding virtual machine with described new data packets by the PCIe module.
The present invention further optimization technical scheme is: describedly also be connected with SMBus based on the network filtering engine in the processing method of network data packets for virtual machine of FPGA, by SMBus FPGA realized Long-distance Control.
The present invention further optimization technical scheme is: describedly be connected with the PCIe module based on the Flash module in the processing method of network data packets for virtual machine of FPGA, the initial configuration information of described FPGA leaves in the Flash module.
The present invention further optimization technical scheme is: described memory modules based on the FPGA in the processing method of network data packets for virtual machine of FPGA adopts the DDR2 memory.
The present invention further optimization technical scheme is: described based on the employing of the Flash module in the processing method of network data packets for virtual machine of FPGA eeprom memory.
Beneficial effect of the present invention: utilize FPGA hardware quick, characteristics of high efficiency, the work that packet unloading is filtered is put into FPGA inside and finishes, liberated the operation of CPU fully, reduced the resource occupation of CPU, simultaneously since the processing speed of hardware-level far above the processing speed of software level, so improved the speed that network is handled up greatly, shortened the response time of data simultaneously, improve data packet transmission speed, avoided because the packet drop of long appearance of processing data packets response time, improve communication performance, especially in the virtual machine application network, saved resource waste greatly, improved data processing rate whole in the virtual machine network.
Accompanying drawing and description of drawings
FPGA inner function module structural representation among Fig. 1 the present invention;
The effect contrast figure of Fig. 2 the inventive method and prior art.
The memory modules subregion schematic diagram of FPGA among Fig. 3 the present invention
Embodiment
The present invention utilizes FPGA hardware characteristics fast and efficiently on the basis of existing technology, the work that the packet unloading is filtered directly is put into the thinking that finish FPGA inside, use the FPGA internal logic, the packet that receives is resequenced according to information such as different ports, IP addresses, the packet that satisfies condition is put in the same data queue, after arriving the data length of some, be uploaded to corresponding virtual machine.
As shown in Figure 1, the invention provides a kind of processing method of network data packets for virtual machine based on FPGA, FPGA is set on network interface card, and FPGA comprises: MAC module, network filtering engine, protocol processor, memory modules, describer engine, dma controller, PCIe module, Flash module; As shown in Figure 3, create one group of former data packet queue and one group of new data packets formation in memory modules, former data packet queue divides a reception area for each virtual machine, and new data packing formation divides a reception area for each virtual machine.
Wherein A, at first network interface card is passed to MAC module and network filtering engine with the packet that receives by the physical layer port of network interface card.
B, MAC module and network filtering engine filter and send branch to the packet that receives, the MAC module filters out the virtual machine numbering of packet, the network filtering engine is assigned the packet that receives according to virtual machine numbering, will be stored in the packet of virtual machine numbering in the respective virtual machine reception area of former data packet queue of memory modules.
C, protocol processor unload filtration to packet in the former packet receipts formation of memory modules, unloading filters out port numbers, IP address, the thread sequence number of described packet, packet in the same virtual machine reception area in the described former data packet queue is rearranged integration according to port numbers, IP address, thread serial number information, and the new data packets after will integrating is stored in the respective virtual machine reception area of new data packets formation of memory modules.
D, when the new data packets in the new data packets formation of described memory modules count to reach the predetermined length number after, described dma controller is uploaded to corresponding virtual machine with described new data packets by the PCIe module.
The network filtering engine of FPGA also is connected with SMBus (System Management Bus), by SMBus FPGA is realized Long-distance Control, the Flash module is connected with the PCIe module, the initial configuration information of FPGA leaves in the Flash module, the memory modules of FPGA of the present invention can adopt the DDR2 memory, and the Flash module can adopt eeprom memory.
As shown in Figure 2, be the effect contrast figure of the present invention and prior art, solid post represents to have the throughput of the big bag unloading of hardware, and open tubular column is represented the throughput less than the big bag unloading of hardware; Solid line represents to have the cpu busy percentage of the big bag unloading of hardware, and dotted line is represented the cpu busy percentage less than the big bag unloading of hardware.As can be seen from Figure 2, under the situation that FPGA hardware is arranged, it is nearly 100% that the throughput of network has improved, and the utilance of CPU drops to original 1/3.
Claims (5)
1. processing method of network data packets for virtual machine based on FPGA, be provided with FPGA on network interface card, described FPGA comprises: MAC module, network filtering engine, protocol processor, memory modules, describer engine, dma controller, PCIe module, flash module; Be characterised in that, create one group of former data packet queue and one group of new data packets formation in the described memory modules, described former data packet queue divides a reception area for each virtual machine, and described new data packing formation divides a reception area for each virtual machine, and described method adopts following steps:
A, network interface card are passed to described MAC module and network filtering engine with the packet that receives by the physical layer port of network interface card;
B, described MAC module and network filtering engine filter the packet that receives and assign, described MAC module filters out the virtual machine numbering of packet, described network filtering engine is assigned the packet that receives according to virtual machine numbering, will be stored in the packet of virtual machine numbering in the respective virtual machine reception area of former data packet queue of memory modules;
C, described protocol processor unload filtration to the packet in the former data packet queue of memory modules, unloading filters out port numbers, IP address, the thread sequence number of described packet, packet in the same virtual machine reception area in the described former data packet queue is rearranged integration according to port numbers, IP address, thread serial number information, and the new data packets after will integrating is stored in the respective virtual machine reception area of new data packets formation of described memory modules;
D, when the new data packets in the new data packets formation of described memory modules count to reach the predetermined length number after, described dma controller is uploaded to corresponding virtual machine with described new data packets by the PCIe module.
2. a kind of processing method of network data packets for virtual machine based on FPGA as claimed in claim 1 is characterized in that described network filtering engine also is connected with SMBus, by SMBus FPGA is realized Long-distance Control.
3. a kind of processing method of network data packets for virtual machine based on FPGA as claimed in claim 1 is characterized in that described Flash module is connected with the PCIe module, and the initial configuration information of described FPGA leaves in the Flash module.
4. a kind of processing method of network data packets for virtual machine based on FPGA as claimed in claim 1 is characterized in that: the memory modules of described FPGA adopts the DDR2 memory.
5. a kind of processing method of network data packets for virtual machine based on FPGA as claimed in claim 3 is characterized in that: described Flash module adopts eeprom memory.
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| CN102185672A (en) * | 2011-03-02 | 2011-09-14 | 浪潮(北京)电子信息产业有限公司 | Inter-process communication method and high-speed network equipment |
| CN103338230B (en) * | 2013-06-03 | 2016-03-30 | 广州天宁信息技术有限公司 | A kind of processing method of business datum and system |
| CN104753813B (en) * | 2013-12-27 | 2018-03-16 | 国家计算机网络与信息安全管理中心 | The method that DMA transmits message |
| CN103890728B (en) | 2013-12-31 | 2015-12-30 | 华为技术有限公司 | The method of live migration of virtual machine and server |
| CN105306241B (en) * | 2014-07-11 | 2018-11-06 | 华为技术有限公司 | A kind of service deployment method and network function accelerate platform |
| CN105260332B (en) * | 2015-09-09 | 2018-04-20 | 北京三未信安科技发展有限公司 | A kind of method and system stored in order to CPLD data packets |
| US20200301747A1 (en) * | 2016-03-31 | 2020-09-24 | Nec Corporation | Control method, control apparatus and server in network system |
| CN108540982B (en) * | 2017-03-06 | 2021-10-22 | 上海诺基亚贝尔股份有限公司 | Communication method and device for virtual base station |
| CN110825485A (en) * | 2018-08-07 | 2020-02-21 | 华为技术有限公司 | Data processing method, equipment and server |
| CN113810791B (en) * | 2021-09-22 | 2022-04-29 | 浙江锐文科技有限公司 | Method for improving intelligent network card/DPU network telemetering technology performance |
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