CN101645685A - Alternating current synchronous motor controller based on FPGA and control method thereof - Google Patents
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Abstract
The invention discloses an alternating current synchronous motor controller based on FPGA and a control method thereof. The feedback digital processing of a coder and a current sensor and the controlof the current operation of a motor are simultaneously carried out by FPGA; simultaneously, dynamic errors caused by the system error of the feedback current value and a common mode rejection ratio are reduced in the digital filtering of the current feedback sensor; in the feedback process, a polar duty ratio after digital filtering replaces the feedback current value for converting linear data, thereby avoiding the nonlinear processing in the converting process of the current value and the data errors due to multiplication computation; in the processes of the data logic computation and the processing of a current ring and a speed ring, the absolute value and the symbol bit of the data are used as a data combination, thereby simplifying the data processing of programming design; and in addition, a uniform synchronous clock is supplied in the control and renovating process of the speed ring and the current ring, thereby eliminating the errors caused by a time sequence problem in the data transmission process in the computation and the control of the current ring and the speed ring.
Description
Technical field
Invention relates to a kind of alternating current synchronous motor controller and control method thereof based on FPGA, belongs to the technical field of AC motor control.
Background technology
For traditional AC motor control design, adopt the special digital chip as the master control chip usually, the control chip of main flow is the DSP digital processing chip at present, is aided with the interface of other chip as data processing and communication simultaneously.This class master control chip can be realized comparatively complicated digital operation usually, but because the complexity of on-chip circuit causes single on the chip functions, in control, must abide by certain time sequence simultaneously, carry out multitasking at needs and adopt interrupt mode often, thereby cause the error on the control time.
For fpga chip, owing to adopt the means of software programming to realize placement-and-routing in the sheet, and do not exist set logical circuit can revise repeatedly on-chip circuit by the means of software simultaneously at chip internal, thereby make the control chip of designing have the multi-functional control action of the multi-process of realization, and then simplified the design of servo-drive control circuit.Aspect precision, because FPGA can carry out various static timing analysis to the module of programming after the placement-and-routing, thereby can revise the time of delay or the clock jitter shake of current circuit, and for the special digital chip because its on-chip circuit be set logical circuit, its sequential then becomes definite value after chip development is finished, the highest frequency that this type of chip of while uses circuit is lower than the fpga chip with price in some sense, so often be lower than the fpga chip with pricing tier on precision.Therefore fpga chip has very big development space as main control chip in the design of servo drive system.
Summary of the invention
The present invention seeks to provides a kind of hardware designs to simplify, have the alternating current synchronous motor controller and the control method thereof based on FPGA of more speed and accuracy data processing and control ability at the defective that prior art exists.
The present invention adopts following technical scheme for achieving the above object:
The present invention is based on the alternating current synchronous motor controller of FPGA, described ac synchronous motor input is connected in series power circuit and described controller successively, in the described ac synchronous motor rotating shaft photoelectric encoder is set, it is characterized in that described controller comprises master control circuit board and the interface circuit that is made of FPGA, wherein FPGA comprises coder module, the current filtering module, the polar switching module, the Clark conversion module, the Park conversion module, anti-Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, the speed ring pi regulator, the SVPWM data processing module, time sequence status modular converter and speed and Current Control synchronised clock module, interface circuit comprises current sensor input and SVPWM output interface and encoder interfaces, described photoelectric encoder connects the input of coder module by encoder interfaces, described power circuit exports the input of current filtering module to by its inner current sensor, the output of while SVPWM data processing module gets input with power circuit and is connected, the output of current filtering module is connected in series the polar switching module successively, the Clark conversion module, the Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, connect the input of SVPWM data processing module behind the anti-Park conversion module, connect the input of current PI adjuster behind the output of the coder module serial connection speed ring pi regulator and the turned position of current rotor is provided for Park and anti-Park conversion, the output of speed and Current Control synchronised clock module connects the SVPWM data processing module respectively, coder module, the current filtering module, the polar switching module, speed ring pi regulator module, the output of time sequence status modular converter connects coder module respectively, the current filtering module, the polar switching module, the Park conversion module, anti-Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, the speed ring pi regulator, the input of SVPWM data processing module and Clark conversion module.
The control method of described alternating current synchronous motor controller based on FPGA is characterized in that described control method is as follows:
Coder module: with described photoelectric encoder detect pulse signal that ac synchronous motor obtains through calculating ac synchronous motor in rotating physical location and the size and Orientation of actual feedback speed;
The current filtering module: the PWM duty cycle signals of the ac synchronous motor input current that described current sensor senses is obtained is handled through digital filtering, is converted to corresponding dutyfactor value;
Polar switching module: described dutyfactor value is converted to corresponding polar duty ratio according to the feedback current positive-negative polarity;
Clark conversion module: described polar duty ratio is synthesized and resolution process through space vector, be converted to the mark component of sitting quietly of polar duty ratio;
Park conversion module: the moving axes component value that the mark component value of sitting quietly of described polar duty ratio is converted to polar duty ratio;
Calibration processing module: the moving axes component value of described polar duty ratio is converted to corresponding electric current perunit value;
The speed ring pi regulator: target velocity and described actual feedback speed ratio by appointment obtain the velocity deviation amount, and logical operation is converted to the target current value of handing over shaft current through data with the velocity deviation amount;
Current PI adjuster and voltage transformation module: adopting the current PI adjuster is that described electric current perunit value compares and obtains the current deviation value with described target current value and feedback current value, and the employing voltage transformation module is converted to the voltage deviation value with the current deviation value;
Anti-Park conversion module: the mark component value of sitting quietly that voltage deviation value process is converted to the voltage deviation value;
SVPWM data processing module: the mark component value of sitting quietly of described voltage deviation value is regulated the processing of Time Calculation and overshoot through sector judgement computing, export corresponding pwm signal to power circuit and control described ac synchronous motor;
Time sequence status modular converter: will link together according to sequential logic with upper module by state machine FSM;
Speed and Current Control synchronised clock module: adopt the mode of increase and decrease counting to send synchronous control signal to SVPWM data processing module, coder module, current filtering module, polar switching module, speed ring pi regulator.
The invention has the advantages that and utilize FPGA multi-process disposal ability to carry out simultaneously that position, current sensor feedback digital are handled and when front motor operation control; In current feedback transducer digital filtering, reduced simultaneously because the systematic error of feedback current value and the dynamic error that common-mode rejection ratio causes; And the polar duty ratio after feedback element is utilized digital filtering replaces the feedback current value to carry out the data error that therefore the linear data conversion avoids Nonlinear Processing in the current value transfer process and multiplication to bring in calculating; The absolute value of data and sign bit have been simplified the data processing of Programming Design as data combination in the data logical calculated of electric current loop and speed ring and processing procedure; The error that causes owing to sequence problem in the data transmission procedure when providing unified synchronised clock to make by electric current loop and speed ring calculation control in addition in control between speed ring and electric current loop and the refresh process is eliminated, thereby makes AC motor control have higher controls reaction speed and data-handling capacity.
Description of drawings
Fig. 1 is controller hardware design principle figure;
Fig. 2 is current digital filtering principle figure;
Fig. 3 is synchronised clock and time sequence status transfer principle figure;
Fig. 4 is the electric current loop data processing method;
Fig. 5 is encoder position, velocity process module behavior emulation sequential result;
Fig. 6 handles behavior emulation sequential result for the current sensor digital filtering;
Fig. 7 is SVPWM data processing behavior emulation sequential result.
Embodiment
Be elaborated below in conjunction with the technical scheme of accompanying drawing to invention:
As Fig. 1, Fig. 3 and shown in Figure 4, alternating current synchronous motor controller based on FPGA, described ac synchronous motor input is connected in series power circuit and described controller successively, in the described ac synchronous motor rotating shaft photoelectric encoder is set, it is characterized in that described controller comprises master control circuit board and the interface circuit that is made of FPGA, wherein FPGA comprises coder module, the current filtering module, the polar switching module, the Clark conversion module, the Park conversion module, anti-Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, the speed ring pi regulator, the SVPWM data processing module, time sequence status modular converter and speed and Current Control synchronised clock module, interface circuit comprises current sensor input and SVPWM output interface and encoder interfaces, described photoelectric encoder connects the input of coder module by encoder interfaces, described power circuit exports the input of current filtering module to by its inner current sensor, the output of while SVPWM data processing module gets input with power circuit and is connected, the output of current filtering module is connected in series the polar switching module successively, the Clark conversion module, the Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, connect the input of SVPWM data processing module behind the anti-Park conversion module, connect the input of current PI adjuster behind the output of the coder module serial connection speed ring pi regulator and the turned position of current rotor is provided for Park and anti-Park conversion, the output of speed and Current Control synchronised clock module connects the SVPWM data processing module respectively, coder module, the current filtering module, the polar switching module, speed ring pi regulator module, the output of time sequence status modular converter connects coder module respectively, the current filtering module, the polar switching module, the Park conversion module, anti-Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, the speed ring pi regulator, the input of SVPWM data processing module and Clark conversion module.
Each functions of modules is as follows:
Module one, encoder position, velocity process: this module at first was converted to corresponding initial position angle by the hall signal that the mixed photoelectric encoder is sent before initial first Z pulse that powers on arrives, and when arriving, the Z pulse provides the current exact position of motor, generally this position is defaulted as the zero degree position that motor rotates a week, then pass through the frequency multiplication effect of FPGA clock data manager DCM, produce corresponding reference count frequency counting operation is carried out in the encoder quadruple pulse that the mixed photoelectric encoder sends, thereby calculate the current location and the velocity of rotation of current alternating current machine main shaft according to the M/T algorithm, simultaneously according to a of 4 double frequency pulses input, the b signal sequence is judged the rotation direction of electric machine main shaft.In this angle calculation process since the position deviation at the position deviation that alternating current machine and mixed photoelectric encoder are installed zero point when causing Z pulse arrival when the Z pulse arrives, this mechanical angle deviation can be counted, to remedy the dead-center position deviation.Concrete behavior simulation result as shown in Figure 5.
Module two, the current sensor digital filtering is handled: as shown in Figure 2, at first the reference frequency by 150MHz is carried out counting operation to the execution cycle and the carrier cycle of the pwm signal of current sensor IR2175 input, then respectively execution cycle and carrier cycle count pulse are carried out the digital filtering processing, thereby after the processing execution cycle data value and carrier cycle data value are carried out the duty ratio data value that division arithmetic calculates the pwm signal of current current sensor output.In this digital filtering processing procedure, need problem and the processing method handled as described below:
1) counting of execution cycle and carrier cycle: the frequency of the PWM waveform that current sensor IR2175 is exported is 130KHz, in order to calculate the size of its dutyfactor value more accurately, adopts the count frequency of 150MHz as the fundamental frequency count pulse among the design.The counting maximum number is about 1153, and is more moderate for this value of design of FPGA register.
2) digital filtering of carrier cycle is handled---and the filtering of single order homogenizing: the frequency of the PWM waveform that current sensor sent is 130KHz, but it is also asynchronous owing to the PWM waveform that sends in the counting process of reality with the fundamental frequency step-by-step counting, the carrier cycle numerical value of record will fluctuate about 130KHz, therefore adopt the method for single order homogenizing Filtering Processing to ask its mean value according to n subpulse numerical value and this numerical value before this moment of sample record herein.Powering on when initial because sampling for once and close with the numerical value of the current sensor of reality, rotating speed of motor does not reach the stabilized (steady-state) speed value when initial powering on simultaneously, so just begin directly to use sampled value powering on.
3) digital filtering of execution cycle is handled---dV/dt Filtering Processing: owing to the execution cycle is a dynamic change value, has no relation between the sampled value of previous moment and back one sampled value constantly, and the sampled value of current time has reflected the rotor current changing condition of this motor constantly, so can not use the homogenizing Filtering Processing as carrier cycle in the Filtering Processing process of reality.DV/dt is meant because the existence of common-mode rejection ratio, causes the deviate of sample rate current, and promptly the PWM dutyfactor value exported of current sensor will change.The existence of dV/dt will make the PWM duty ratio of surveying in motor uniform rotation process, produce fluctuation, thereby make the SVPWM control waveform of final output change, and then cause the fluctuation of motor speed.This fluctuation can't be eliminated fully in the real electrical machinery control procedure, at this in order to reduce the fluctuation of dutyfactor value, utilize the difference of the single order homogenizing value of carrier cycle and actual count value as the offset of execution cycle among the design, thereby can alleviate the fluctuation of duty ratio.
4) division arithmetic of duty ratio: this paper that finds the solution for duty ratio in design uses division to carry out computing, and division arithmetic not only can solve corresponding dutyfactor value can eliminate the error that temperature drift brings simultaneously.
The elimination problem that except above-mentioned 4, also has current sensor tolerance deviate, the duty ratio of the PWM that exports of current sensor is 50% o'clock in theory, be that the current deviation value is 0, but actual value is that 50% place is not 0 in duty ratio, cancellation scheme herein is to postpone electric current loop to calculate a bit of time when motor powers on, then the last brachium pontis with inverter disconnects, following brachium pontis is connected, promptly the dutyfactor value in this section current sensor output in the time should be 0%, and the current sensor of the on off state this moment by changing brachium pontis down between at this moment will measure the minor fluctuations of current sampling data, thereby can calculate the tolerance deviate of current sensor.Behavior simulation result in the over-current sensor digital filtering module is handled as shown in Figure 6.
Module three, the polar duty ratio data transaction: what export in the current sensor digital signal processing module is nonpolar duty ratio data value, this value does not have positive negativity, use 10 bit data latchs that the duty ratio data value is latched in the present design, this dutyfactor value and actual current value have certain linear, because the linear relationship scope of employed current sensor IR2175 duty ratio and current value is about 5% ~ 95%, carry out data transaction between duty ratio data and the current value so often adopt look-up table or multiply operation, yet this type of processing mode has obviously increased the actual use amount to the FPGA limited resources, consider simultaneously in whole electric current loop feedback path data computation processing procedure and be linear computational process that the polar duty ratio data that therefore signless duty ratio numerical value can be converted to symbol replace the actual feedback currents value to carry out linear data at the current feedback passage handling in order to reduce the resource of FPGA used.The conversion of concrete polar duty ratio is to be the boundary at zero point with 10 signless duty ratio numerical value with 2048, less than 2048 be 1 with its highest order as the sign bit value, all the other each bit data value are constant as current polar duty ratio data value, highest order sign bit value greater than 2048 is 0, and all the other each bit data value are constant as positive polar duty ratio data value.
Module four, Clark conversion: the three-phase current polar duty ratio data value of feedback is synthesized single-phase space complex vector current value, then carry out projection, promptly realize three-phase current i to the mark of sitting quietly
u, i
v, i
wTo the two-phase mark current i of sitting quietly
aWith i
bConversion.Since only the sampled electric current of V and W two-phase of current sensor IR2175 in the hardware designs of reality, so reference axis conversion formula herein is:
Module five, Park and anti-Park conversion: the IP kernel that this module adopts FPGA to carry in developing software---CORDIC rotation of coordinate nuclear carries out realize sitting quietly the mutual conversion between mark and the moving axes of multiplexing method.Below be the concrete operation formula of Park and anti-Park conversion, wherein i
dWith i
qBe moving axes current value, u
dWith u
qBe the mark magnitude of voltage of sitting quietly in the anti-Park conversion, u
AsWith u
BsBe the mark magnitude of voltage of sitting quietly in the anti-Park conversion:
The Park transformation for mula
Anti-Park transformation for mula
Module six, calibration is handled: owing to relate to nonlinear calculating and data processing in subsequent current pi regulator and voltage conversion processing, corresponding current value is carried out standardization handle so before current feedback channel data value is sent to the current PI adjuster, in advance the data value after the polar duty ratio linear process is converted to convenience that corresponding current value handles for subsequent calculations simultaneously, thereby be the electric current perunit value in the output of calibration processing module.
Module seven, current PI adjuster and voltage transitions are handled: consider that in design the differential adjusting mainly is the dynamic property at control, and use current sensor sample rate current deviate to the linearity of current feedback digital Filtering Processing and current feedback passage to calculate herein, the time that whole process spent is quite of short duration, so consider simultaneously and regulate the complexity of logical calculated and programming by differential a usage ratio integration is to the difference of current target value and value of feedback that promptly the current deviation value is regulated herein.Its basic PI adjusting computing formula is as follows:
While, so the current deviation value after regulating need be converted to magnitude of voltage, specifically the fundamental formular of calculating was as follows owing to the employing of electric current loop main channel is that the voltage control inverter is regulated algorithm:
u
q＝R
si
q+L
q(i
q(n)-i
q(n-1))+ω
rL
di
d+ψ
fω
r (5)
u
d＝R
si
d+L
d(i
d(n)-i
d(n-1))-ω
rL
qi
q (6)
Module eight, speed ring pi regulator: compare the output speed deviate by target velocity and feedback actual speed, then with the target current reference value of velocity deviation value through proportional and integral controller output current ring quadrature axis component with input.
In above-mentioned module seven and module eight processing procedures owing to have big difference between the desired value of initial input and the value of feedback, cause final output error amount because the effect of inertia of integration causes the distortion owing to overshoot of follow-up space vector SVPWM module conditioning signal output waveform, therefore must make restriction to regulating output valve, to avoid regulating distortion.
Module nine, SVPWM data processing: SVPWM is that control level calculating signal duration, ovennodulation judgement and the corresponding 6 road and bridge arm control of outputs such as processing and dead band processing pwm signal are judged, exported to the voltage deviation value that the space vector modulation scheme is about to import after the modulation treatment through the sector.Its behavior simulation result as shown in Figure 7.
Module ten, time sequence status conversion: because the design of FPGA separate modular, need above each module is connected in series according to certain time sequence so that realize control to alternating current machine.Adopt state machine FSM that the data processing and the calculating of each module are controlled among the design, shown in the realization order of each module among Fig. 3.
Module 11, speed and Current Control synchronised clock: in the design of whole AC motor control, in order to reach the requirement that final output meets the inverter switching device sequential, the current value of feedback path and the adjusting that velocity amplitude should remain unchanged in electric current loop and speed ring data computation and processing procedure simultaneously.The design is a benchmark with the switching frequency of inverter, SVPWM output signal refresh time, electric current loop calculating refresh time, speed regulator calculating refresh time, current sensor digital filtering is latched time and encoder feedback current electric machine main shaft position and the speed time of latching use unified synchronizing signal to control.Concrete synchronizing signal to each module as shown in Figure 3.
After algorithm was determined, then operation of data and the key that is treated as the actual program operation comprised the subject matter aspect two in data handling procedure in the processing procedure of upper module:
Choosing of 1 data bits, for data bits choose, though the figure place number is many more, but the EMS memory occupation amount of the high more corresponding FPGA of corresponding computational accuracy is also just big more, also increased simultaneously the complexity of calculating, because the computing of FPGA mainly is to realize by shifting function and add operation, so when complexity improves, so corresponding displacement and addition number of times also can correspondingly increase, corresponding to microscopic circuits, promptly increased the time between input variable and the shifter-adder output variable passage and may cause deviation with expected approach time.
The setting of 2 symbolic numbers, owing in the design process of electric current loop and speed ring, exist a large amount of plus and minus calculations, so the processing of signed number then becomes the key of result of calculation correctness, common method for designing is negative to be carried out negate add 1 operation, simultaneously with highest order as sign bit, just must differentiate and the operation that takes absolute value the operational data of input in each calculating process so, this will cause the increase of programing work amount.
At above two problems, the method for being taked is herein:
1 bottom data processing from feedback path begins its fetch bit number is calculated, promptly adopt method from bottom to top, because the data of the bottom are the electric current duty ratio data of current sensor feedback, therefore begin thus to operate the data figure place is handled.By the design of current sensor module above as can be known, in calculating, duty ratio considers that it is that span is 0 ~ 4095 that value precision and subsequent current feedback path convenience of calculation dutyfactor value are got no symbol 12 figure places.
2 for signed number, and then highest order is taken as sign bit, and other data bit all is taken as the absolute value of data.
The data processing method of concrete electric current loop and figure place are set as shown in Figure 6.
Claims (4)
1, a kind of alternating current synchronous motor controller based on FPGA, described ac synchronous motor input is connected in series power circuit and described controller successively, in the described ac synchronous motor rotating shaft photoelectric encoder is set, it is characterized in that described controller comprises master control circuit board and the interface circuit that is made of FPGA, wherein FPGA comprises coder module, the current filtering module, the polar switching module, the Clark conversion module, the Park conversion module, anti-Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, the speed ring pi regulator, the SVPWM data processing module, time sequence status modular converter and speed and Current Control synchronised clock module, interface circuit comprises current sensor input and SVPWM output interface and encoder interfaces, described photoelectric encoder connects the input of coder module by encoder interfaces, described power circuit exports the input of current filtering module to by its inner current sensor, the output of SVPWM data processing module is connected with the input of power circuit simultaneously, the output of current filtering module is connected in series the polar switching module successively, the Clark conversion module, the Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, connect the input of SVPWM data processing module behind the anti-Park conversion module, connect the input of current PI adjuster behind the output of the coder module serial connection speed ring pi regulator and the turned position of current rotor is provided for Park and anti-Park conversion, the output of speed and Current Control synchronised clock module connects the SVPWM data processing module respectively, coder module, the current filtering module, the polar switching module, speed ring pi regulator module, the output of time sequence status modular converter connects coder module respectively, the current filtering module, the polar switching module, the Park conversion module, anti-Park conversion module, the calibration processing module, electric current loop pi regulator and voltage transformation module, the speed ring pi regulator, the input of SVPWM data processing module and Clark conversion module.
2, the alternating current synchronous motor controller based on FPGA as claimed in claim 1 is characterized in that described photoelectric encoder is the mixed photoelectric encoder.
3, a kind of control method of the alternating current synchronous motor controller based on FPGA as claimed in claim 1 is characterized in that described control method is as follows:
Coder module: with described photoelectric encoder detect pulse signal that ac synchronous motor obtains through calculating ac synchronous motor in rotating physical location and the size and Orientation of actual feedback speed;
The current filtering module: the PWM duty cycle signals of the ac synchronous motor input current that described current sensor senses is obtained is handled through digital filtering, is converted to corresponding dutyfactor value;
Polar switching module: described dutyfactor value is converted to corresponding polar duty ratio according to the feedback current positive-negative polarity;
Clark conversion module: described polar duty ratio is synthesized and resolution process through space vector, be converted to the mark component of sitting quietly of polar duty ratio;
Park conversion module: the moving axes component value that the mark component value of sitting quietly of described polar duty ratio is converted to polar duty ratio;
Calibration processing module: the moving axes component value of described polar duty ratio is converted to corresponding electric current perunit value;
The speed ring pi regulator: target velocity and described actual feedback speed ratio by appointment obtain the velocity deviation amount, and logical operation is converted to the target current perunit value of handing over shaft current through data with the velocity deviation amount;
Current PI adjuster and voltage transformation module: adopting the current PI adjuster is that described electric current perunit value compares and obtains the current deviation value with described target current perunit value and feedback current value, and the employing voltage transformation module is converted to the voltage deviation value with the current deviation value;
Anti-Park conversion module: the mark component value of sitting quietly that voltage deviation value process is converted to the voltage deviation value;
SVPWM data processing module: the mark component value of sitting quietly of described voltage deviation value is regulated the processing of Time Calculation and overshoot through sector judgement computing, export corresponding pwm signal to power circuit and control described ac synchronous motor;
Time sequence status modular converter: will link together according to sequential logic with upper module by state machine FSM;
Speed and Current Control synchronised clock module: adopt the mode of increase and decrease counting to send synchronous control signal to SVPWM data processing module, coder module, current filtering module, polar switching module, speed ring pi regulator.
4, the control method of the alternating current synchronous motor controller based on FPGA as claimed in claim 3 is characterized in that the digital filtering processing method of described current filtering module comprises the steps:
1) counting of execution cycle and carrier cycle: the execution cycle of the PWM duty cycle signals that current sensor senses is obtained by reference frequency and carrier cycle carry out counting operation and obtain execution cycle number of pulses and n subcarrier recurrent pulse numerical value respectively, and wherein n is a natural number;
2) processing of the digital filtering of carrier cycle is the filtering of single order homogenizing: filtering obtains single order homogenizing value through the single order homogenizing with n subcarrier recurrent pulse numerical value;
3) processing of the digital filtering of execution cycle is the dV/dt Filtering Processing: obtain the actual execution cycle with adding the tolerance deviate after the execution cycle number of pulses process dV/dt Filtering Processing;
4) division arithmetic of duty ratio: with the described actual execution cycle of step 3) divided by step 2) described single order homogenizing value obtains dutyfactor value.
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