CN101630994B - Method and apparatus for controlling dataflow - Google Patents
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Abstract
The invention provides a method and apparatus for controlling dataflow. The method includes receiving data in a first data processing module, wherein the first data processing module comprises a united surveillance accelerator; and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard; exchanging signals between the first data processing module and software executing in a processor in order to indicate that the first data processing module is ready to deliver the data to the second data processing module, and determining that a software configuration of the second data processing module has been completed; processing the data in the second data processing module for the at least one signal time slot; enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots. The third data processing module comprises a bit rate processor.
Description
Technical field
The invention relates to a kind of wireless communication system, particularly relevant for method of data flow control and the device of wireless communication system.
Background technology
Early stage movable type or wireless communication system (being called now the first generation (1G) system) use and are called frequency division multiple access access (Frequency Division Multiple Access, FDMA) analogue technique transmits the radio voice channel to the mobile phone user, after 1980, develop the second generation (2G) system that uses digital technology.U.S. system at first is to use time-division multiple access (Time Division Multiple Access, TDMA).Early stage in the nineties in 20th century, the TDMA technology is that global system for mobile communications (Global System for Mobile Communications, GSM) is introduced to Europe.In the mid-90 in 20th century, along with the U.S. adopts IS-95(Interim Standard-95) standard, code division multiple access access (Code Division Multiple Access, CDMA) becomes the digital 2G system of the second type.
Wideband Code Division Multiple Access (WCDMA) access (Wideband Code Division Multiple Access, WCDMA) be for the movable type of the 3rd generation (3G) global system for mobile communications (Universal Mobile Telecommunication System, UMTS) or the tranmission techniques of radio communication.The WCDMA system is supported in the voice and the data that have variable-data-rate in the radio communication channel (for example direct access communications channels, paging channel (paging channel), broadcast channel etc.) and transmits.The WCDMA system comprises one or more radio frequency carrier.Each radio frequency carrier comprises frequently coding (spread code) of some exhibitions, and it is assigned with and is used to provide different data rates to satisfy different requirements of mobile subscribers.
The normal utilization of WCDMA system can map to the transmission channel of physical channel.Physical layer/channel (Layer 1) is at inventionthe open systems interconnection reference model (Open System Interconnection(OSI) Reference Model) in be minimum stratum, and it is supported in, and bit stream transmits employed function on the physical medium.This physical layer then provides the higher-order layer of data transport service to wireless communication system.The characteristic of transmission channel is defined by its transformat (or format setting), may need given application to indicate (service-specific) rate-matched in the physical layer process of the transmission channel of discussing (for example convolution chnnel coding and interweave) and any service.Transmission channel can represent the service that is offered the higher-order layer by Layer 1.
The transmission channel of demonstration comprises: the common transmission channel of a., broadcast channel (Broadcast Channel for example, BCH, usually as down link (Downlink, DL) transmission channel is to the customizing messages of broadcast system and/or cell phone system), forward access channel (Forward Access Channel, FACH), paging channel (Paging Channel, PCH), direct access communications channels (Random Access Channel, RACH), general package channel (Common Packet Channel, CPCH) and down link share channel (Downlink Shared Channel, DSCH); And b. can be used on the dedicated channel (Dedicated Channel, DCH) of up link or down link.
TD SDMA access (Time Division Synchronous Code Division Multiple Access, TD-SCDMA) also is the movable type of the 3rd generation global system for mobile communications (3G UMTS) or the tranmission techniques of radio communication.TD-SCDMA uses time domain duplex and a combination code territory multiple-access technology, to support symmetry and asymmetrical transmission.
High-speed down link packet access (High Speed Downlink Packet Access, HSDPA) be third generation partner program (third Generation Partnership Project, 3GPP) the valuable feature of the 5th of specification the edition (Release 5), and represented that TD-SCDMA is towards the developmental first step of high data rate.Specifically, HSDPA is the UMTS that strengthens, so that the downlink data rate by the 5th edition defined increase of UMTS specification to be provided.HSDPA expectation can increase power system capacity, reduce loop-delay and peak data rate increased to be higher than the 2MB/S(MBPS).Therefore, having proposed to be called high-speed down link shares the new shared channel of channel (High Speed Downlink Shared Channel, HS-DSCH) and supports above-mentioned purpose.
In existing communication system, baseband receiver comprises two main elements: one is inner receiver, namely be used for relaxing known equalizers or the chip rate processor of multipath and interference effect, and another is outside receiver, it carries out channel-decoding or other character rate is processed.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of method of data flow control and device thereof, applicable to wireless communication system.
In an embodiment of the present invention, provide a kind of method of controlling data flow, be applicable to wireless communication system.The method is included in receive data in the first data processing module, and wherein the first data processing module comprises the joint detection accelerator; When the data that receive at least one signal slot comprise the data that meet the first data transport standard, enable the second data processing module; The a plurality of signals of exchange between the first data processing module and processor prepare to transmit data to the second data processing module to indicate the first data processing module, and determine that the software configuration of the second data processing module finishes; In the second data processing module, process the data that at least one signal slot receives; And according to finishing that at least one data block in the second data processing module is processed, enable the 3rd data processing module, and the software configuration that determines the 3rd data processing module is finished, wherein, at least one data block comprises a plurality of signal slots, and the 3rd data processing module comprises bit rate processor.
In another embodiment of the present invention, a kind of device of controlling data flow is provided, be applicable to wireless communication system.This device comprises the first data processing module, Circuits System and the 3rd data processing module.The first data processing module comprises the joint detection accelerator, is used for receive data.Circuits System is in order to indicate the first data processing module to prepare to transmit data to the second data processing module, and the software configuration that determines the second data processing module is finished, wherein, the data at least one signal slot are carried out and processed to the second data processing module, and the data at least one signal slot comprise the data that meet the first data transport standard.The 3rd data processing module is enabled according to the finishing of at least one data block processing in the second data processing module, and wherein, this at least one data block comprises a plurality of signal slots, and the 3rd data processing module comprises bit rate processor.
In another embodiment of the present invention, a kind of method of controlling data flow is provided, be applicable to wireless communication system, the method is included in receive data in the first data processing module, the first data processing module comprises the joint detection accelerator, wherein, this step comprises: the data that will meet the first data transport standard export the interior digital signal processor of wireless communication system to, and enable the second data processing module according to the data that detect at least one time slot that comprises the data that meet the second data transport standard.The method also comprises, for each delivery time interval (the transmission time internal that comprises a plurality of time slots, TTI), dispose the second data processing module by digital signal processor, wherein, this step comprises: set a plurality of corresponding control bits in a plurality of configuration registers, and issue a plurality of the interruption and dispose the second data processing module to digital signal processor with request.The method comprises again when the second data processing module disposes to be finished, in the data of each time slot processing in the second data processing module, and finishing according at least one delivery time interval in the second data processing module, enable the 3rd data processing module, wherein the 3rd data processing module comprises bit rate processor.
In another embodiment of the present invention, a kind of device of controlling data flow is provided, be applicable to wireless communication system.This device comprises separating device, a plurality of the first hardware signal processing module, a plurality of the second hardware signal processing module and processor.Separating device meets the data that a plurality of different pieces of informations transmit standard in order to separation.Above-mentioned the first hardware signal processing module is processed the data that meet the first data transport standard take time slot as the basis, a plurality of the first hardware signal processing modules comprise the joint detection accelerator.These the second hardware signal processing modules are spaced apart the basis with the delivery time and process the data that meet the first data transport standard, and wherein, the delivery time interval comprises one or more time slot.Processor meets the data of the second data transport standard in order to processing, and disposes these the first hardware signal processing modules and the second hardware signal processing module.Before processing each time slot and each delivery time interval, these the first hardware signal processing modules and the second hardware signal processing module and processor exchange a plurality of signals according to Handshake Protocol (handshake protocol).
The method of control data flow provided by the present invention and device, compared with prior art, its beneficial effect comprises: by using software and hardware combined control, can reach better signal processing results, and can reduce hardware delay and support multiple wireless standard.
Description of drawings
Figure 1A represents the down link signal processing chain schematic diagram that the present invention simplifies in the HSDPA receiver.
Figure 1B represents the schematic diagram of TD-SCDMA data framework of the present invention.
Fig. 2 represents that the high-level hardware and software of the present invention in the HSDPA channel divided and the schematic diagram of the hardware data stream of joint detection function.
Fig. 3 represents the schematic diagram of embodiment of the JD reprocessing data flow of HSDPA of the present invention.
Fig. 4 represents the present invention in continuous time slot, the data flow in the HSDPA receiver and the schematic diagram of transmission.
Fig. 5 represents the form of the data flow of the present invention in the HSDPA receiver.
Fig. 6 has listed the form of the interruption of the present invention in the HSDPA receiver with the suggestion software operation.
Fig. 7 represents that the present invention in HSDPA and non-HSDPA processing, carries out the form of the control parameter of sequence.
Fig. 8 represents the embodiment flow chart of the program of executable operations of the present invention.
Embodiment
In the middle of this specification and claim, used some vocabulary to censure specific element, those skilled in the art should understand, hardware manufacturer may be called same element with different nouns, this specification and claims not with the difference of title as the mode of distinguishing element, but with the criterion of the difference of element on function as differentiation, be open term mentioned " comprising " in the middle of specification and claims in the whole text, so should be construed to " include but be not limited to ".
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and cooperation accompanying drawing are described in detail below.Read hereinafter detailed description of the illustrated embodiment for accompanying drawing after, the present invention for the person of ordinary skill in the field with obviously.
Figure 1A is illustrated in the schematic diagram of the down link signal processing chain of wireless communication system in high-speed down link packet access (High Speed Downlink Packet Access, the HSDPA) receiver 10.The wireless signal that radio/Analog Baseband (Radio/Analog Baseband, ABB) module 102 receives from base station 101 by antenna 100, and this signal is sent to other signal processing module at signal processing chain downstream (downstream).HSDPA receiver 10 is supported one or more wireless standard or agreement, for example non-HSDPA.Radio/Analog Baseband module 102 is carried out amplification and filtering to the signal that receives on analog domain, and provides digital signal at its output.Then, digital baseband (Digital Baseband, DBB) module 112 is mainly processed the signal executive signal on numeric field.In order to allow that radio/Analog Baseband module 102 and digital baseband block 112 interact, HSDPA receiver 10 can comprise analog-digital converter and digital analog converter (not being shown among Figure 1A), with switching signal between analog domain and numeric field.
Shown in Figure 1A, digital baseband block 112 can be the TD-SCDMA digital baseband block.The Circuits System that is used for implementing digital baseband block 112 can comprise joint detection (Joint Detection, JD) pretreatment module 104, joint detection accelerator (Joint Detection Accelerator, be designated hereinafter simply as JDA) 106, joint detection (JD) post-processing module 108 and HSDPA bit rate processor subsequently (Bit Rate Processor, BRP) 110.From about disturbing (for example noise) and different take matched filter as the receiver on basis, joint detection device (Joint Detector, JD) or " multi-user's detector " this device, to process by user's interference signal is used as separation signal, to remove the interference effect between the user.Like this, can synchronously detect the data that in all codings, transmit by the joint detection calculation rule that the joint detection device is performed, thereby reduce (for example minimizing) intersymbol interference (Inter-Symbol Interference, ISI) and multiple-access disturb (Multi-Access Interference, MAI).In some instances, joint detection calculation rule is used and is forced to make zero (Zero Forcing, ZF) (consult equation (1)) and linear minimum mean-squared error (Linear Minimum Mean Square Error, LMMSE) (consulting equation (2)).
Equation (1)
Equation (2)
Wherein, σ
2Expression noise power, and the data r that receives can affect with the accumulative total of channel impulse response by the data d that transmits and channel/upsets coding, by matrix T and add that noise z represents:
r＝Td+z
In some instances, the joint detection of wireless communication system can be implemented (for example programmable digital signal processor (DSP)) by software approach, perhaps implements with circuit mode by hardware approach, for example the JDA 106 of Figure 1A.In comparison with the joint detection of implementing with software, use the joint detection accelerator can reduce power consumption and chip area, to promote the overall performance of receiver.The r and the σ that provide by software
2And the T that obtains of the information calculations of using software to provide, the joint detection accelerator can provide solution to above listed equation (1) and equation (2).HSDPA receiver 10 support force to make zero (ZF) and linear minimum mean-squared error (LMMSE) calculation rule, and force special status (wherein, the σ that makes zero and can be considered linear minimum mean-squared error
n 2Equal zero).
JD pretreatment module 104 is responsible for producing the input data to JDA 106.JD post-processing module 108 is between JDA 106 and HSDPA bit rate processor 110.More particularly, the output signal that JD post-processing module 108 is processed from JDA 106, and be converted into the form that is fit to HSDPA bit rate processor 110.
In wireless communication system, data are downloaded with the increment of a time slot or subframe usually, but come inter-process with frame rate and/or delivery time interval (Transmission Time Internal, TTI) speed by HSDPA bit rate processor 110.TTI is at global system for mobile communications (Universal Mobile Telecommunication System, UMTS) parameter in (or other digital communication networking), it is relevant with the data encapsulation that enters frame by the higher-order layer and transmit at the radio link layer.TTI is relevant with the length that independent codified on radio link transmits.More particularly, TTI is with relevant about the data block size that is sent to the radio link layer by higher network stratum.
Figure 1B represents the schematic diagram of example TD-SCDMA data framework.Data are with radio frames 130,132 ... transmit etc. sequence, each frame has the duration of 10 milliseconds (millisecond, ms).Each radio frames is divided into two subframes 134 and 136, and each subframe has the duration of 5ms.Each subframe is by 7 time slot TS0 138, TS1 150 ... Deng form, and each time slot has the duration of 0.675ms.Each time slot comprises 4 parts: have the intermediate code (midamble) 152 of 144 chip durations, before intermediate code 152 and after have two data fields 154 and 156 of 352 chip durations, and after data field 156, have among the protection zone 158(figure of 16 chip durations be denoted as G).Intermediate code 152 is loaded with given data and is used by receiver, to carry out channel estimating.According to the flow on each of up link and down link, 7 time slots (TS0, TS1 in each subframe (for example 134 or 136) ... etc.) can distinguish between up link and the downlink traffic.
In one embodiment, HSDPA bit rate processor 110 can TTI be that deal with data is come on the basis.In some instances, HSDPA bit rate processor 110 is divided into two main computing elements: the front-end processing of bit rate processor and back-end processing.The front-end processing of bit rate processor is included in all processing blocks before mixed automatic retransfer request (Hybrid Automatic Repeat ReQuest, the HARQ) memory, comprises demodulation, deinterleaving and rate de-matching.The front-end processing of bit rate processor being finished and being triggered by hardware according to following two events.
● software preparation (or software triggering): transmitting all control parameters to hardware, software can be carried out trigger register and write.
● hardware preparation (or termination of TTI signal): all soft decisions that the hardware preparation indicates about current TTI have arrived frame memory.JD post-processing module 108 transmits soft decision to frame memory with the method for time slot (slot-by-slot) one by one.After receiving software preparatory signal and hardware preparatory signal, arrange at once the front-end processing of bit rate processor.
The back-end processing of HSDPA bit rate processor 110 is included in after the HARQ memory and is connected in all processing blocks of front-end processing.
Fig. 2 represents to be implemented on the embodiment of JD pretreatment module 104, JDA 106 and the JD post-processing module 108 of software and hardware, and the data flow con-trol in software and hardware.At this, " software " (being denoted as SW among the figure) word is broadly about carrying out a large amount of computer programs of some tasks and the set of program in computer system or distributed computing system.Because programming software can upgrade simply, so software can provide widely diversified feature and have preferably adaptability.And " hardware " (being denoted as HW among the figure) word is about physical equipment and device, for example Circuits System, microchip, digital processing unit, microcontroller etc.Digital signal processing hardware can provide sound and fast signal processing, is comparatively difficult but upgrade hardware so that new function to be provided.By carefully divide using, so that the some parts of this application is implemented with software, other parts are then implemented with hardware, and only use software or only use hardware by comparison, and signal processing system can reach better result.
As shown in Figure 2, JDA 106 is to implement with hardware with JD post-processing module 108.JDA 106 more is divided into JDA front-end processor 208 and JDA back-end processor 210.JD post-processing module 108 obtains the data from JDA back-end processor 210, and sends the demapping physical channels symbol to HSDPA bit rate processor 110.JD post-processing module 108 is also assessed the parameter evaluation module 204 that offers at the software end with signal to interference/noise than (Signal-to-Interference-and-Noise-Ratio, SINR).Channel quality pointer (Channel Quality Indicator, CQI) evaluation module 206 also receives the data from JD post-processing module 108.
In certain embodiments, JD post-processing module 108 more can be divided between the software of the hardware of HSDPA data channel (HS-DSCH) (for example capturing the HSDPA physical channel data) and all other channels.By controlling data flow with suitable hardware and software, JD post-processing module 108 enables the adaptive extra stratum of tool on current hardware.This feature provides adaptability, and to support the future development of TD-SCDMA standard, it needs extra process, perhaps with designed current JD post-processing module by comparison, it is comparatively strict with requirement that planisphere (constellation) gains for SINR.
Radio frequency (Radio Frequency, RF) receiver (for example HSDPA receiver 10 of Figure 1A) or utilize the conveyer of direct converting structure produces homophase and quadrature (In-phase and Quadrature, IQ) signal.These signals may have distortion, and it has limited the performance of subsequent demodulation device or modulator.These distortions (being called quadrature error) are to be caused by the gain between the IQ signal component and phase imbalance.Unbalance on the IQ signal may cause picture frequency and direct current offset, and it harms demodulation or modulation treatment.Unbalance in order to proofread and correct IQ, in certain embodiments, as shown in Figure 2, can use JD pretreatment module 104.
JDA front-end processor 208 receives pretreated IQ sampling, channel information and control information, and for example chnnel coding, and generation is by JD efficient coding detecting (Active Code Detection, ACD) module 202 employed intermediate object programs.After the output data that receive from JDA front-end processor 208, the efficient coding of these JD efficient coding detecting module 202 each time slots of assessment.This efficient coding detecting calculation rule can be implemented by software.
After the efficient coding tabulation that receives from software, JDA back-end processor 210 is enabled.In addition, the hardware of Fig. 2-software demarcation framework can support to be called the operator scheme that ACD skips over (skip).That is to say that if in advance known one group of efficient coding, JD efficient coding detecting module 202 becomes can pass through no (transparent).The purpose of design of the HSDPA receiver 10 of narrating in this file is to support 384Kbps and 2.8Mbps channel.Speed comprises different data groups up to the HSDPA channel of 2.8Mbps from the channel of 384Kbps.The data flow con-trol that gives the different pieces of information channel in single hardware processor is for the challenge that guarantees high-performance TS-SCDMA system.Switching on the hardware processor between 384Kbps and 2.8Mbps application implemented immediately, and need not delay (stall) whole HSDPA receiver 10.Hand shake procedure on the software programming model is used for enabling the processing stage of different hardware between software and hardware module.
Utilize effective hardware-software demarcation and data flow con-trol, the TD-SCDMA the 4th edition (Release 4) that HSDPA receiver 10 can be supported the 3GPP standard with the 7th edition, and do not have hardware to delay.This can finish by careful design hardware interface and one group of software programming model, to be implemented in the Handshake Protocol between the hardware and software.
Fig. 3 represents the embodiment of the JD reprocessing data flow con-trol of HSDPA.The first in first out of JDA 106 (First-In First-Out, FIFO) module 302 different the processing stage in the different data group of Buffer output.High-order state machine (top level state machine the is not shown in Fig. 3) control store of can hardware implementing is in the data group of fifo module 302.The downstream hardware that this mechanism makes HSDPA use (such as mobile phone, data card) is processed and is become effectively, yet it still can be supported in the 384Kbps channel in the TTI.
In some instances, it can TTI be that deal with data is come on the basis that HSDPA uses, and JD post-processing module 108 operates as the basis take time slot.When the HSDPA data are sent to JD post-processing module 108 by fifo module 302, or when data were sent to HSDPA bit rate processor 110 by JD post-processing module 108, this species diversity caused hardware to be delayed.Delay in order to reduce hardware, can implement software control or HSDPA programming model and temporarily keep JD reprocessing (being the operation of JD post-processing module 108) data processing and bit rate processing (being the operation of HSDPA bit rate processor 110) data processing at the beginning at the beginning.In addition, maskable interrupts request (Interrupt Request can be provided, IRQ), so that when some operation of beginning, allow the hardware handles state information to be used to notify software, and allow the hardware handles state information to enable and will be transferred into next TTI input data of fifo module 302.In one embodiment, general interrupts mask register (not shown) can determine to produce which kind of interruption.In some instances, when the interruption mask bit was set, it can prevent that the interruption of being correlated with is transmitted to the interrupt output end of HSDPA bit rate processor 110, but relevant interrupt status position will be set in whole interrupt status register.When interruption is eliminated for effective its interrupt mask bit, this interruption will be transmitted to the output of HSDPA bit rate processor 110.According to default value, all mask bits are set as " 1 ", so in order to produce the interruption that needs, its relevant mask bit is eliminated first.
Flag of HSDPA programming model definable, which time slot its notice hardware comprises the HSDPA chnnel coding, uses thereby the data processing is switched to HSDPA by the 384Kbps channel, and vice versa.HSDPA programming model definition data flow, so that high-order hardware state machine monitoring hardware the processing stage, with enable or anergy (disable) by JDA 106 to JD post-processing module 108 and in due course machine further transmit to the data of software and HSDPA bit rate processor 110.HSDPA programming model definable is by the performed operation of JD post-processing module 108 and HSDPA bit rate processor 110.
In conjunction with dedicated channel and the JD reprocessing of HSDPA control channel can be by implement software.Can directly be sent to HSDPA bit rate processor 110 for the output of the JD reprocessing of HSDPA data channel.In other words, the JD reprocessing can by following two kinds independently mode carry out: about the software approach of non-HSDPA channel and the JD reprocessing hardware approach processed about the HSDPA chnnel coding.In one embodiment, JDA input data comprise the input data of predefined format (for example 16 bit sequences and have an ad-hoc location for each bit).Hardware processor can be controlled or enabled by the certain bits (for example HSDPA enable bit of 16 bit sequences) of the input data sequence of JDA 106 behind the JD.
In operation, the chnnel coding of a plurality of transfer rates and standard transmits by the output of JDA 106.Multiplexer is selected and is indicated non-HSDPA chnnel coding to software, processes to carry out further signal.This selection can be finished by set the JDA_OUT_MODE position in JD reprocessing configuration register.The acquisition of non-HSDPA coding is to reach (for example using non-HSDPA acquisition module 304) by carrying out non-HSDPA data acquisition calculation rule.
In some instances, the HSDPA enable bit that includes in the JDA input data enables JD post-processing module 108, and after carrying out the HSDPA data acquisition and calculating (namely behind HSDPA acquisition module 306), cause the HSDPA chnnel coding in accordance with regulations route be sent to JD post-processing module 108.Input data from fifo module 302 comprise various chnnel codings.HSDPA acquisition module 306 captures the HSDPA data, and these data are sent to planisphere rotation and gain assessment (Constellation Rotation and Gain Estimation) module 308.In one embodiment, the planisphere of planisphere rotation and gain evaluation module 308 rotatable HSDPA data is similar to frequency division duplexing (Frequency Division Duplex, FDD) planisphere so that it presents.As shown in Figure 3, adopt subsequently FDD planisphere form in the planisphere rotation of downstream with gain evaluation module 308, SINR evaluation module 316 and demodulation.In case the planisphere rotation is finished its calculating with gain evaluation module 308, if set the JDA_OUT_MODE position, 304 of non-HSDPA acquisition modules are enabled, to carry out the data acquisition of non-HSDPA chnnel coding.The data that acquisition obtains write back to fifo module 302, and then by the interface of external coprocessor I/F port (External Co-processor I/F Port, ECP) data are sent out.If the JDA_OUT_MODE position is reset, all chnnel codings are sent out by the ECP interface.JD post-processing module 108 can not made supposition to constellation gain (being the channel zoom factor), and carries out " hidden " constellation gain assessment (blind).
In certain embodiments, different along with about the demand of accuracy and reporting format in HSDPA bit rate processor 110 and software, all need SINR and constellation gain.For example, SINR divides number format to calculate with 8.8 without sign, and it helps the CQI in the software to calculate.For for each time slot among the single TTI, this numerical value is stored in the one of output register POST_JD_SINR_S0 to POST_JD_SINR_S4 of JD post-processing module 108 accordingly, so that software this numerical value of fechtable after a while.In some instances, constellation gain is come internal calculation with specific format, and for example 1.12 divide number format without sign, but for software, adopts different forms more convenient, so that result value can reset form to avoid saturated.For instance, least significant bit (Least Significant Bits, LSBs) is " 0 " at first, and being filled to 16 bit lengths, and then this end value becomes saturated.
In operation, the SINR value need to be reset form becomes time slot index (slot-exponent).This numerical value can utilize many methods and derive from the SINR value, and wherein, method is the suitable bit fragment (bit-slice) of selecting in the SINR value preferably, and it is got take 2 logarithms the end of as (log2) as index.
JD post-processing module 108 also has some read-only registers, and it generally is that the data treatment state is reported to other element in HSDPA receiver 10.For instance, constellation gain register CONST_GAIN_S0 to CONST_GAIN_S4 is used for being stored in the constellation gain that obtains by hardware in each time slot, but so that these registers of software poll at any time.For JD post-processing module 108 with status report to HSDPA bit rate processor 110, constellation gain can be multiplied by 2, solving the difference on the planisphere gain definitions in JD post-processing module 108 and HSDPA bit rate processor 110, and constellation gain is quantized and makes its bit width be same as bit width to the main output signal of BRP input store.Yet, since this numerical value be always on the occasion of, sign bit can be omitted, and the result exports and can be 0.7 and divide 7 bit widths of number format without sign.
Alternatively, the constellation gain of expectation can be provided by software, and in the case, constellation gain is assessed by anergy.In some instances, control bit (for example constellation gain assessment) can be selected to assess and get or fixing constellation gain.This constellation gain directly offers SINR evaluation module 316.Time slot memory 310 is used for cushioning from the data of planisphere rotation with gain evaluation module 308.The JD reprocessing of this downstream is calculated and is comprised demapping physical channels module (physical channel demapping module) 312 and SINR evaluation module 316.As shown in Figure 4, this output signal provides to HSDPA bit rate processor 110 and software.After in case JD post-processing module 108 is finished the data processing of each frame and each time slot, it sends out time slot end signal (End Of Slot, EOS) with frame end signal (End Of Frame, EOF) with indication HSDPA bit rate processor 110, illustrate that JD post-processing module 108 finished the transmission data to the BRP frame buffer.At one time, transmit EOS and EOF interrupt requests to the digital signal processor (not shown).
In addition, the internal control register-bit of HSDPA bit rate processor 110 (being software preparation position) is used for triggering the processing of HSDPA bit rate processor 110.This feature provides adaptability to software,, has replaced calculating the numerical value that provides by JD reprocessing hardware to downstream with SINR that itself is provided and constellation gain.This feature allows this is calculated regular optimization, makes gradually it be independent of to a great extent JD reprocessing hardware.
In certain embodiments, HSDPA bit rate processor 110 can be used to transmit " BRP inputs preparation and interrupts " request, indicates to software from the information of next TTI data of JD post-processing module 108 so that HSDPA bit rate processor 110 is prepared reception.This interrupt requests also initialization sends next TTI data of JDA106 to.106 beginnings of JDA chip rate is processed, and all data are stored to its fifo module 302.When the constellation gain of the JD reprocessing that determines each time slot, non-HSDPA data are captured and are written back to identical fifo module 302.Like this, JDA processes and all can reuse in HSDPA and 384Kbps data channel.This feature also enables hardware designs and related software programming model, makes it be exclusively used in the HSDPA application specification, still can process the data that meet various criterion simultaneously.When processing met the data of various criterion, device of the present invention more comprised separating device, was used for separating these and met the data that different pieces of information transmits standard.
Should be noted that efficient coding can be resequenced by software (reorder), so that HS-DSCH is coded among the JDA 106 is at first processed.This has been avoided when the number change at non-HSDPA coding of two time slot chien shih times spent, and wherein, this number change will affect the relevant configuration of HS-DSCH channel, therefore, allows at each TTI to these channel programmings once.
Fig. 4 is illustrated in the transmission of the data in nine continuous slots in the HSDPA receiver 10, and consults simultaneously Figure 1A.In addition, having summarized the key data that occurs in the form of Fig. 5 during each time slot transmits.In Fig. 4 and Fig. 5, for the energy concise description, part explanation represents abridging, and in the full name and the meaning that have above proved absolutely abbreviation, the frame end signal input of the reprocessing of wherein, " Pre-JD " expression JD preliminary treatment, " Post-JD " expression JD reprocessing, " Post JDA EOF Int " expression joint detection accelerator.For instance, in the row 1,3,8 and 9 of Fig. 5, the data of being calculated and being provided by software are provided HSDPA receiver 10.Row 1 expression is implemented to operate once at each downlink time slots as the JDA 106 of first element in the HSDPA signal chains.The input data of JDA 106 (for example data sampling, chnnel coding, channel estimating and control information) are provided by software, and are sent to the joint detection accelerator hardware, transmit as complete data.JDA 106 exports a secondary data in each time slot.Second element in the HSDPA signal chains is JD post-processing module 108.The input data of JD post-processing module 108 are to obtain (label that is Fig. 4 transmits row 4 with Fig. 5 for 4. data) from JDA 106, and the control parameter is from software (label that is Fig. 4 transmits row 8 with Fig. 5 for 8. data).Before the first time slot of data arrived JD post-processing module 108, JD post-processing module 108 hardware can be programmed by software.Programming JD post-processing module 108 is to implement as the basis take TTI, and JD post-processing module 108 is come deal with data with time slot method one by one.
About the 3rd element (being JD post-processing module 108) in the HSDPA signal chains, the output data of JD post-processing module 108 are sent to the input store of HSDPA bit rate processor 110 with the method for time slot one by one, and this transmission is by the hardware internal control.That is to say that the increment with time slot or subframe comes downloading data usually, but come the inter-process data with frame rate or TTI speed by HSDPA bit rate processor 110.The transmission block of acquisition is stored in the transmission block buffer with the TTI speed relevant with transmission channel.Transport channel data for a plurality of transmission channels with identical TTI will become effectively at one time.In one embodiment, download frame data and frame configuration at the every 10ms of the frame rate action need of HSDPA bit rate processor 110.This TTI speed action need is at each TTI programming transmission channel control register of each effective transmission channel.Therefore, programming HSDPA bit rate processor 110 is to implement as the basis take TTI, and each HSDPA TTI of the coprocessor of HSDPA bit rate processor 110 produces the output data once.
Fig. 6 has listed the software operation that interrupts with suggestion.In the form of Fig. 7, summarized in the HSDPA processing chain, be used for controlling the parameter of carrying out sequence about the expection of HSDPA and non-HSDPA processing.In Fig. 6 and Fig. 7, for can concise description, the part explanation represents abridging, and in the full name and the meaning that have above proved absolutely abbreviation, wherein, the request of " HARQ " expression mixed automatic retransfer.Consult Fig. 6, for instance, according to finishing that current TTI is processed, HSDPA bit rate processor 110 will propose to interrupt HS_BRP_DONE, so that the parameter of the HSDPA bit rate processor 110 of next TTI of software programmable.Far Left field according to Fig. 7 can learn, when HSDPA receiver 10 is not when processing the HSDPA data, register HS_RX_EN position can be set as 0.In the case, JDA 106 can be independent of JD post-processing module 108 and work, and therefore HSDPA bit rate processor 110 makes HSDPA process anergy.This can implement by ignoring all the HSDPA particular register in JD post-processing module 108 and HSDPA bit rate processor 110 and the HSDPA enable bit (HSDPAEn) in the JDA 106 being set as 0.At this moment, JDA 106 operates under the Rel4 pattern.On the other hand, when current TTI comprised the HSDPA data, register HS_RX_EN position can be set as 1 to enable the HSDPA processing.This informs that also JDA 106 goes to move according to the HSDPA enable bit, and enables JD post-processing module 108 in the time slot that comprises the HSDPA data, in addition, when receiving whole TTI, triggers at last HSDPA bit rate processor 110.
Owing to be not that all time slots all comprise the HSDPA data in HSDPA TTI, which time slot JDA 106 is apprised of by the HSDPA enable bit and the processing of HSDPA time slot and which does not process (namely being considered as the HS_RX_EN position is 0) as the HSDPA time slot as.When the HSDPA enable bit was 0, JDA 106 can't swap data or notice JD post-processing module 108, but after finishing execution, spread out of all output data by direct memory access (DMA) (DMA).When the HSDPA enable bit was 1, JD post-processing module 108 was triggered according to finishing of JDA 106.If (being CONFIG_READY=0) do not got in the at this moment programming of JD post-processing module 108 in advance ready, JD post-processing module 108 indication softwares, the configuration that JD post-processing module 108 is described is not also finished, JD post-processing module 108 produces ConfigNotReady and interrupts, and JD post-processing module 108 is also delayed, until configuration successful write and the CONFIG_READY position is set as 1.JD post-processing module 108 then will copy the HSDPA data from the JDA output buffer, and notice JDA 106.JDA 106 then removes HSDPA data (if JD_OUTPUT_MODE=1) from the JDA output buffer, and continues to transmit data to JD post-processing module 108.The JD_OUTPUT_MODE position is the configuration register from JD post-processing module 108.Before the hardware handles of JDA 106 finished, software need to be programmed in the JD_OUTPUT_MODE position of JD post-processing module 108.Yet if JD_OUTPUT_MODE=0, before transmitting, JDA 106 can not remove the HSDPA data.The JD_OUTPUT_MODE position is to be programmed when each TTI, even therefore it affects JDA 106, the JD_OUTPUT_MODE position is to be programmed with JD post-processing module 108 as the basis take TTI.
The number of times that the quantity that JD post-processing module 108 maintains HSDPA time slot in the TTI according to the HS_RX_TS position is calculated with and triggered by JDA 106.In case JD post-processing module 108 is judged and received whole TTI, it will trigger HSDPA bit rate processor 110.
In order to implement above-mentioned sequence, the programmed sequence summary is proposed hereinafter.
1. by setting the configuration register JD post-processing module 108 of programming, and the register HS_SLOT_SIZE that sets HSDPA bit rate processor 110 is to TTI, and wherein, configuration register is shared by all time slots that belong to TTI.
2. programming JDA 106(HSDPA enable bit is 1), in order to process a HSDPA time slot.Be positioned at any non-HSDPA time slot before first HSDPA time slot and can be independent of JD post-processing module 108 and be programmed, as long as be 0 about the HSDPAEn position of this time slot.Under situation before JDA 106 finishes first time slot of TTI was finished in the programming of JD post-processing module 108, step 2 can be in the front execution of step 1.This can promote data to process.
3. programming HSDPA bit rate processor 110.If (for any the preceding HSDPA TTI) carried out in the processing of HSDPA bit rate processor 110, this programming can delay, until HSDPA bit rate processor 110 is notified its processing of having finished this TTI (HS_BRP_DONE interruption).Simultaneously, the programming of following JDA 106 can be carried out simultaneously.
4. become when effective when the data from JD pretreatment module 104, programming JDA 106 is to be used for remaining time slot.If time slot does not comprise the HSDPA data in the middle of any, then set the HSDPAEn position and be 0 to this time slot.Comprise the time slot of HSDPA data for all, the HSDPAEn position can be set as 1.
Below two patterns are the performance requirements that indicate to different.For example, if adopt time slot overlap scheme (it is default mode), the overall performance of JDA 106 can be higher than the performance of non-overlapped pattern.More particularly, the time slot overlap scheme relates to and side by side carries out to JDA 106 input and along with JDA 106 outputs of next time slot hardware handles.This pattern can shorten the overall data process time of JDA 106.On the contrary since non-time slot overlap scheme provide better and completely Data Control to software debugging, so its mainly as the debugging purposes.
● time slot overlap scheme (suggestion mode): under this pattern, when JDA 106 hardware are just being processed current time slots, JDA 106 programmings of next time slot occur.The time slot overlap scheme is proposed to be used in the peak data rate situation that each TTI has 5 HSDPA time slots.
● non-time slot overlap scheme: under this pattern, after JDA 106 finishes the processing of current time slots, JDA 106 programmings of next time slot occur.Software will be subject to the indication interrupting or interrupt from the JDA Done of JDA 106 from the EOS of JD post-processing module 108.This pattern can be used as the debugging purposes.
5. in case all the HSDPA time slots in TTI are processed by JD post-processing module 108, HSDPA bit rate processor 110 automatically is triggered.Yet, if HSDPA bit rate processor 110 at this moment machine also be not programmed, HSDPA bit rate processor 110 will be informed software.In case HSDPA bit rate processor 110 has consumed its input signal, (BRP Input Ready) interrupted in 110 issues of HSDPA bit rate processor, and then the programming of next TTI can begin reliably.
Fig. 8 is illustrated in the embodiment of program 80 flow charts that are used for controlling data flow in the HSDPA receiver 10.In program 80, receive input data (step 802) by JD pretreatment module 104, as shown in Figure 2, data will further be processed by JDA front-end processor 208.Then, judge whether the data that receive are HSDPA data (step 804).If, fechtable HSDPA channel data, and send a signal to JD post-processing module 108, and carry out hardware handshaking program (step 808) with JD post-processing module 108, prepare to be used for downstream with designation data.Simultaneously, (step 810) finished in the software configuration of HSDPA receiver 10 affirmation JD post-processing module 108.If two situations all satisfy, 108 beginnings of JD post-processing module deal with data (step 812).If the non-HSDPA data of data that receive, then deal with data (step 806) in software.
SINR and constellation gain output register one by one time slot are that access is come on the basis, but also can be read out after TTI finishes.SINR output preparation (being used for CQI calculates) is finished by the time slot of each time slot and is interrupted notifying.For example, JD post-processing module 108 comprises status register, and it comprises some mode bits, and these mode bits can be used to confirm the hardware progress of JD post-processing module 108.Specifically, be the state that special use is stored in each time slot among the TTI at the bit EOS0 to EOS4 of status register.Any unexpected time slot of software maskable is finished interruption.Yet hardware needs enough adaptability to be processed by software with the interruption that allows any or all.The numbering that time slot is finished interruption is relative.For example, if use three time slots, the corresponding EOS2 of last time slot of frame is no matter which physical slot by time is used.
Software also provides HSDPA bit rate deal with data current control by the programming that postpones HSDPA bit rate processor 110.This operation is finished and interrupt signal chain (when EOF issues) according to the JD reprocessing, and allows software before triggering HSDPA bit rate processor 110, uses constellation gain and SINR for each time slot in the frame.Can restart this program by the configuration register that writes the HSDPA bit rate processor.SINR and constellation gain parameter are come access by HSDPA bit rate processor debugging interface (not shown).
In this narration, connection can be wired or wireless connection.When a module is stated as when being connected to another module, this module can be directly or indirectly (for example by another module) be connected to another module.
Can implement by the computer processing system that comprises Software Coding in device, method, flow chart, architecture block diagram that this specification is narrated, and Software Coding comprises by the performed program command of computer processing system.Other execution mode also can use.In addition, the flow chart that this specification is narrated and architecture block diagram are to be described in ad hoc approach under the step support and/or respective action and to disclose the corresponding function of architecture device under supporting, but also can be used to implement corresponding software architecture and calculation rule with and the person of being equal to.
Method and system described here can be implemented with many dissimilar processing unit by program coding, and this program coding comprise can be by the performed program command of one or more processor.This software program instructions comprises coming source code, purpose coding, machine code or operation to cause treatment system to go to carry out other storage data of said method.
This System and method for can provide by dissimilar computer-readable mediums, computer-readable medium comprises Computer Memory Unit (for example CD-ROM, disk, RAM, flash memory, computer hardware etc.), it comprises by the performed instruction of processor, to carry out above-mentioned method operation and to implement above-mentioned system.
These civilian described computer components, software module, function and data framework can directly or indirectly be connected to each other person, to allow data flow as other operation.Should be noted that also software instruction or module can be implemented computer code or the firmware as SFU software functional unit, object (Object Oriented OO type), Program Type, computer mark language or other type of the subprogram unit of coding, coding.According to virtual condition, the configurable a plurality of devices in single device or dispersion of this software element and/or function.
The person of ordinary skill in the field is can be unlabored impartial to be changed or retouching all belongs to the scope that the present invention advocates, interest field of the present invention should be as the criterion with claims limited range.
Claims (25)
1. a method of controlling data flow is applicable to wireless communication system, it is characterized in that, described method comprises:
Receive data in the first data processing module, wherein said the first data processing module comprises the joint detection accelerator;
When the described data that receive at least one signal slot comprise the data that meet the first data transport standard, enable the second data processing module;
The a plurality of signals of exchange to be indicating described the first data processing module to prepare to transmit described data to described the second data processing module between described the first data processing module and processor, and determine that the software configuration of described the second data processing module finishes;
In described the second data processing module, process the described data that described at least one signal slot receives; And
Finish to enable the 3rd data processing module according to what at least one data block in described the second data processing module was processed, and the software configuration that determines described the 3rd data processing module is finished, wherein, described at least one data block comprises a plurality of signal slots, and described the 3rd data processing module comprises bit rate processor.
2. the method for control data flow as claimed in claim 1 is characterized in that, described the first data transport standard comprises high-speed down link packet access standard.
3. the method for control data flow as claimed in claim 1 is characterized in that, described joint detection accelerator comprises the first in first out module.
4. the method for control data flow as claimed in claim 1, it is characterized in that, described the second data processing module is processed the output data from described the first data processing module, and described output data are converted to the form that is fit to described the 3rd data processing module.
5. the method for control data flow as claimed in claim 1 is characterized in that, described the first data processing module is configured to:
Acquisition meets the data of the second data transport standard; And
Process the data that meet described the second data transport standard by described processor.
6. the method for control data flow as claimed in claim 1 is characterized in that, described processor provides constellation gain to described the second data processing module.
7. the method for control data flow as claimed in claim 1 is characterized in that, described the second data processing module is used to provide signal interference/noise is compared numerical value.
8. the method for control data flow as claimed in claim 7 is characterized in that, described signal calculates acquisition take time slot as the basis than numerical value to interference/noise.
9. a device of controlling data flow is applicable to wireless communication system, it is characterized in that, described device comprises:
The first data processing module, in order to receive data, wherein said the first data processing module comprises the joint detection accelerator;
Circuits System, prepare to transmit described data to the second data processing module in order to indicate described the first data processing module, and the software configuration that determines described the second data processing module is finished, wherein, described the second data processing module captures and processes the data at least one signal slot, and the data in described at least one signal slot comprise the data that meet the first data transport standard; And
The 3rd data processing module is enabled according to finishing of at least one data block processing in described the second data processing module, and wherein, described at least one data block comprises a plurality of signal slots, and described the 3rd data processing module comprises bit rate processor.
10. the device of control data flow as claimed in claim 9 is characterized in that, described the first data transport standard comprises high-speed down link packet access standard.
11. the device of control data flow as claimed in claim 9 is characterized in that, described joint detection accelerator comprises the first in first out module.
12. the device of control data flow as claimed in claim 9, it is characterized in that, described the second data processing module is processed the output data from described the first data processing module, and described output data are converted to the form that is fit to described the 3rd data processing module.
13. the device of control data flow as claimed in claim 9 is characterized in that, described the first data processing module is configured to:
Acquisition meets the data of the second data transport standard; And
Process the data that meet described the second data transport standard by processor.
14. the device of control data flow as claimed in claim 9 is characterized in that, processor provides constellation gain to described the second data processing module.
15. the device of control data flow as claimed in claim 9 is characterized in that, described the second data processing module is used to provide signal interference/noise is compared numerical value.
16. the device of control data flow as claimed in claim 15 is characterized in that, described signal calculates acquisition take time slot as the basis than numerical value to interference/noise.
17. a method of controlling data flow is applicable to wireless communication system, it is characterized in that, described method comprises:
Receive data in the first data processing module, wherein, described the first data processing module comprises the joint detection accelerator, the described step that receives described data in described the first data processing module comprises:
The data that will meet the first data transport standard export the interior digital signal processor of described wireless communication system to; And
Data according at least one time slot that detects enable the second data processing module, and wherein, the data of described at least one time slot comprise the data that meet the second data transport standard;
By described digital signal processor, dispose described the second data processing module at each the delivery time interval that comprises a plurality of time slots, wherein, the described step that disposes described the second data processing module comprises:
In a plurality of configuration registers, set the control bit of a plurality of correspondences; And
Issue a plurality of interruptions to described digital signal processor and dispose described the second data processing module with request;
When described the second data processing module configuration is finished, in the data of each time slot processing in described the second data processing module; And
According to finishing of at least one delivery time interval in described the second data processing module, enable the 3rd data processing module, wherein said the 3rd data processing module comprises bit rate processor.
18. the method for control data flow as claimed in claim 17 is characterized in that, described a plurality of interruptions are maskable.
19. the method for control data flow as claimed in claim 17 is characterized in that, the described step that receives described data in described the first data processing module is to come deal with data take time slot as the basis.
20. the method for control data flow as claimed in claim 17 is characterized in that, processes the described step that meets the data of described the second data transport standard in described the second data processing module and comprises that being spaced apart the basis with the delivery time comes deal with data.
21. the method for control data flow as claimed in claim 17 is characterized in that, described the first data transport standard comprises non-high-speed down link packet access standard.
22. the method for control data flow as claimed in claim 17 is characterized in that, comprises described digital signal processor in described wireless communication system.
23. a device of controlling data flow is applicable to wireless communication system, it is characterized in that, described device comprises:
Separating device meets the data that a plurality of different pieces of informations transmit standard in order to separation;
A plurality of the first hardware signal processing modules are processed the data that meet the first data transport standard take time slot as the basis, wherein said a plurality of the first hardware signal processing modules comprise the joint detection accelerator;
A plurality of the second hardware signal processing modules are spaced apart the basis with the delivery time and process the data that meet described the first data transport standard, and wherein, described delivery time interval comprises one or more time slot; And
Processor meets the data of the second data transport standard in order to processing, and disposes described a plurality of the first hardware signal processing module and described a plurality of the second hardware signal processing module;
Wherein, before processing each described time slot and each described delivery time interval, described a plurality of the first hardware signal processing modules and described a plurality of the second hardware signal processing modules and described processor exchange a plurality of signals according to Handshake Protocol.
24. the device of control data flow as claimed in claim 23 is characterized in that, described the first data transport standard comprises high-speed down link packet access standard.
25. the device of control data flow as claimed in claim 23, it is characterized in that, described a plurality of the second hardware signal processing module is used for processing the output data from described a plurality of the first hardware signal processing modules, and described output data is converted to the form of a plurality of downstream data processing modules that are fit to described wireless communication system.
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| CN101635607B (en) | 2012-10-31 |
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