CN101626299B - Stackable switch, switch stacking system and cable hot plugging method - Google Patents
Stackable switch, switch stacking system and cable hot plugging method Download PDFInfo
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- CN101626299B CN101626299B CN200910090419XA CN200910090419A CN101626299B CN 101626299 B CN101626299 B CN 101626299B CN 200910090419X A CN200910090419X A CN 200910090419XA CN 200910090419 A CN200910090419 A CN 200910090419A CN 101626299 B CN101626299 B CN 101626299B
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Abstract
The invention discloses a stackable switch, a switch stacking system and a cable hot plugging method. The stackable switch comprises a main board and a stacking subboard, wherein the main board comprises a data exchange application specific integrated circuit (ASIC); a stacking plug is arranged on the stacking subboard; the ASIC is connected with the stacking plug by a printed circuit board (PCB) cable; a protective circuit is arranged on the PCB cable between the ASIC and the stacking plug and used for plugging the stacking plug and a stacking plug on the stackable switch at the opposite end, and the stackable switch and the stackable switch at the opposite end are communicated with the PCB cable after being normally energized; and the PCB cable is cut off before the stacking plug and the stacking plug on the stackable switch at the opposite end are pulled out. The embodiment of the invention can prevent the damage of the hot plugging of the cable on the stackable switch.
Description
Technical field
The present invention relates to the communication technology, especially a kind of stackable switch, switchboard stacked system and cable hot plugging method.
Background technology
Development along with modern very lagre scale integrated circuit (VLSIC); CMOS complementary metal-oxide-semiconductor (complementary metaloxide semi-conductor; Hereinafter to be referred as: CMOS) the transistor technology characteristic size is sharply dwindled; The also corresponding attenuation fast of gate causes the CMOS transistor constantly to reduce for the ability to bear of high voltage with big electric current.For example: the transistorized gate of CMOS that is of a size of 180nm has only about 4nm, can only bear the quiescent voltage about 10V.And ubiquitous in daily life electrostatic phenomenon, in the time can being perceived by human body, its voltage is up to 3000V, considerably beyond the scope that can bear of CMOS transistor.
In the Ethernet Exchanger Technology field, owing to sharp increase to swap data capacity and bandwidth demand, ultrahigh speed exchanges data application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit, hereinafter to be referred as: ASIC) arise at the historic moment.In asic chip, adopted the design technology of smaller szie so that reduce power consumption, this also just makes switch system be faced with the danger of increasingly serious high voltage and big electric current destruction.In switchboard stacked system, this risk is just even more serious.So-called switchboard stacked system is that according to specific topological structure, use can plug the system that cable is connected with each other of piling up by two or stackable switch more than two.All separate unit switches logically form an integral body in the switchboard stacked system.In switchboard stacked system, exist a main process equipment (Master) and many from machine equipment (Slave).As shown in Figure 1, be a topological structure sketch map of prior art switchboard stacked system.Wherein, A, B ..., N is each the separate unit switch in the switchboard stacked system.As shown in Figure 2, be a structural representation of separate unit switch among Fig. 1.
In switchboard stacked system; Local device is certain switch device of present analysis; In switchboard stacked system, can make a general reference any switch, remote equipment and local device are through piling up the direct-connected switch device of cable, and remote equipment is for local device.Cable hot plugging is in switchboard stacked system, when having at least one to be in electriferous state in local device and the remote equipment, to piling up the plug operation that cable carries out.
In piling up application, to often pile up cable hot plugging inevitably.Mainly there are following two kinds of risks in prior art in the process of cable hot plugging:
First kind is, in the moment that cable heat is inserted and hot drawing goes out, especially when remote equipment does not normally power on, dock with the local device that has powered on through piling up cable, then with pile up the remote equipment that cable is connected on capacitive load be recharged.In charging process, the capacitive load on the remote equipment will be received a large amount of electric currents from the system power supply of local device in the moment that cable inserts, and cause system voltage moment of local device to be fallen, thereby influence the normal operation of local device.In extracting the process of cable, the load capacitance discharge on the remote equipment also can produce instantaneous large-current, is also referred to as surge current, and surge current carries lot of energy, sees through to pile up socket; The printed circuit board (PCB) that connects (Printed circuit board, hereinafter to be referred as: PCB) cabling, possibly directly pour into exchanges data ASIC inside, cause the permanent damage of exchanges data ASIC.
Second kind is, in piling up the hot plug process of cable, along with piling up removing and inserting of cable, has produced relatively moving of charged object piling up the socket place, for the generation of static provides prerequisite.And in piling up the hot plug process of cable, exterior static charge carrier such as human body probably directly touch piles up socket, thereby static discharge takes place.And in a single day static discharge takes place, instantaneous pressure will be scurried switch inside through piling up socket, makes the exchanges data ASIC to electrostatic sensitive cause irrecoverable damage.
Summary of the invention
The purpose of the embodiment of the invention is: a kind of stackable switch, switchboard stacked system and cable hot plugging method are provided, the damage of avoiding the hot plug of cable that stackable switch is caused.
A kind of stackable switch that the embodiment of the invention provides; Comprise mainboard and pile up daughter board; Said mainboard comprises the exchanges data application-specific integrated circuit ASIC; The said daughter board that piles up is provided with and piles up socket; Said ASIC is connected with the printing board PCB cabling with said piling up between the socket, and said ASIC and the said PCB cabling that piles up between the socket are provided with protective circuit, said pile up socket be provided with earth terminal GND, first receive FPDP to RD+/-, first send FPDP to TD+/-, with the control signal port to Pre_R/Pre_L; Said RD+/-respectively with the opposite end stackable switch on pile up TD+ on the socket/-dock, said Pre_R/Pre_L respectively with said opposite end stackable switch on the Pre_L/Pre_R that piles up on the socket dock; Pile up on the socket said, the stitch lengths of said GND is the longest, said RD+/-with said TD+/-stitch lengths take second place, the stitch lengths of said Pre_R/Pre_L is the shortest;
Said protective circuit specifically be used for said pile up on the socket Pre_R/Pre_L respectively with said opposite end stackable switch on pile up the said PCB cabling of connection after Pre_L/Pre_R on the socket pegs graft and said stackable switch normally powers on said opposite end stackable switch; Said pile up on the socket Pre_R/Pre_L respectively with said opposite end stackable switch on pile up and when Pre_L/Pre_R on the socket breaks off said PCB cabling, said ASIC be provided with second send FPDP to TX+/-with the second reception FPDP to RX+/-;
Said protective circuit comprises diverter switch, and this diverter switch comprises: the first differential signal input, the second differential signal input, the 3rd differential signal input, the first differential signal output, the second differential signal output, the first binary channels single channel gate logic device, the second binary channels single channel gate logic device and the 3rd binary channels single channel gate logic device;
Input port IN+ on the said first differential signal input/-respectively through electric capacity and said TX+/-corresponding connection, the output port on the said first differential signal input respectively with the said second binary channels single channel gate logic device on an access port, an access port on said the 3rd binary channels single channel gate logic device be connected;
Input port IN0+ on the said second differential signal input/-pull down to GND through electric capacity respectively, the output port on the said second differential signal input respectively with said the 3rd binary channels single channel gate logic device on another access port, an access port on the said first binary channels single channel gate logic device be connected;
Input port IN1+ on said the 3rd differential signal input/-respectively through electric capacity and said TD+/-corresponding connection, the output port on said the 3rd differential signal input respectively with the said first binary channels single channel gate logic device on another access port, another access port on the said second binary channels single channel gate logic device be connected;
Output port OUT+ on the said first differential signal output/-respectively through electric capacity and said RX+/-corresponding connection, the input port on the said first differential signal output is connected with single channel port on the said first binary channels single channel gate logic device;
Output port OUT0+ on the said second differential signal output/-respectively through electric capacity and said RD+/-corresponding connection; Input port on the said second differential signal output is connected with single channel port on the said second binary channels single channel gate logic device; The said second differential signal output is provided with the first enable logic control unit OE0; This OE0 pulls down to GND through resistance, and being used in logical value is 0 o'clock, make OUT0+/-output high-impedance state; In logical value is 1 o'clock, make OUT0+/-normal output;
Another access port on the said first binary channels single channel gate logic device also with the said second binary channels single channel gate logic device on another access port be connected; Output channel switch logic control pin MUX on the said first binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up said IN0+/-and said OUT+/-between output channel, be 1 o'clock in logical value, set up said IN1+/-and said OUT+/-between output channel;
Output channel switch logic control pin MUX0 on the said second binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up said IN+/-and said OUT0+/-between output channel; In logical value is 1 o'clock, set up said IN1+/-and said OUT0+/-between output channel;
Single channel port on said the 3rd binary channels single channel gate logic device is unsettled; Output channel switch logic control pin MUX1 on said the 3rd binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up said IN0+/-and said the 3rd binary channels single channel gate logic device on the single channel port between output channel, be 1 o'clock in logical value, set up said IN+/-and said the 3rd binary channels single channel gate logic device on the single channel port between output channel;
Said Pre L is through moving system power supply VCC on the resistance; Said Pre R pulls down to GND through resistance, and connects an input of AND circuit simultaneously, and another input of said AND circuit pulls down to GND through resistance, and the output of said AND circuit is connected with said OE0 and said MUX respectively.
A kind of switchboard stacked system that the embodiment of the invention provides comprises a plurality of stackable switch that provide like the above embodiment of the present invention.
A kind of cable hot plugging method that the embodiment of the invention provides comprises:
ASIC and pile up the protective circuit that is provided with on the PCB cabling between the socket; Pile up that socket is pegged graft and said stackable switch and said opposite end stackable switch when normally powering on socket and the opposite end stackable switch detecting said piling up; Connect said PCB cabling; Detecting saidly when piling up piling up socket and will extract on socket and the opposite end stackable switch, breaking off said PCB cabling.
The stackable switch, switchboard stacked system and the cable hot plugging method that provide based on the above embodiment of the present invention; At ASIC and pile up on the PCB cabling between the socket and be provided with protective circuit; Can detect pile up on socket and the opposite end stackable switch pile up whether socket pegs graft and whether stackable switch and opposite end stackable switch normally power on; Piling up piling up after socket grafting and stackable switch and opposite end stackable switch normally power on socket and the opposite end stackable switch; Just connect ASIC and pile up the PCB cabling between the socket; And, break off ASIC and pile up the PCB cabling between the socket, thereby avoid the hot plug of cable that ASIC is caused damage detecting when piling up piling up socket and will extract on socket and the opposite end stackable switch; And then effectively prevent in the hot plug process of cable, stackable switch to be caused damage, improve the hot plug protective capacities of whole switchboard stacked system.
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a topological structure sketch map of prior art switchboard stacked system;
Fig. 2 is a structural representation of separate unit switch among Fig. 1;
Fig. 3 is the structural representation of an embodiment of stackable switch of the present invention;
Fig. 4 is the structural representation of another embodiment of stackable switch of the present invention;
Fig. 5 is the structural representation of another embodiment of stackable switch of the present invention;
Fig. 6 is the structural representation of an embodiment of protective circuit of the present invention;
Fig. 7 a is the structural representation of the present invention's first differential signal input;
Fig. 7 b is the structural representation of the present invention's second differential signal input;
Fig. 7 c is the structural representation of the present invention's the 3rd differential signal input;
Fig. 7 d is the structural representation of the present invention's first differential signal output;
Fig. 7 e is the structural representation of the present invention's second differential signal output;
Fig. 7 f is the structural representation of the present invention's first binary channels single channel gate logic device;
Fig. 7 g is the structural representation of the present invention's second binary channels single channel gate logic device;
Fig. 7 h is the structural representation of the present invention's the 3rd binary channels single channel gate logic device;
Fig. 8 is the structural representation of another embodiment of protective circuit of the present invention;
Fig. 9 is the structural representation of the present invention's the 3rd differential signal output;
Figure 10 is a structural representation of electrostatic discharge protection circuit of the present invention;
Figure 11 is the structural representation of an embodiment of switchboard stacked system of the present invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
In the embodiment of the invention; At the exchanges data ASIC of stackable switch and pile up between the socket; A protective circuit is set; Avoid in the conventional switch pile system that two stackable switch exist in the cable hot plug process, the data processing ASIC as the stackable switch core component is produced damage, thereby improve the hot plug protective capacities of whole switchboard stacked system.
Fig. 3 is the structural representation of an embodiment of stackable switch of the present invention.As shown in Figure 3, the stackable switch of this embodiment comprises mainboard 11 and piles up daughter board 12.Wherein, mainboard 11 comprises exchanges data ASIC111, piles up daughter board 12 and is provided with and piles up socket 121.ASIC111 is connected with PCB cabling 13 with piling up between the socket 121.At ASIC111 and pile up on the PCB cabling 13 between the socket 121; Be provided with protective circuit 14; Be used for connecting this PCB cabling 13 after socket is pegged graft and stackable switch normally powers on the opposite end stackable switch piling up piling up on socket 121 and the opposite end stackable switch this PCB cabling 13 of disconnection before the piling up socket and extract on piling up socket 121 and opposite end stackable switch.Because protective circuit 14 is arranged on ASIC111 and piles up on the PCB cabling 13 between the socket 121, the protective circuit 14 of the embodiment of the invention possesses the I/O channel management function and supports hot plug.
Wherein, as a specific embodiment of the present invention, stackable switch and opposite end stackable switch normally power on and specifically can be: the magnitude of voltage that piles up on the socket belongs to the normal voltage value scope that is provided with in advance.
In the stackable switch that the foregoing description provides; Because at ASIC and pile up on the PCB cabling between the socket and be provided with protective circuit; Can detect pile up on socket and the opposite end stackable switch pile up whether socket pegs graft and whether stackable switch and opposite end stackable switch normally power on; Piling up piling up after socket grafting and stackable switch and opposite end stackable switch normally power on socket and the opposite end stackable switch; Just connect ASIC and pile up the PCB cabling between the socket, and, break off ASIC and pile up the PCB cabling between the socket detecting when piling up piling up socket and will extract on socket and the opposite end stackable switch; Thereby avoid the hot plug process of cable that ASIC is caused damage, and then prevent that effectively the hot plug process of cable from causing damage to stackable switch.
Fig. 4 is the structural representation of another embodiment of stackable switch of the present invention.As shown in Figure 4, to compare with embodiment shown in Figure 3, in the stackable switch of this embodiment, mainboard 11 is connected with socket between plate 15 with piling up between the daughter board 12.Accordingly, ASIC111 is specially with piling up between the socket 121 to be connected with PCB cabling 13: be connected with a PCB cabling 131 between the socket 15 between ASIC111 and plate, socket 15, protective circuit 14 and piling up between the socket 121 is connected with the 2nd PCB cabling 132 between plate.Accordingly, protective circuit 14 can be arranged on the PCB cabling 131, also can be arranged on the 2nd PCB cabling 132.
Fig. 5 is the structural representation of another embodiment of stackable switch of the present invention.Fig. 6 is the structural representation of an embodiment of protective circuit of the present invention.Simultaneously referring to Fig. 5 and Fig. 6; Compare with the stackable switch of the above embodiment of the present invention; Among this embodiment, pile up socket 121 be provided with earth terminal (GND), first receive FPDP to RD+/-, first send FPDP to TD+/-, with the control signal port to Pre_R/Pre_L.Wherein, RD+/-respectively with the opposite end stackable switch on pile up TD+ on the socket/-dock, Pre_R/Pre_L respectively with the opposite end stackable switch on the Pre_L/Pre_R that piles up on the socket dock.Piling up on the socket 121, the stitch lengths of GND is the longest, RD+/-with TD+/-stitch lengths take second place, the stitch lengths of Pre_R/Pre_L is the shortest.Accordingly; In this embodiment; Protective circuit 14 specifically be used for pile up on the socket 121 Pre_R/Pre_L respectively with the opposite end stackable switch on pile up connection PCB cabling after Pre_L/Pre_R on the socket pegs graft and stackable switch normally powers on the opposite end stackable switch; Specifically; Set up the passage between a PCB cabling 131 and the 2nd PCB cabling 132 exactly, the Pre_R/Pre_L on piling up socket 121 respectively with the opposite end stackable switch on pile up and when Pre_L/Pre_R on the socket breaks off the PCB cabling.
In addition, ASIC111 be provided with second send FPDP to TX+/-with the second reception FPDP to RX+/-.As a specific embodiment of the present invention; Protective circuit 14 comprises diverter switch, and this diverter switch comprises: the first differential signal input, the second differential signal input, the 3rd differential signal input, the first differential signal output, the second differential signal output, the first binary channels single channel gate logic device, the second binary channels single channel gate logic device and the 3rd binary channels single channel gate logic device.Wherein, Shown in Fig. 7 a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, be respectively the structural representation of the present invention's first differential signal input, the second differential signal input, the 3rd differential signal input, the first differential signal output, the second differential signal output, the first binary channels single channel gate logic device, the second binary channels single channel gate logic device and the 3rd binary channels single channel gate logic device.Wherein, it is 0 o'clock in logical value that the first binary channels single channel gate logic device has been shown among Fig. 7 f, set up IN0+/-and OUT+/-between output channel; It is 1 o'clock in logical value that Fig. 7 g shows the second binary channels single channel gate logic device, set up IN1+/-and OUT0+/-between output channel; It is 1 o'clock in logical value that Fig. 7 h shows the 3rd binary channels single channel gate logic device, set up IN+/-and the 3rd binary channels single channel gate logic device on the single channel port between output channel.
Wherein, Input port IN+ on the first differential signal input/-respectively through electric capacity and TX+/-corresponding connection, the output port on the first differential signal input respectively with the second binary channels single channel gate logic device on an access port, an access port on the 3rd binary channels single channel gate logic device be connected.Input port IN0+ on the second differential signal input/-pull down to GND through electric capacity respectively, the output port on the second differential signal input respectively with the second binary channels single channel gate logic device on another access port, an access port on the first binary channels single channel gate logic device be connected.Input port IN1+ on the 3rd differential signal input/-respectively through electric capacity and TD+/-corresponding connection, the output port on the 3rd differential signal input respectively with the first binary channels single channel gate logic device on another access port, an access port on the second binary channels single channel gate logic device be connected.Output port OUT+ on the first differential signal output/-respectively through electric capacity and RX+/-corresponding connection, the input port on the first differential signal output is connected with single channel port on the first binary channels single channel gate logic device.Output port OUT0+ on the second differential signal output/-respectively through electric capacity and RD+/-corresponding connection; Input port on the second differential signal output is connected with single channel port on the second binary channels single channel gate logic device, and the second differential signal output is provided with the first enable logic control unit OE0, and this OE0 pulls down to GND through resistance; Being used in logical value is 0 o'clock; Make OUT0+/-the output high-impedance state, be 1 o'clock in logical value, make OUT0+/-normal output.Another access port on the first binary channels single channel gate logic device also with the second binary channels single channel gate logic device on another access port be connected; Output channel switch logic control pin MUX on the first binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up IN0+/-and OUT+/-between output channel, make IN0+/-on signal be input to OUT+/-, be 1 o'clock in logical value; Set up IN1+/-and OUT+/-between output channel, make IN1+/-on signal be input to OUT+/-.Output channel switch logic control pin MUX0 on the second binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up IN+/-and OUT0+/-between output channel, make IN+/-on signal be input to OUT0+/-, be 1 o'clock in logical value; Set up IN1+/-and OUT0+/-between output channel, make IN1+/-on signal be input to OUT0+/-.Single channel port on the 3rd binary channels single channel gate logic device is unsettled; Output channel switch logic control pin MUX1 on the 3rd binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up IN0+/-and the 3rd binary channels single channel gate logic device on the single channel port between output channel, make IN0+/-on the single channel port output of signal from the 3rd binary channels single channel gate logic device, be 1 o'clock in logical value; Set up IN+/-and the 3rd binary channels single channel gate logic device on the single channel port between output channel, make IN+/-on the single channel port output of signal from the 3rd binary channels single channel gate logic device.Pre L is through forgetting about it system power supply VCC on the resistance; Pre R pulls down to GND through resistance, and connects an input of AND circuit simultaneously, and another input of AND circuit pulls down to GND through resistance, and the output of AND circuit is connected with OE0 and MUX respectively.
Fig. 8 is the structural representation of another embodiment of protective circuit of the present invention.Compare with embodiment shown in Figure 6, among this embodiment, diverter switch also comprises the 3rd differential signal output port, and is as shown in Figure 9, is the structural representation of the present invention's the 3rd differential signal output.Please be simultaneously referring to Fig. 5, Fig. 8 and Fig. 9; Output port OUT1+ on the 3rd differential signal output/-unsettled, not shown among Fig. 5, the input port on the 3rd differential signal output is connected with single channel port on the 3rd binary channels single channel gate logic device; The 3rd differential signal output is provided with the second enable logic control unit OE1; This OE1 pulls down to GND through resistance, and being used in logical value is 0 o'clock, make OUT1+/-output high-impedance state; In logical value is 1 o'clock, make OUT1+/-normal output.Accordingly, MUX1 is 0 o'clock in logical value, set up IN0+/-and OUT1+/-between output channel; Make IN0+/-on signal be input to OUT1+/-; In logical value is 1 o'clock, set up IN+/-and OUT1+/-between output channel, make IN+/-on signal be input to OUT1+/-.As shown in table 1 below, be the control unit/pin and the function declaration thereof of diverter switch of the present invention.
Each pin and the function declaration thereof of table 1 diverter switch
Referring to Fig. 5, according to concrete an application of the present invention, the default conditions that diverter switch is set are:
MUX pulls down to GND through the 10K Ohmic resistance, and the logical value of configuration on the MUX is 0, also is designated as: MUX=0, make IN0+/-on signal can be input to OUT+/-;
MUX0 pulls down to GND through the 10K Ohmic resistance, and the logical value of configuration on the MUX0 is 0, also is designated as: MUX0=0, make IN+/-on signal can be input to simultaneously OUT0+/-;
MUX1 pulls down to GND through the 10K Ohmic resistance, and the logical value of configuration on the MUX1 is 0, also is designated as: MUX1=0, make IN0+/-on signal can be input to OUT1+/-;
OE0 pulls down to GND through the 10K Ohmic resistance; The logical value of configuration on the OE0 is 0, also is designated as: OE0=0, be provided with OUT0+/-be high-impedance state; So that Pre L effectively before, guarantee the port TX+ of exchanges data ASIC/-not destroyed by exterior static voltage or surge current;
OE1 pulls down to GND through the 10K Ohmic resistance, and the logical value of configuration on the OE1 is 0, also is designated as: configuration OE1=0, be provided with OUT1+/-be high-impedance state;
IN0+/-pull down to GND through electric capacity, with guarantee Pre_R effectively before, the port RX+ of exchanges data ASIC/-not destroyed by exterior static voltage or surge current;
Pre_L is through moving system power supply VCC on the 1K resistance, the Pre_R with the far-end stackable switch on physical connection is connected;
Pre_R has the affirmation signal that is connected and has normally powered on for the stackable switch at place with the far-end stackable switch, and height is effective, on the physical connection with the far-end stackable switch on Pre_L be connected.Piling up on the socket, this signal pin than GND, RD+/-and TD+/-short.Have only when piling up cable and insert socket fully, and remote equipment has been when also normally having powered on, the Pre_R signal is just drawn high, that is: logical value is 1; Otherwise Pre_R remains low, that is: logical value is 0.
When Pre_R=0, have three kinds of situation: first kind is: on the local stackable switch to pile up socket unsettled, that is: do not peg graft and pile up cable; Second kind is: have the cable of piling up unsettled, that is: this piles up the stackable switch that cable connects far-end; The third is: local stackable switch is connected through piling up cable with the far-end stackable switch, but the far-end stackable switch does not normally power on.Under these three kinds of situation; Diverter switch on the local stackable switch remains above-mentioned default conditions; With exchanges data ASIC with pile up external isolation such as socket, even if scurry into electrostatic potential piling up the socket place, also can be dissolved by withstand voltage diverter switch up to 4KV.
When Pre_R=1, expression stackable switch and far-end stackable switch are through piling up cable and be connected and the far-end stackable switch normally powering on.At this moment; Diverter switch is communicated with swap data ASIC and piles up socket; Make differential signal be transferred to swap data ASIC from piling up socket; Equally, the far-end stackable switch on also have same action, then local stackable switch and far-end stackable switch just can be realized proper communication.
In concrete application shown in Figure 5, the appearance value of 103 expression electric capacity, also promptly: 0.01 μ f.As another concrete application of the embodiment of the invention, the appearance value of electric capacity also can get 104.The resistance that in addition, also can have other resistance according to concrete application demand selection.
In addition; In the stackable switch of the above embodiment of the present invention; IN+/-, IN0+/-, IN1+/-, OUT+/-, OUT0+/-with OUT1+/-on can be connected an electrostatic discharge protection circuit respectively; Be used to detect the magnitude of voltage on the port that this electrostatic discharge protection circuit connects, at detected magnitude of voltage during greater than the predeterminated voltage value, the electric current on the port that is connected of releasing.Particularly, as one embodiment of the present of invention, electrostatic discharge protection circuit comprises electric capacity, IN+/-, IN0+/-, IN1+/-, OUT+/-, OUT0+/-with OUT1+/-in each port be connected an electric capacity respectively, the other end of electric capacity pulls down to GND.Particularly, the antistatic grade of electric capacity is 4KV, also can be the more high-antistatic grade greater than 4KV in addition, for example: 6KV.Shown in figure 10, be a structural representation of electrostatic discharge protection circuit of the present invention.Port wherein be IN+/-, IN0+/-, IN1+/-, OUT+/-, OUT0+/-or OUT1+/-, at detected magnitude of voltage during greater than the predeterminated voltage value, the electric current on the port that is connected of releasing.
After differential signal input/output end port place is provided with electrostatic discharge protection circuit; Magnitude of voltage on being applied to port is in predeterminated voltage value scope the time; Electrostatic discharge protection circuit can not start, and shown in arrow among Figure 10 1, differential signal can normally be sent into the internal layer circuit of diverter switch through port.And the magnitude of voltage on being applied to port is when surpassing the predeterminated voltage value, and electrostatic discharge protection circuit starts automatically, shown in arrow among Figure 10 2, with the current energy safety relief that flows into, with the internal circuit of switch protecting switch.In the time of in the magnitude of voltage on the port is reduced to predeterminated voltage value scope, electrostatic discharge protection circuit is closed automatically.According to an instantiation of the present invention; The predeterminated voltage value can be a concrete numerical value; For example: 3.3KV also can be the multiple of a stackable switch common voltage value, for example: 1.1 times; At this moment, electrostatic discharge protection circuit can protect 1.1 times of voltage ranges to antistatic grade from the normal voltage value.
The stackable switch that provides based on the above embodiment of the present invention is in piling up the cable insertion process, owing to piling up on the socket; The stitch lengths of GND is the longest; The stitch of differential signal comprise RD+/-with TD+/-length take second place, at first be that the stitch of GND and differential signal is pegged graft successively and put in place, be that Pre_L and Pre_R peg graft and put in place then; PRE_R is drawn high, that is: logical value becomes 1.In case PRE_R is drawn high, mean that piling up cable pegs graft and to put in place, and the far-end stackable switch powers on normally, just there is not the uncharged situation of load capacitance yet, then OE0 and MUX are drawn high, that is: logical value is changed to 1.OE0 was changed to 1 o'clock in logical value, make with IN+/-OUT0+ that is connected/-become normal output by high-impedance state, the IN+ that is conducting also/-to the path that piles up between the cable.And MUX was changed to 1 o'clock in logical value, break off IN0+/-and OUT+/-between output channel, set up simultaneously IN1+/-and OUT+/-between output channel, make IN1+/-on signal be input to OUT+/-, to be conducting also pile up cable and OUT+/-between path.Through above-mentioned flow process, the local stackable switch exchanges data of gating AISC and the differential signal path of piling up socket then can avoid because the momentary charge of load capacitance causes surge current, thereby play the purpose of protection swap data ASIC.
In can piling up the cable withdrawal process, owing to piling up on the socket contact pin shortlyer, at first be that Pre_L and PRE_R are pulled out, then Pre_R is dragged down immediately, that is: logical value becomes 0.After Pre_R was dragged down immediately, OE0 and MUX were dragged down, that is: logical value is changed to 0.OE0 was changed to 0 o'clock in logical value, make with IN+/-OUT0+ that is connected/-become high-impedance state by normal output, also promptly cut off IN+/-to the path that piles up between the cable.And MUX was changed to 0 o'clock in logical value, break off IN1+/-and OUT+/-between output channel, also promptly cut off pile up cable and OUT+/-between path, set up simultaneously IN0+/-and OUT+/-between output channel, make IN0+/-on signal be input to OUT+/-.Through above-mentioned flow process, diverter switch is closed exchanges data ASIC and the differential signal channel of piling up socket.And the GND on local at this moment and the far-end stackable switch also is in connection status; Guarantee that the two ends reference level is consistent; Produce surge current when avoiding the load capacitance discharge; Even and if producing surge current, the switching chip that also can be supported the hot plug function is dissolved, thereby plays the purpose of protection swap data ASIC.
The embodiment of the invention also provides a kind of switchboard stacked system, and it comprises a plurality of stackable switch that provide like the above embodiment of the present invention.In this switchboard stacked system, for each stackable switch, connected another stackable switch all is called the opposite end stackable switch.Shown in figure 11, be the structural representation of an embodiment of switchboard stacked system of the present invention, the annexation between any two stackable switch in the switchboard stacked system has been shown in this sketch map.
A kind of cable hot plugging method that the embodiment of the invention provides based on the foregoing description stackable switch; Comprise: ASIC and pile up the protective circuit that is provided with on the PCB cabling between the socket; Pile up that socket is pegged graft and stackable switch and opposite end stackable switch when normally powering on socket and the opposite end stackable switch detecting to pile up; Connect the PCB cabling, detecting when piling up piling up socket and will extract on socket and the opposite end stackable switch disconnection PCB cabling.
As a specific embodiment of cable hot plugging method of the present invention, before the piling up socket and peg graft on piling up socket and opposite end stackable switch, the logical value of MUX is 0, IN0+/-with OUT+/-set up output channel; The logical value of MUX0 is 0, IN+/-and OUT0+/-between set up output channel; The logical value of MUX1 is 0, IN0+/-and OUT1+/-between set up output channel; The logical value of OE0 is 0, make OUT0+/-output high-impedance state; The logical value of OE1 is 0, make OUT1+/-output high-impedance state; The last value of Pre_R is an invalid value.
Accordingly; Detect to pile up and pile up that socket is pegged graft and stackable switch normally powers on the opposite end stackable switch comprises on socket and the opposite end stackable switch: pile up on the socket Pre_R/Pre_L respectively with the opposite end stackable switch on pile up the Pre_L/Pre_R grafting on the socket, and the value on the Pre_R is changed to effective value.Connecting the PCB cabling comprises: when the value of MUX on Pre_R is effective value, logical value is changed to 1, set up IN1+/-with OUT+/-between output channel, and the value of OE0 on Pre_R be changed to 1 with logical value when being effective value, make OUT0+/-normally export.Detect and pile up piling up socket and will extract and comprise on socket and the opposite end stackable switch: pile up on the socket Pre_R/Pre_L respectively with the opposite end stackable switch on the Pre_L/Pre_R that piles up on the socket break off, and the value on the Pre_R is changed to invalid value.Breaking off the PCB cabling comprises: when the value of MUX on Pre_R is invalid value, logical value is changed to 0, set up IN0+/-with OUT+/-between output channel, and the value of OE0 on Pre_R be changed to 0 with logical value when being invalid value, make OUT0+/-export high-impedance state.
Further; In the specific embodiment of cable hot plugging method of the present invention; Can also comprise: IN+/-, IN0+/-, IN1+/-, OUT+/-, OUT0+/-with OUT1+/-on the electrostatic discharge protection circuit that is connected whether detect magnitude of voltage on the port that is connected respectively greater than the predeterminated voltage value; And whether the magnitude of voltage on the port that is connected during greater than the predeterminated voltage value, the electric current on the port that is connected of releasing.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be accomplished through the relevant hardware of program command; Aforesaid program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
The embodiment of the invention can detect pile up on socket and the opposite end stackable switch pile up whether socket pegs graft and whether stackable switch and opposite end stackable switch normally power on; Piling up piling up after socket grafting and stackable switch and opposite end stackable switch normally power on socket and the opposite end stackable switch; Just connect ASIC and pile up the PCB cabling between the socket; And detecting when piling up piling up socket and will extract on socket and the opposite end stackable switch; Break off ASIC and pile up the PCB cabling between the socket, thereby avoid the hot plug of cable that ASIC is caused damage, and then effectively prevent in the hot plug process of cable, stackable switch to be caused damage; Promote the antistatic surge capacity of plug of port, improve the hot plug protective capacities and the reliability of whole switchboard stacked system.
It should be noted last that: above embodiment is only in order to explaining technical scheme of the present invention, but not the present invention is made restrictive sense.Although the present invention is specified with reference to above-mentioned preferred embodiment; Those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and this modification or be equal to spirit and the scope that replacement does not break away from technical scheme of the present invention.
Claims (11)
1. a stackable switch comprises mainboard and piles up daughter board, and said mainboard comprises the exchanges data application-specific integrated circuit ASIC; The said daughter board that piles up is provided with and piles up socket; Said ASIC is connected with the printing board PCB cabling with said piling up between the socket, it is characterized in that
Said ASIC and the said PCB cabling that piles up between the socket are provided with protective circuit;
Said pile up socket be provided with earth terminal GND, first receive FPDP to RD+/-, first send FPDP to TD+/-, with the control signal port to Pre_R/Pre_L; Said RD+/-respectively with the opposite end stackable switch on pile up TD+ on the socket/-dock, said Pre_R/Pre_L respectively with said opposite end stackable switch on the Pre_L/Pre_R that piles up on the socket dock; Pile up on the socket said, the stitch lengths of said GND is the longest, said RD+/-with said TD+/-stitch lengths take second place, the stitch lengths of said Pre_R/Pre_L is the shortest;
Said protective circuit specifically be used for said pile up on the socket Pre_R/Pre_L respectively with said opposite end stackable switch on pile up the said PCB cabling of connection after Pre_L/Pre_R on the socket pegs graft and said stackable switch normally powers on said opposite end stackable switch; Said pile up on the socket Pre_R/Pre_L respectively with said opposite end stackable switch on pile up and when Pre_L/Pre_R on the socket breaks off said PCB cabling, said ASIC be provided with second send FPDP to TX+/-with the second reception FPDP to RX+/-;
Said protective circuit comprises diverter switch, and this diverter switch comprises: the first differential signal input, the second differential signal input, the 3rd differential signal input, the first differential signal output, the second differential signal output, the first binary channels single channel gate logic device, the second binary channels single channel gate logic device and the 3rd binary channels single channel gate logic device;
Input port IN+ on the said first differential signal input/-respectively through electric capacity and said TX+/-corresponding connection, the output port on the said first differential signal input respectively with the said second binary channels single channel gate logic device on an access port, an access port on said the 3rd binary channels single channel gate logic device be connected;
Input port IN0+ on the said second differential signal input/-pull down to GND through electric capacity respectively, the output port on the said second differential signal input respectively with said the 3rd binary channels single channel gate logic device on another access port, an access port on the said first binary channels single channel gate logic device be connected;
Input port IN1+ on said the 3rd differential signal input/-respectively through electric capacity and said TD+/-corresponding connection, the output port on said the 3rd differential signal input respectively with the said first binary channels single channel gate logic device on another access port, another access port on the said second binary channels single channel gate logic device be connected;
Output port OUT+ on the said first differential signal output/-respectively through electric capacity and said RX+/-corresponding connection, the input port on the said first differential signal output is connected with single channel port on the said first binary channels single channel gate logic device;
Output port OUT0+ on the said second differential signal output/-respectively through electric capacity and said RD+/-corresponding connection; Input port on the said second differential signal output is connected with single channel port on the said second binary channels single channel gate logic device; The said second differential signal output is provided with the first enable logic control unit OE0; This OE0 pulls down to GND through resistance, and being used in logical value is 0 o'clock, make OUT0+/-output high-impedance state; In logical value is 1 o'clock, make OUT0+/-normal output;
Another access port on the said first binary channels single channel gate logic device also with the said second binary channels single channel gate logic device on another access port be connected; Output channel switch logic control pin MUX on the said first binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up said IN0+/-and said OUT+/-between output channel, be 1 o'clock in logical value, set up said IN1+/-and said OUT+/-between output channel;
Output channel switch logic control pin MUX0 on the said second binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up said IN+/-and said OUT0+/-between output channel; In logical value is 1 o'clock, set up said IN1+/-and said OUT0+/-between output channel;
Single channel port on said the 3rd binary channels single channel gate logic device is unsettled; Output channel switch logic control pin MUX1 on said the 3rd binary channels single channel gate logic device pulls down to GND through resistance; In logical value is 0 o'clock; Set up said IN0+/-and said the 3rd binary channels single channel gate logic device on the single channel port between output channel, be 1 o'clock in logical value, set up said IN+/-and said the 3rd binary channels single channel gate logic device on the single channel port between output channel;
Said Pre_L is through moving system power supply VCC on the resistance; Said Pre_R pulls down to GND through resistance, and connects an input of AND circuit simultaneously, and another input of said AND circuit pulls down to GND through resistance, and the output of said AND circuit is connected with said OE0 and said MUX respectively.
2. stackable switch according to claim 1 is characterized in that, said mainboard is connected with socket between plate with said piling up between the daughter board;
Said ASIC with said pile up between the socket to be connected with the printing board PCB cabling be specially: be connected with a PCB cabling between the socket between said ASIC and said plate, be connected with the 2nd PCB cabling between socket and the said protective circuit between said plate.
3. stackable switch according to claim 1 is characterized in that, said stackable switch and said opposite end stackable switch normally power on and be specially: the said magnitude of voltage that piles up on the socket belongs to the normal voltage value scope that is provided with in advance.
4. stackable switch according to claim 1; It is characterized in that; Said IN+/-, said IN0+/-, said IN1+/-, said OUT+/-with said OUT0+/-on be connected an electrostatic discharge protection circuit respectively; Be used to detect the magnitude of voltage on the port that is connected, at detected magnitude of voltage during greater than the predeterminated voltage value, the electric current on the port that is connected of releasing.
5. stackable switch according to claim 4; It is characterized in that; Said electrostatic discharge protection circuit comprises electric capacity; Said IN+/-, said IN0+/-, said IN1+/-, said OUT+/-, said OUT0+/-with said OUT1+/-in each port be connected an electric capacity respectively, the other end of electric capacity pulls down to GND.
6. stackable switch according to claim 5 is characterized in that, the antistatic grade of said electric capacity is 4KV.
7. a switchboard stacked system is characterized in that, comprises a plurality of like any described stackable switch of claim 1 to 6.
8. the cable hot plugging method based on any stackable switch of claim 1 to 6 is characterized in that, comprising:
ASIC and pile up the protective circuit that is provided with on the PCB cabling between the socket; Pile up that socket is pegged graft and said stackable switch and said opposite end stackable switch when normally powering on socket and the opposite end stackable switch detecting said piling up; Connect said PCB cabling; Detecting saidly when piling up piling up socket and will extract on socket and the opposite end stackable switch, breaking off said PCB cabling.
9. method according to claim 8 is characterized in that, said pile up piling up socket and peg graft on socket and the opposite end stackable switch before, the logical value of MUX is 0, IN0+/-with OUT+/-set up output channel; The logical value of MUX0 is 0, IN+/-and OUT0+/-between set up output channel; The logical value of OE0 is 0, make OUT0+/-output high-impedance state; The last value of Pre_R is an invalid value.
10. method according to claim 9; It is characterized in that; Detect said piling up and pile up that socket is pegged graft and said stackable switch normally powers on said opposite end stackable switch comprises on socket and the opposite end stackable switch: said pile up on the socket Pre_R/Pre_L respectively with said opposite end stackable switch on pile up the Pre_L/Pre_R grafting on the socket, and the value on the said Pre_R is changed to effective value;
Connecting said PCB cabling comprises: when the value of said MUX on said Pre_R is effective value; Logical value is changed to 1; Set up said IN1+/-and said OUT+/-between output channel; And the value of said OE0 on said Pre_R be changed to 1 with logical value when being effective value, make OUT0+/-normal output;
Detect said the piling up socket and will extract and comprise on socket and the opposite end stackable switch of piling up: said pile up on the socket Pre_R/Pre_L respectively with said opposite end stackable switch on the Pre_L/Pre_R that piles up on the socket break off, and the value on the said Pre_R is changed to invalid value;
Breaking off said PCB cabling comprises: when the value of said MUX on said Pre_R is invalid value; Logical value is changed to 0; Set up said IN0+/-and said OUT+/-between output channel; And the value of said OE0 on said Pre_R be changed to 0 with logical value when being invalid value, make OUT0+/-the output high-impedance state.
11. method according to claim 9 is characterized in that, also comprises:
Said IN+/-, said IN0+/-, said IN1+/-, said OUT+/-with said OUT0+/-on the electrostatic discharge protection circuit that is connected whether detect magnitude of voltage on the port that is connected respectively greater than the predeterminated voltage value; And the magnitude of voltage on the port that is connected is during greater than the predeterminated voltage value, the electric current on the port that is connected of releasing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910090419XA CN101626299B (en) | 2009-08-04 | 2009-08-04 | Stackable switch, switch stacking system and cable hot plugging method |
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| CN200910090419XA CN101626299B (en) | 2009-08-04 | 2009-08-04 | Stackable switch, switch stacking system and cable hot plugging method |
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| CN101626299A CN101626299A (en) | 2010-01-13 |
| CN101626299B true CN101626299B (en) | 2012-03-07 |
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| WO2016082095A1 (en) * | 2014-11-25 | 2016-06-02 | Source Photonics (Chengdu) Co., Ltd. | Dc level detection circuit between high speed signal line connecting ports, system including the circuit, and methods of making and using the same |
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| CN1459906A (en) * | 2002-05-22 | 2003-12-03 | 上海贝尔有限公司 | New distribution type power supply system |
| CN1614851A (en) * | 2003-11-06 | 2005-05-11 | 明基电通股份有限公司 | Protecting circuit and peripheral apparatus with protecting circuit and application |
| CN1630155A (en) * | 2003-12-19 | 2005-06-22 | 明基电通股份有限公司 | Power supply protective device and electronic device with protective device |
| CN1731362A (en) * | 2005-08-24 | 2006-02-08 | 杭州华为三康技术有限公司 | Harddisk hot-swap protection system and method |
| CN101378339A (en) * | 2008-10-07 | 2009-03-04 | 北京星网锐捷网络技术有限公司 | Control method and apparatus, business board for heat insertion and pull |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1459906A (en) * | 2002-05-22 | 2003-12-03 | 上海贝尔有限公司 | New distribution type power supply system |
| CN1614851A (en) * | 2003-11-06 | 2005-05-11 | 明基电通股份有限公司 | Protecting circuit and peripheral apparatus with protecting circuit and application |
| CN1630155A (en) * | 2003-12-19 | 2005-06-22 | 明基电通股份有限公司 | Power supply protective device and electronic device with protective device |
| CN1731362A (en) * | 2005-08-24 | 2006-02-08 | 杭州华为三康技术有限公司 | Harddisk hot-swap protection system and method |
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