CN101621083A - Semiconductor solar cells having front surface electrodes and method for manufacturing the same - Google Patents
Semiconductor solar cells having front surface electrodes and method for manufacturing the same Download PDFInfo
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- CN101621083A CN101621083A CN200910139382A CN200910139382A CN101621083A CN 101621083 A CN101621083 A CN 101621083A CN 200910139382 A CN200910139382 A CN 200910139382A CN 200910139382 A CN200910139382 A CN 200910139382A CN 101621083 A CN101621083 A CN 101621083A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides semiconductor solar cells having front surface electrodes and method for manufacturing the same. Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.
Description
Technical field
The present invention relates to solar cell and forming method thereof, more specifically, relate to semiconductor solar cell and forming method thereof.
Background technology
Solar cell is the device that solar energy (for example sunlight) is converted to electricity.Solar cell has many application.Single battery can be used for to the midget plant energy supply, and the battery (for example, photovoltaic array) of big array can be used to produce a kind of renewable energy, and this renewable energy is particularly useful under the situation that can not obtain from the electric energy of electrical network (power grid).Solar battery array also is used for electric power system (grid-based electrical system) based on grid by development now.
Solar cell incides the photon of substrate by response the middle electron-hole pair that produces of substrate (for example semiconductor substrate) that is absorbed in comes work.When photon was absorbed, its energy was passed to the electronics in the lattice of substrate.Usually, this electronics is in the valence band of lattice and be strapped in tightly in the covalent bond between the adjacent atom.The energy of being passed to electronics by photon can enough be used for electron excitation in the conduction band of lattice, and this electronics becomes and moves freely in substrate in conduction band then.Electronics is that its a part of covalent bond has lacked an electronics now before, and it is called as " hole ".The existence of the covalent bond that lacks allows to be somebody's turn to do " hole " from the bound electron immigration of adjacent atom, and the back stays another hole, and the hole can be moved at whole lattice by this way.Electronics and hole should move in substrate can be used to set up the direct voltage that process is connected to the load of solar cell then.
Particularly, be created in internal electric field in the p-n junction and can cause enough that electronics and hole in the electron-hole pair move to n N-type semiconductor N district and p N-type semiconductor N district respectively.Use p-n junction and disclosed in United States Patent(USP) Nos. 4726850 and 4748130 in an example of the solar cell of the electrode pair on the apparent surface of semiconductor substrate.Another example of solar cell is called in the U.S. Patent No. 7335555 of " Buried-Contact Solar Cell With Self-Doping Contacts (contact solar cell of burying with autodoping contact) " disclosed in people such as Gee, name.
Summary of the invention
Solar cell according to the embodiment of the invention comprises substrate, and the light that this substrate has is thereon collected surface and the P-N rectifying junction in substrate.The P-N rectifying junction comprises: the base of first conductivity type (for example p type) and the semiconductor layer of collecting second conductivity type that extends between the surface at base and light.Also be provided with and extend through semiconductor layer and to enter groove in the base.First electrode and the second electrode adjacent light are collected the surface and are provided with.First electrode is conductively coupled to semiconductor layer, and second electrode is conductively coupled to the base in the position of adjacent trenches bottom.
According to additional embodiment of the present invention, solar cell can also comprise the electric insulation trench sidewall spacer thing on the trenched side-wall, and it extends between the semiconductor layer of second electrode and second conductivity type and provides electricity between the two to isolate.In addition, the semiconductor layer of second conductivity type can be the amorphous silicon layer that has different band gap with respect to monocrystalline silicon.Particularly, the semiconductor layer of second conductivity type can be the amorphous silicon layer that forms heterojunction in the substrate.Can also comprise the boundary layer of second conductivity type according to the solar cell of these embodiment, it extends between the semiconductor layer of second conductivity type and base.The boundary layer of second conductivity type can form non-rectification heterojunction with the semiconductor layer of second conductivity type and form the P-N rectifying junction with the base.
Embodiments of the invention also are included in light and collect lip-deep anti-reflecting layer.Light is collected the surface can be configured to have the peak of band localization and the heterogeneous surface profile of paddy.Particularly, non-rectification heterojunction can have the non-planar junction profile, and light is collected the heterogeneous surface profile that the surface can have the non-planar junction profile that approaches non-rectification heterojunction.And non-rectification heterojunction can have the first non-planar junction profile, and the rectifying junction between boundary layer and base can have the second non-planar junction profile of the shape that approaches the first non-planar junction profile.
Additional embodiment of the present invention comprises the method that forms solar cell.In these methods some are included in semiconductor substrate (base that wherein has first conductivity type (for example p type)) and go up the semiconductor layer that forms second conductivity type (for example n type).Also form first groove, it extends through the semiconductor layer of second conductivity type and enters in the base.The step that forms first groove can form after the step of anti-reflecting layer on the semiconductor layer of second conductivity type.The trench sidewall spacer thing is formed on the sidewall of first groove.Also form second groove, it extends through the stepping of going forward side by side of first channel bottom and goes in the base.First groove and second groove can be the strip-shaped grooves of extend past substrate.Second groove is filled with first electrode, and first electrode is conductively coupled to the base.Fill the step of second groove can be in bottom that first type conductivity dopant is injected into second groove and sidewall after.Second electrode can also form with the semiconductor layer of second conductivity type and contact.Second electrode can be formed on the outside and/or inner of first groove.
According among these methods embodiment some, the step that forms first groove can form in the base after the step in boundary layer of second conductivity type.Thereby the boundary layer can be transformed into clean second conductivity type from first conductivity type by the part that will be diffused into from second type conductivity dopant of the q.s of semiconductor layer in the base the base.The boundary layer can form non-rectification heterojunction with semiconductor layer, and this semiconductor layer can comprise amorphous silicon.Semiconductor layer can form by the in-situ doped amorphous silicon layer of deposition on the surface of substrate.This surface can have surface profile heterogeneous (Feng Hegu that wherein has localization).
The method of the formation solar cell of additional embodiment comprises that the surface texturizing (texturize) of the silicon wafer that makes the base with first conductivity type is to produce the Feng Hegu of localization in the surface according to the present invention.After the veining of surface, the in-situ doped amorphous silicon layer of second conductivity type can deposit on the surface of veining, thereby definition has the non-rectification heterojunction of this surperficial veining.Amorphous silicon layer can have therein about 1 * 10
19Cm
-3To about 1 * 10
21Cm
-3Doping content in the scope.Then, thereby be transformed into clean second conductivity type by the part that will be diffused into from second type conductivity dopant of the q.s of amorphous silicon layer in the base the base from clean first conductivity type, the boundary layer of second conductivity type is formed in the base.Form groove then, this groove extends through amorphous silicon layer and boundary layer and enters in the base.Also form first electrode and second electrode.First electrode is conductively coupled to amorphous silicon layer, and the second electrode adjacent trenches bottom electrical is couple to the base.In these embodiment of the present invention some, the step that forms first electrode and second electrode is included in bottom deposit second electrode of groove and covers second electrode at the electricity consumption dielectric spacer layer and deposits first electrode in the adjacent trenches top afterwards.
According to the embodiments of the invention some, the step of veining comprise that being exposed to the etchant that causes on this surface forming residue by the surface with silicon wafer comes the etching should the surface, and it is as further etched localization etching mask.Particularly, the step of surface texturizing can be comprised the surface is exposed to the dry ecthing agent that contains chlorine and fluorine.Particularly, the dry ecthing agent can be passed through chlorine (Cl
2), oxygen (O
2) and SF
6Source gas mixes in low pressure process chamber and forms.
According to additional embodiment of the present invention, the step that forms the boundary layer comprises by the annealing temperature in the scope of amorphous silicon layer between about 500 ℃ to about 900 ℃ of second conductivity type is formed having from pact
To about
The boundary layer of the preferred thickness in the scope.And the step that forms groove can comprise by form a plurality of right-angled intersections (criss-crossing) groove in the surface of silicon wafer and forms latticed groove.Latticed groove can also comprise the outermost annular groove of adjacent silicon wafer periphery.Can also be after forming the step of first electrode, the part of the part of first electrode and following electric insulation wall in the selective removal ring-shaped groove, thus expose second electrode.
Description of drawings
Fig. 1 is the sectional view according to the integrated circuit solar cell of the embodiment of the invention;
Fig. 2 is the amplification sectional view of ledge of the solar cell of Fig. 1;
Fig. 3-the 9th, the sectional view of structure between two parties, it combines the method for formation according to the integrated circuit solar cell of the embodiment of the invention that illustrate with Fig. 1;
Figure 10 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 10 B is that the integrated circuit solar cell I-I ' along the line of Figure 10 A cuts open the sectional view of getting;
Figure 11 is the amplification sectional view of ledge of the solar cell of Figure 10 B;
Figure 12 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 12 B is that the I-I ' along the line of the integrated circuit solar cell of Figure 12 A cuts open the sectional view of getting;
Figure 12 C is the alternative cross sections figure of I-I ' along the line of the integrated circuit solar cell of Figure 12 A;
Figure 13 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 13 B is that the I-I ' along the line of the integrated circuit solar cell of Figure 13 A cuts open the sectional view of getting;
Figure 14 A-20A is the plane graph of structure between two parties, and it illustrates the method for formation according to the integrated circuit solar cell of the embodiment of the invention;
Figure 14 B-20B is that the I-I ' along the line of the structure between two parties of Figure 14 A-20A cuts open the sectional view of getting;
Figure 21 A-23A is the plane graph of structure between two parties, and it illustrates formation each method by the integrated circuit solar cell shown in Figure 12 A and the 12C according to the embodiment of the invention;
Figure 21 B-23B is that the I-I ' along the line of the structure between two parties of Figure 21 A-23A cuts open the sectional view of getting;
Figure 24 A-25A is the plane graph of structure between two parties, and it illustrates formation each method according to the integrated circuit solar cell of the embodiment of the invention;
Figure 24 B-25B is that the I-I ' along the line of the structure between two parties of Figure 24 A-25A cuts open the sectional view of getting;
Figure 26 is the block diagram that can use according to the photovoltaic system of the integrated circuit solar cell of the embodiment of the invention;
Figure 27 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 27 B is that the I-I ' along the line of the solar cell embodiment of Figure 27 A cuts open the sectional view of getting.
Figure 28 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 28 B is that the I-I ' along the line of the solar cell embodiment of Figure 28 A cuts open the sectional view of getting;
Figure 29 A is the sectional view according to the integrated circuit solar cell of the embodiment of the invention;
Figure 29 B is that the I-I ' along the line of the solar cell embodiment of Figure 29 A cuts open the sectional view of getting;
Figure 30 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 30 B is that the I-I ' along the line of the solar cell embodiment of Figure 30 A cuts open the sectional view of getting;
Figure 31 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 31 B is that the I-I ' along the line of the solar cell embodiment of Figure 31 A cuts open the sectional view of getting;
Figure 32 A is the plane according to the integrated circuit solar cell of the embodiment of the invention;
Figure 32 B is that the I-I ' along the line of the solar cell embodiment of Figure 32 A cuts open the sectional view of getting;
Figure 33 is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 34 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 34 B is that the I-I ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting;
Figure 34 C is that the II-II ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting;
Figure 35 is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 36 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 36 B is that the I-I ' along the line of the solar cell embodiment of Figure 36 A cuts open the sectional view of getting;
Figure 37 A is the plane graph according to the integrated circuit solar cell of the embodiment of the invention;
Figure 37 B is that the I-I ' along the line of the solar cell embodiment of Figure 37 A cuts open the sectional view of getting.
Embodiment
Now with reference to accompanying drawing the present invention is described more fully, the preferred embodiments of the present invention have been shown in the accompanying drawing.Yet the present invention can should not be construed as limited to example embodiment described herein with multiple different forms enforcement; On the contrary, it is in order to make the disclosure thoroughly and complete that these embodiment are provided, and scope of the present invention is fully conveyed to those skilled in the art.Identical Reference numeral refers to components identical all the time, holding wire with and on signal can represent with identical reference symbol.
Should be understood that, in specification when claim layer (or a film) " " another layer or substrate " on " time, can perhaps can also there be the layer of insertion in it directly on another layer or substrate.And in the accompanying drawings, in order to be shown clearly in, the size in layer and zone can be by exaggerative.In addition, be used for describing different zone of different embodiments of the invention and layer as the word of " first ", " second " and " the 3rd ", these zones and layer are not limited to these words.These words only are used for a zone or layer with another zone or layer differentiate.Therefore, the layer that is called as " ground floor " in one embodiment can be called " second layer " in another embodiment.
Referring now to Fig. 1-2, can comprise substrate according to the solar cell of the embodiment of the invention with upper surface and basal surface, upper surface represents that light collects the surface, basal surface and upper surface relatively extend.Substrate is depicted as and comprises semiconductor substrate region 110, and it can mix with first type conductivity dopant (for example p type dopant).Particularly, substrate zone 110 can be initially p type silicon single crystal wafer, and it can stand by the semiconductor processes step shown in Fig. 3 that will be described below-9.Substrate can also be included in the semiconductor layer 120 of second conductivity type (for example n type) that extends on the substrate zone 110.The upper surface of the semiconductor layer 120 of second conductivity type can be collected the surface as light, and anti-reflecting layer 131 can be formed on light and collect on the surface.The purpose of anti-reflecting layer 131 can be to provide the light collection efficiency etc. of increase by reducing reflection that incident light collects the surface away from light.
Specifically illustrate as Fig. 2 (it has been given prominence to by the zone shown in Fig. 1 " A "), substrate zone 110 comprises base (base region) 110b of clean first conductivity type (for example p type) and the boundary layer 110a of clean second conductivity type, and boundary layer 110a and base 110b form the P-N rectifying junction.Describe more fully as following, this boundary layer 110a can form by the dopant (for example n type dopant) of q.s is diffused into the base 110b from the semiconductor layer 120 of second conductivity type, thereby the part of base 110b is transformed into clean second conductivity type from first conductivity type.
The semiconductor layer 120 of the boundary layer 110a and second conductivity type can form the conduction region 122 of second conductivity type jointly.In addition, the semiconductor layer 120 of second conductivity type can form amorphous silicon layer, and itself and boundary layer 110a form non-rectification heterojunction.Thereby can be captured near the wave-length coverage that the P-N knot, produces electron-hole pair by increasing, can help supporting higher light collection efficiency with respect to this heterojunction of homojunction.Semiconductor layer 120 can be high relatively doped layer, and for example it can form the have second conductivity type in-situ doped semiconductor layer of (for example phosphorus), and wherein doping content is about 10
19Cm
-3To about 10
21Cm
-3In the scope.The thickness of boundary layer 110a is chosen as by reduce electronics-hole-recombination of not expecting near the P-N knot and increases solar battery efficiency.Although do not wish by any theory constraint, but thick inadequately boundary layer 110a can be relevant with the electronics-hole-recombination of relative elevation degree, and this electronics-hole-recombination is caused by the boundary defect at the heterojunction place between the semiconductor layer 120 of the boundary layer 110a and second conductivity type.Alternatively, blocked up boundary layer 110a can be by high relatively electronics-hole-recombination restriction, and this electronics-hole-recombination is caused through the wide depletion region around the P-N knot by excessive charge carrier drift (migration just).Consider, to have from approximately for given semi-conducting material based on these
To about
The boundary layer 110a of the thickness in the scope can support the light collection efficiency of high level by minimizing electronics-hole-recombination wherein.
Anti-emission layer 131 (it can be deposited on the semiconductor layer 120 of second conductivity type) thus the thickness that can have about λ/4 increases efficiency of light absorption, wherein λ will be incident on light during the solar cell working to collect lip-deep expectation light wavelength.And anti-reflecting layer 131 can form sandwich construction, for example comprises the layer of silicon oxide layer and silicon-nitride layer.Except increasing the light collection efficiency of solar cell, anti-reflecting layer 131 can also be used for protection and provide electric passivation (electrical passivation) to collect the surface to the following light of solar cell.
Also with reference to Fig. 2, light is collected surface (its be depicted as the semiconductor layer 120 of second conductivity type and the interface between the anti-reflecting layer 131) can be configured to have surface profile heterogeneous, has the Feng Hegu of localization in surface profile.This heterogeneous surface profile can show as the projection at a plurality of isolated Pyramids shown in the surface of anti-reflecting layer 131.Particularly, can have the non-planar junction profile at the semiconductor layer 120 of second conductivity type and the non-rectification heterojunction between the 110a of boundary layer, light is collected the heterogeneous surface profile that the surface can have the non-planar junction profile that approaches non-rectification heterojunction.And non-rectification heterojunction can have the first non-planar junction profile, and the rectifying junction between boundary layer 110a and base 110b can have the second non-planar junction profile of the shape that approaches the first non-planar junction profile.
The solar cell of Fig. 1 comprises that also being arranged on light collects lip-deep electrode pair.This electrode pair is depicted as first electrode 141 (it is conductively coupled to base 110b) and second electrode 143 (it is conductively coupled to the semiconductor layer 120 of second conductivity type).These electrodes can be the strip shaped electric poles with narrow relatively width, and it has reduced shade (shading) loss of collecting the surface at light.First electrode 141 and second electrode 143 can be formed by at least a metal that is selected from the group of being made up of aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN).Electrode 141 and 143 can also comprise metal silicide layer and/or multi-layer conductive for example Ti/TiN/Al or Ti/TiN/W.
Groove 116 can also be set, and it extends through the semiconductor layer 120 of second conductivity type and enters base 110b.Explain more fully that as following groove 116 can be formed by last strip-shaped grooves 113 and following strip-shaped grooves 114, this time strip groove 114 extends through the bottom of groove 113.Lower groove 114 for example can have from about 0.3 micron width in about 1 micrometer range, and has the strip or the analogous shape of extend past substrate.The sidewall of last groove 113 can be adorned and be lined with electric insulation sidewall spacer 115, and it can for example form oxide and/or insulating nitride layer.These sidewall spacers 115 play the effect that first electrode 141 is electrically insulated from the semiconductor layer 120 of second conductivity type.And the highly doped relatively impurity range 117 of first conductivity type can be formed in the sidewall of lower groove 114 and the bottom to reduce the series resistance between the first interior electrode 141 of base 110b and lower groove 114.Impurity range 117 can for example have about 0.3 micron thickness.As shown in the figure, shallow relatively groove/recess 118 can also be formed in the semiconductor layer 120 also with 143 fillings of second electrode.
Fig. 3-9 shows other embodiments of the invention, and it comprises the method for the solar cell that forms Fig. 1-2.As shown in Figure 3, these methods can be included in the optional step in back of the body surface field (BSF) district 111 that forms first conductivity type (for example P type) in the semiconductor substrate 110 of first conductivity type (for example P type wafer), the formation in back of the body surface field (BSF) district 111 of first conductivity type is by relative front surface that first type conductivity dopant (for example boron (B)) is injected substrate 110 and back of the body surface, thereby heat treatment substrate 110 advances the dopant that injects then.After this, as shown in Figure 4, the front surface of substrate 110 can become uneven by producing a plurality of peaks and paddy therein.These peaks in the front surface are shown as has pyramid or similar structures 112, and can use conventional art to form for example plasma etching, mechanical scribing (mechanical scribing), photoetching and chemical etching.For example, the oxide layer (not shown) can form the sacrifice layer on the front surface of substrate 110, uses the photoresist layer (not shown) of patterning to come lithographic patterning as etching mask then.The front surface of substrate 110 can use patterned sacrificial layers to come etched as etching mask then.During this technology, any BSF district 111 on the front surface of substrate 110 typically is removed.
Referring now to Fig. 5, noncrystal semiconductor layer 120 is formed on the front surface of injustice of substrate 110.This noncrystal semiconductor layer 120 can be clean second conductivity type (for example N type) highly doped (for example in-situ doped) layer.Particularly, the second conductivity type doping content in the noncrystal semiconductor layer 120 can be from about 1 * 10
19Cm
-3To about 1 * 10
21Cm
-3In the scope.(it can have from about hundreds of dust to about noncrystal semiconductor layer 120
Thickness in the scope typically is approximately
) can use various technology to be deposited.These technology comprise plasma enhanced chemical vapor deposition (PECVD) or the low pressure chemical vapor deposition that uses silane and hydrogen.Particularly, in-situ doped noncrystal semiconductor layer 120 can use silane (SiH by chemical vapour deposition (CVD)
4), hydrogen phosphide (PH
3) and hydrogen formation.
Also with reference to Fig. 5, the boundary layer 110a of second conductivity type forms by second type conductivity dopant is diffused into the substrate 110 from noncrystal semiconductor layer 120, thus definition boundary layer 110a, and the base 110b of the boundary layer 110a and first conductivity type forms the P-N rectifying junction.This diffusion of second type conductivity dopant can be undertaken by substrate 110 is annealed.In order to increase solar battery efficiency by reduce the electronics-hole-recombination do not expect near the P-N rectifying junction, annealing can be carried out enough duration in enough temperature and have from approximately with generation
To about
The boundary layer 110a of the thickness in the scope.According to some embodiment of the present invention, the unevenness on the surface of noncrystal semiconductor layer 120 can also increase by hemispherical silicon grain (HSG) layer of growing on noncrystal semiconductor layer 120, thereby increases the light collection efficiency of solar cell.Alternatively, the conductive euphotic zone (for example ZnO layer) with rough surface structure can be deposited on the noncrystal semiconductor layer 120.
Shown in Fig. 6-7, then, anti-reflecting layer 131 is formed on the noncrystal semiconductor layer 120.Anti-reflecting layer 131 can form by using conventional deposition processes (for example plasma activated chemical vapour deposition (PECVD)) one or more electric insulation layers (for example silicon dioxide, silicon nitride) to be deposited on the upper surface of noncrystal semiconductor layer 120.In order to increase efficiency of light absorption, anti-reflecting layer 131 can have the thickness of about λ/4, and wherein λ is incident on light to collect lip-deep expectation light wavelength during solar cell working.Then, can carry out lithographic definition etching step (for example dry etching) extends through noncrystal semiconductor layer 120 and boundary layer 110a and enters base 110b with narrow relatively strip first groove 113, the first grooves 113 of definition.In these embodiment of part of the present invention, strip first groove 113 can have about 1 μ m or littler width.For example, strip-shaped grooves can have the width of about 0.3 μ m.
Lateral wall insulation sept 115 is formed on the sidewall of first groove 113.These lateral wall insulation septs 115 can form silicon dioxide layer or silicon-nitride layer or form the compound of a plurality of insulating barriers.Lateral wall insulation sept 115 can by with the electric insulation layer conformal deposited in first groove 113 then anisotropy eat-back layer that (etch back) deposited and be exposed up to the bottom of first groove 113 and form.This step of conformal deposited electric insulation layer can be included in deposition protection insulating barrier 132 on the basal surface of substrate 110.
Referring now to Fig. 8, use the first mask (not shown) and lateral wall insulation sept 115 bottom as further etching first groove 113 of etching mask.This etching step causes the formation of extension groove 114, and extension groove 114 can extend in fact among the base 110b.First groove and the extension groove 114 common multistage grooves 116 that form with the upper side wall that is covered by lateral wall insulation sept 115.The step that forms extension groove 114 can then be injected first type conductivity dopant (for example P type dopant) forms relative highly doped impurity range 117 to the bottom and the sidewall of extension groove 114 step by selectivity.As shown in Figure 9, then carry out selective etch step with etching relatively shallow second groove 118, the second grooves 118 extend through anti-reflecting layer 131 and enter amorphous silicon layer 120 thereafter.Second groove 118 forms more shallow than P-N rectifying junction.Then, the multistage groove 116 and second groove 118 are filled with first electrode 141 and second electrode 143 respectively, as shown in Figure 1.These first electrodes 141 and second electrode 143 can patterned metal layer forms by depositing then.Metal level can be formed by at least a metal of selecting the group of forming from the silicide of aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and these metals.Particularly, according to some embodiment of the present invention, metal level can be Ti/TiN/Al or Ti/TiN/W layer.After forming these first electrodes 141 and second electrode 143, can carry out the step of in hydrogeneous atmosphere, electrode being annealed.This hydrogen annealing can play the effect that activates N type dopant in the substrate, thereby improves electron mobility, can also eliminate the defective in the substrate surface, thereby reduces the Leakage Current of duration of work.
Referring now to Figure 10 A-10B and Figure 11, the solar cell of additional embodiment is depicted as and is formed in the semiconductor substrate 1110 (for example single crystal semiconductor (for example silicon) wafer) according to the present invention, and semiconductor substrate 1110 has the base 1111 of first conductivity type (for example P type) therein.Highlight as the zone among Figure 10 B and Figure 11 " A ", substrate 1110 can comprise texturizing surfaces, and it is constructed to reflect the light collection efficiency that strengthens solar cell by reducing the incident light of collecting the surface away from the glazing of substrate 1110.P-N rectifying junction with uneven profile is arranged between the boundary layer 1113 of base 1111 and second conductivity type (for example N type).(it can have therein from about 1 * 10 in boundary layer 1113
19Cm
-3To about 1 * 10
21Cm
-3Clean N type doping content in the scope) can be formed in the base 1111 by making second type conductivity dopant (for example phosphorus (P)) diffusion from highly doped relatively semiconductor layer 1114 (for example N+ amorphous silicon layer).The thickness in boundary layer 1113 can be chosen as by reducing near do not expect the P-N knot electronics-hole-recombination and increase solar battery efficiency.
Although do not wish to be subjected to any theory constraint, thick inadequately boundary layer 1113 can be relevant with the electronics-hole-recombination of relative elevation degree, and this electronics-hole-recombination is caused by the boundary defect at the heterojunction place between the semiconductor layer 1114 of the boundary layer 1113 and second conductivity type.Alternatively, blocked up boundary layer 1113 can be by high relatively electronics-hole-recombination restriction, and this electronics-hole-recombination is caused by the excessive charge carrier drift (migration just) of process around the wide depletion region of P-N knot.Based on these considerations, have from about 500
To about 2000
The boundary layer 1113 of the thickness in the scope can be supported the light collection efficiency of high level by minimizing electronics-hole-recombination wherein.
And, thereby can be captured near the scope that produces the wavelength of electron-hole pair the P-N knot by increasing, the heterojunction between the semiconductor layer 1114 of the boundary layer 1113 and second conductivity type can help supporting higher light collection efficiency with respect to homojunction.Figure 10 A-10B and Figure 11 also show on the semiconductor layer 1114 of second conductivity type and comprise anti-reflecting layer 1141.As explained above, anti-reflecting layer 1141 can have and the proportional thickness of incident light wavelength.For example, increase efficiency of light absorption thereby anti-reflecting layer 1141 can have the thickness of about λ/4, wherein λ is that the light that will be incident on solar cell is collected lip-deep expectation light wavelength.Anti-reflecting layer 1141 (anti-reflecting layer 1141 can form silicon oxide layer, silicon nitride layer or its multilayer) can also provide electricity for solar cell with the passivation and the protection of physics.
Groove 1120 (it comprise two-dimensional array right-angled intersection groove 1121 and 1123 and outer ring-like " edge " groove 1125) be formed in the substrate 1110.Shown in Figure 10 B (the solar cell I-I ' along the line of its presentation graphs 10A cuts open the sectional view of getting), groove 1120 extends semiconductor layer 1114 and the boundary layer 1113 of passing through anti-reflecting layer 1141, second conductivity type fully.Groove 1121 and 1123 can have the width " W " of about 1 μ m or littler (for example 0.3 μ m) to reduce the shadow loss of incident light, " but edge " groove 1125 can enough wide (as shown in the figure, for example " Wa "＞" W ") to support low resistance contact and wire- bonded.Groove 1121 and 1123 should be darker slightly than the P-N rectifying junction between boundary layer 1113 and the base 1111, thereby the contact of enough low resistance can be produced between trench electrode 1131,1131a and the base 1111.
Illustrate best as Figure 10 B, first conductivity type impurity region 1115 can use bottom and the lower wall place of selecting injection and dopant to advance the combination of (drive-in) technology and being arranged on groove 1120.Impurity range 1115 typically has the clean first conductivity type doping content above the first conductivity type doping content in the base 1111 therein.It will be understood by those skilled in the art that impurity range 1115 can play the effect of enhancing from back of the body surface field (BSF) district of the electric current collection of base 1111.
Figure 10 A-10B also is illustrated on the front surface (just light collect surface) of solar cell and comprises first electrode and second electrode. First electrode 1131,1131a are depicted as the bottom of adjacent trenches 1120 and extend, and with impurity range 1115 and/or base 1111 ohmic contact.As shown in the figure, electric insulation layer 1135 (for example silicon dioxide) is arranged on first electrode 1131,1131a is last and in groove 1120, second electrode 1133,1133a are arranged on the electric insulation layer 1135. Second electrode 1133,1133a can form semiconductor layer 1114 ohmic contact with second conductivity type, and can extend on the upper surface of anti-reflecting layer 1141.The width W 2 of second electrode 1133 can be greater than the width " W " of groove 1121,1123.The upper surface of electric insulation layer 1135 is below the interface between the semiconductor layer 1114 of the boundary layer 1113 and second conductivity type, as shown in figure 11.
Shown in Figure 10 A, can be fabricated into electrically contact (for example the passing through wire-bonded) of the first electrode 1131a in the periphery at rim openings 1119 places that are close to semiconductor substrate 1110, and can be fabricated into electrically contacting of the second electrode 1133a (extending to) around peripheral segmental arc.Particularly, arc opening can be formed in the second electrode 1133a and the following electric insulation layer 1135, thereby exposes the first electrode 1131a and the adjacent upper surface in bottom annular " edge " groove 1125.
According to some embodiment of the present invention, first electrode 1131,1131a and second electrode 1133,1133a can be formed by the material of selecting the group of forming from the combination of aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide and these electric conducting materials.For example, in certain embodiments of the present invention, first electrode 1131,1131a and second electrode 1133,1133a can form the compound of Ti/TiN/Al or Ti/TiN/W.Alternatively, first electrode 1131,1131a can form the P type semiconductor electrode, and second electrode 1133,1133a can form the N type semiconductor electrode.
The solar cell of further embodiment is illustrated by Figure 12 A-12C according to the present invention.Particularly, the solar cell embodiment of Figure 12 A-12B is similar to the solar cell embodiment of Figure 10 A-10B, but has revised the position of the anti-reflecting layer 1141 of Figure 10 A-10B with respect to second electrode 1133.Particularly, shown in Figure 12 A-12B, anti-reflecting layer 1141 can form blanket formula layer (blanket layer) with cover second electrode 1133 (with boundary layer 1113) with respect to the peripheral edge of substrate 1110 part in inside.Alternatively, Figure 12 C illustrates embodiments of the invention, and it has the light transmission conductive layer 1137 that is arranged between anti-reflecting layer 1141 and the boundary layer 1113, and light transmission conductive layer 1137 is arranged on the semiconductor layer 1114.In this embodiment, second electrode 1133 is patterned as on the upper surface that directly extends in light transmission conductive layer 1137.In this way, light transmission conductive layer 1137 can be as promoting the evenly conductive formation of expansion of electric current wherein, this electric current flow through (via the semiconductor layer 1114 of second conductivity type, not shown) between second electrode 1133 and the boundary layer 1113.Light transmission conductive layer 1137 can form indium tin oxide (ITO) layer or zinc oxide (ZnO) layer, yet can also use other light transmissive material.The superficial makings of light transmission conductive layer 1137 can also be coarse relatively, thereby improves the light collection efficiency of solar cell.
According to other embodiments of the invention, the solar cell embodiment of Figure 10 A-10C can further be revised, shown in the solar cell embodiment of Figure 13 A-13B.Particularly, the solar cell embodiment of Figure 13 A-13B comprises second electrode 1133 of revising patterning, makes the upper surface of second electrode 1133 and anti-reflecting layer 1141 at grade.This plane surface profile can realize itself and anti-reflecting layer 1141 coplines by planarization second electrode 1133.And the marginal portion of second electrode 1133 is set to annular and extends 1133b.Extend 1133b and defined the circle second marginal zone 1119b that locates in the periphery of semiconductor substrate 1110, the circular second marginal zone 1119b exposes the surface of first electrode beneath 1131b.The circular second marginal zone 1119b has the width less than width " Wa ".The exposed surface that annular is extended 1133b and first electrode beneath 1131b is an outer electrode (wire-bonded for example, not shown) contact point is provided, this outer electrode is fed to load (not shown) or photovoltaic system (seeing, for example Figure 26) with the electric current that the sun produces.
The method of the solar cell of formation additional embodiment according to the present invention is illustrated by Figure 14 A-20A and Figure 14 B-20B, and Figure 14 B-20B illustrates the sectional view that I-I ' along the line cuts open the structure between two parties of Figure 14 A-20A that gets.Particularly, Figure 14 A-14B illustrates on the base 1111 that boundary layer 1113 is formed on first conductivity type (for example P type) and being combined to form on the base 1111 of first conductivity type (for example P type) of semiconductor layer 1114 (for example highly doped amorphous silicon layer, not shown) of the boundary layer 1113 of second conductivity type (for example N type) and second conductivity type in certain embodiments.The semiconductor layer 1114 of the boundary layer 1113 and second conductivity type can be with respect to Figure 10 A-10B and Figure 11 such as above-mentioned formation, thus definition P-N rectifying junction.As shown in figure 11, the first type surface of semiconductor substrate 1110 can have the surface profile of veining.
Referring now to Figure 15 A-15B, anti-reflecting layer 1141 is formed on the boundary layer 1113, thereby increases the light collection efficiency of solar cell.Anti-reflecting layer 1141 (it can be silicon oxide layer, silicon nitride layer or their combination) for example can use, and the treatment process of plasma enhanced chemical vapor deposition (PECVD) forms.Anti-reflecting layer 1141 can also use conventional antireflection coating (ARC) layer to form.Figure 16 A-16B illustrates photoresist layer 1143 and is deposited on the anti-reflecting layer 1141.Photoresist layer 1143 can be by lithographic patterning with definition opening 1143a and 1143b wherein.These openings can define the cross grid of intersection opening (intersecting opening), shown in Figure 16 A.Photoresist layer 1143 can also be patterned with definition ring edge opening 1119.
Referring now to Figure 17 A-17B, use patterning photoresist layer 1143 to select etching step with groove array and ring edge groove 1125 in the definition semiconductor substrate 1110 as etching mask.These grooves are depicted as two-dimensional grid groove 1120 jointly.Particularly, a plurality of first grooves 1121 and a plurality of second groove 1123 (it forms the cross array (two-dimensional grid just) of groove jointly) form and extend through anti-reflecting layer 1141 and boundary layer 1113 fully, and further extend in the base 1111 of first conductivity type.According to some embodiment of the present invention, the degree of depth of groove can be about 2/3rds of the thickness of semiconductor substrate 1110.As above described about Figure 10 B, these grooves 1121 and 1123 can have the Breadth Maximum of about 1 μ m, but the typical case has the narrower width of for example about 0.3 μ m.
Figure 18 A-18B shows the formation with contiguous first conductivity type impurity region 1115 in the bottom of groove 1121,1123 and 1125.These impurity ranges 1115 can form as lower wall and the bottom that injecting mask injects grid groove 1120 with first type conductivity dopant (for example boron) by the photoresist layer 1143 that uses anti-reflecting layer 1141 and/or patterning.According to some embodiment of the present invention, the injection of first type conductivity dopant can be carried out with enough energy and dosage, to produce the impurity range 1115 that has the first higher type conductivity dopant concentration with respect to base 1111 therein.Then this implantation step, blanket formula conductive layer (not shown) can be deposited on the anti-reflecting layer 1141 and in grid groove 1120.This blanket formula conductive layer can be formed by the material of selecting the group of forming from the combination of aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide and these electric conducting materials.Particularly, blanket formula conductive layer can form the compound of Ti/TiN/Al or Ti/TiN/W.This blanket formula layer is patterned first electrode 1131 with the bottom of definition adjacent trenches 1121,1123 and 1125 then.This patterning of blanket formula layer can be used as the anisotropic etching step to carry out, and this etching step plays the effect that selectivity is eat-back part blanket formula layer.During the anisotropic etching step, anti-reflecting layer 1141 can be used as etch stop layer.As shown in the figure, first electrode 1131 can have the upper surface lower than the P-N junction interface between base 1111 and the boundary layer 1113 (in grid groove 1120).
Also with reference to Figure 18 A-18B, blanket formula insulating barrier (not shown) can be deposited on the anti-reflecting layer 1141 and in grid groove 1120.This blanket formula insulating barrier (it can be formed by the inter-level dielectric material from for example silicon dioxide) is eat-back with the insulating barrier 1135 in the definition grid groove 1120 by selectivity then.This etchback step can need not photoetching and carry out.For example, the anisotropic etching step can use anti-reflecting layer 1141 to carry out as etch stop layer.As shown in the figure, after eat-backing, the top surface of insulating barrier 1135 is lower than the top surface in boundary layer 1113.
Referring now to Figure 19 A-19B, another conductive layer (not shown) conformally be deposited on the anti-reflecting layer 1141 as blanket formula layer and insulating barrier 1135 on.As mentioned above, this conductive layer can be formed by the material of selecting the group of forming from the combination of aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide and these electric conducting materials.Photoresist layer (not shown) can be deposited on the conductive layer, is patterned then with definition photoresist mask 1144.During etching step, use photoresist mask 1144 to define second electrode 1133 then.Anti-reflecting layer 1141 can be used as etch stop layer once more.During the technology that forms second electrode 1133, at least a portion marginal zone 1119 can cover with hard mask 1146, so that the second electrode 1133a of the periphery of definition adjacent substrates 1110, shown in Figure 10 A.Shown in Figure 19 B, the part of insulating barrier 1135 in marginal zone 1119 can be exposed by photoresist mask 1144 and hard mask 1146.
Referring now to Figure 20 A-20B, photoresist mask 1144 and hard mask 1146 can be removed, and another photoresist layer (not shown) can be formed.Then, this photoresist layer can be patterned (for example using wet etching) to define another photoresist mask 1145, and it exposes the first marginal zone 1119a.Then, can carry out the expose portion of dry etch step, thereby expose the bottom that extend the periphery of the contiguous semiconductor substrate 1110 of the first electrode 1131a with selective removal insulating barrier 1135.The bottom of these exposures of the first electrode 1131a can be used as the contact point that outside lead (for example wire-bonded) connects.
Other method embodiment of the present invention is illustrated by Figure 21 A-23A and Figure 21 B-23B.Particularly, Figure 21 A-21B is illustrated in and comprises light transmission conductive layer 1137 on the boundary layer 1113.After this, shown in Figure 22 A-23A, Figure 22 B-23B, Figure 12 A and Figure 12 C, anti-reflecting layer 1141 can conformally be deposited on the substrate 1110.Shown in Figure 23 A-23B, the photoresist layer 1147 of patterning is formed on the anti-reflecting layer 1141.Then, the photoresist layer 1147 of patterning eat-backs in selectivity during the step of expose portion of anti-reflecting layer 1141 and light transmission conductive layer 1137 as mask, thereby exposes the first electrode 1131a and peripheral adjacent respective lower substrate 1110.The photoresist layer 1147 of patterning is removed then, shown in Figure 12 C.
According to additional embodiment of the present invention, the solar cell embodiment of Figure 13 A-13B can use by the step shown in Figure 24 A-25A, Figure 24 B-25B and form.For example, the method that forms solar cell can comprise the modify steps of patterning second electrode 1133, thus the upper surface of second electrode 1133 and anti-reflecting layer 1141 coplines.This plane surface profile can be by making 1133 planarizations of second electrode to realize with anti-reflecting layer 1141 coplines, shown in Figure 24 B.
The marginal portion of second electrode 1133 is set to annular and extends 1133b.Extend 1133b (it is illustrated by Figure 13 B) and defined the circular second marginal zone 1119b (it exposes the surface of first electrode beneath 1131b) at the place, periphery of semiconductor substrate 1110.The circular second marginal zone 1119b has than the littler width of the width among Figure 10 " Wa ".The circular second marginal zone 1119b can define by the photoresist layer 1149 that forms patterning on the planarized surface of second electrode 1133 and anti-reflecting layer 1141, shown in Figure 25 A-25B.Thereafter, shown in Figure 13 A-13B, the part of the expose portion of second electrode 1133 and following insulating barrier 1135 is selectively removed, thereby the narrower upper surface of the first electrode 1131b can be exposed.By increasing the total contact area between second electrode 1133,1133b and the boundary layer 1113, the solar cell embodiment of Figure 13 A-13B provides higher efficient (with respect to the solar cell embodiment of Figure 10 A-10B) potentially.
Referring now to Figure 26, above-described solar cell embodiment of the present invention can be used in the power Control Network 4000, the power that power Control Network 4000 receives from solar battery array 3000.As shown, each solar battery array 3000 can be configured to a plurality of solar modules 2000, and each module comprises the array of solar cell 1000.Like this, voltage and/or electric current that lower voltage that is provided by each solar cell 1000 and/or electric current can provide with the solar cell 1000 by other combine, thereby produce big relatively power source.Power Control Network 4000 is depicted as and comprises output device 4100, power storage device 4200, charge/discharge controller 4300 and system controller 4400, system controller 4400 power controlling storage devices 4200, charge/discharge controller 4300, power regulating system (PCS) 4120 and grid connected system 4140.Output device 4100 can comprise power regulating system (PCS) 4120 and grid connected system 4140.PCS 4120 is used for and will be transformed into the converter of alternating current (AC) from the direct current (DC) of solar battery array 3000.Grid connected system 4140 can be connected to external power system 5000.When the output that is produced by solar battery array 3000 surpasses when outputing to the power of external power system 5000, charge/discharge controller 4300 is used for unnecessary energy is transferred to power storage device 4200.Alternatively, when the output that is produced by solar battery array 3000 was not enough to satisfy the demand of external power system 5000, charge/discharge controller 4300 was used for energy is fetched from power storage device 4200.
The above embodiment of the present invention can be manufactured to has different electrode structures and pattern, their incident lights of receiving on the first type surface of solar cell of response and support the efficient collection of electric charge carrier.For example, Figure 27 A is the plane graph of the integrated circuit solar cell 2700 of the additional embodiment according to the present invention, and Figure 27 B is that the I-I ' along the line of the solar cell 2700 of Figure 27 A cuts open the sectional view of getting.As shown in these figures, solar cell 2700 comprises the two-dimensional array in the second conductivity type district 2710 (being depicted as squared region) that is centered on by top surface electrode 2708, and the second conductivity type district 2710 can have N type conductivity.Each second conductivity type district 2710 and substrate zone 2702 (it can have P-type conduction) formation P-N rectifying junction separately.Shown in Figure 27 B, can be fabricated into electrically contacting of P type substrate zone 2702 by groove base electrode 2704 (it is positioned at the place, bottom of netted groove).Netted top surface electrode 2708 is isolated with following groove base electrode 2704 electricity by the groove base electric insulation layer 2706 (for example silicon dioxide) that inserts, the upper surface of groove base electric insulation layer 2706 can with the upper surface copline of substrate zone 2702, top surface electrode 2708 and N type district 2710 are formed on the substrate zone 2702.
Figure 28 A is the plane graph of the integrated circuit solar cell 2800 of the additional embodiment according to the present invention, and Figure 28 B is that the I-I ' along the line of the solar cell 2800 of Figure 28 A cuts open the sectional view of getting.Shown in the plane graph of Figure 28 A, solar cell 2800 is similar to the solar cell 2700 of Figure 27 A, yet groove base electrode 2804 (seeing, for example Figure 28 B) is depicted as the uppermost light that extends up to solar cell 2800 and accepts the surface.Particularly, Figure 28 B illustrates has the P type substrate zone 2802 that a plurality of N types district 2810 forms thereon, and a plurality of N types district 2810 forms the P-N rectifying junction with substrate zone 2802 respectively.Use a plurality of top surface electrodes 2808 to be fabricated into electrically contacting of N type district 2810, be fabricated into electrically contacting of P type substrate zone 2802 by groove base electrode 2804, groove base electrode 2804 is depicted as the strip shaped electric poles of extend past solar cell 2800 abreast.Further illustrate as Figure 28 B, groove base electrode 2804 and top surface electrode 2808 are electrically isolated from one by electric insulation layer 2806, and the light of electric insulation layer 2806 contiguous solar cells 2800 is accepted the surface and extended.Top surface electrode 2808 is also isolated by electric insulation sept 2809 and following substrate zone 2802 electricity, and electric insulation sept 2809 is arranged on below the top surface electrode 2808.
Figure 29 A is the plane graph of the integrated circuit solar cell 2900 of the additional embodiment according to the present invention, and Figure 29 B is that the I-I ' along the line of the solar cell 2900 of Figure 29 A cuts open the sectional view of getting.Shown in Figure 29 A-29B, solar cell 2900 is similar to the solar cell embodiment of Figure 28 A-28B, yet electric insulation layer 2906 moves in the substrate zones 2902 and at the opposite side on the top of groove base electrode 2904.Top surface electrode 2908 is arranged on the upper surface of electric insulation layer 2906, and this can make the N type district 2910 among Figure 29 B bigger than the N type district 2810 among Figure 28 B.Thereby the solar cell embodiment of Figure 29 A-29B can have the light collection efficiency bigger than the solar cell embodiment of Figure 28 A-28B.As shown in the figure, the solar cell embodiment of Figure 29 A-29B can also comprise and conformally be deposited in the N type district 2910 and the printing opacity insulating barrier 2912 in the interval between adjacent electrode 2908, makes the light of the contiguous solar cell 2900 of plane surface profile collect the surface and is provided with.
Figure 30 A is the plane graph of the integrated circuit solar cell 3000 of the additional embodiment according to the present invention, and Figure 30 B is that the I-I ' along the line of the solar cell 3000 of Figure 30 A cuts open the sectional view of getting.Shown in Figure 30 A-30B, groove base electrode 3004 extends to the parallel striped of the optical receiving surface of crossing solar cell 3000.In these groove base electrodes 3004 each is electrically connected to substrate zone 3002, and isolates by each insulation spacer 3006 and N type district 3010 electricity.These N type districts 3010 form the P-N knot respectively with following substrate zone 3002, and electrically contact top surface electrode 3008.Electric insulation sept 3009 also is arranged on below the top surface electrode 3008, thereby these electrodes 3008 and following substrate zone 3002 are isolated.
Figure 31 A is the plane graph of the integrated circuit solar cell 3100 of the additional embodiment according to the present invention, and Figure 31 B is that the I-I ' along the line of the solar cell 3100 of Figure 31 A cuts open the sectional view of getting.Solar cell 3100 is depicted as the substrate zone 3102 that comprises the square N type district 3110 that has two-dimensional array on it, and square N type district 3110 is centered on by netted top surface electrode 3108.As shown in the figure, top surface electrode 3108 is separated and is isolated by electric insulation sept 3109 and substrate zone 3102.Shown in Figure 31 B, the bottom of strip-shaped grooves base electrode 3104 contiguous each grooves is provided with.These groove base electrodes 3104 are electrically connected to substrate zone 3102.Electric insulation sept 3106 also is arranged between groove base electrode 3104 and the N type district 3110.Can use wire-bonded (not shown in Figure 31 A-31B) to be fabricated into the external control of groove base electrode 3104, wire-bonded is connected to the periphery of substrate zone 3102 (for example silicon wafer).
Figure 32 A is the plane graph of the integrated circuit solar cell 3200 of the additional embodiment according to the present invention, and Figure 32 B is that the I-I ' along the line of the solar cell 3200 of Figure 32 A cuts open the sectional view of getting.Solar cell 3200 is depicted as the substrate zone 3202 that comprises the square N type district 3210 that has two-dimensional array thereon, and square N type district 3210 forms the P-N knot with substrate zone 3202 respectively.A plurality of parallel strip groove base electrodes 3208 are arranged in each groove.As shown in the figure, these groove base electrodes 3208 are electrically connected to top N type district 3210, but isolate by electric insulation lining 3209 and substrate zone 3202 electricity that center on, and electric insulation lining 3209 extends along the bottom and the sidewall of groove.As shown in the figure, a plurality of parallel strip trench electrode 3204 (it is conductively coupled to substrate zone 3202) also are arranged in the respective groove.These electrodes 3204 (optical receiving surface of its contiguous solar cell 3200 extends) are isolated by the electric insulation sept 3206 (for example oxide spacer) and the array electricity in N type district 3210.
Figure 33 is the plane graph of integrated circuit solar cell 3300 according to another embodiment of the present invention, and it is similar to the embodiment 3100 of Figure 31 A-31B.Solar cell 3300 is depicted as the square N type district 3310 of the two-dimensional array that comprises thereon, and square N type district 3310 is centered on by netted top surface electrode 3308.The parallel strip groove base electrode 3304 also bottom of contiguous each groove (not shown in Figure 33) is provided with.But opposite with the solar cell 3100 of Figure 31 A-31B, parallel strip groove base electrode 3304 extends at angle with the electrode 3104 with respect to Figure 31 A-31B.
Figure 34 A is the plane graph of the integrated circuit solar cell 3400 of the additional embodiment according to the present invention, Figure 34 B is that the I-I ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting, and Figure 34 C is that the II-II ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting.Like this, shown in Figure 34 B-34C, the groove base electrode 3404 of right-angled intersection grid is embedded in the P type substrate zone 3402.P type substrate zone 3402 forms the P-N rectifying junction with the array in square N type district 3410 respectively.Also be provided with mesh electrode 3408, it is electrically connected to N type district 3410.Mesh electrode 3408 is isolated by electric insulation sept 3409 (for example silicon dioxide spacer thing) and substrate zone 3402 electricity.Figure 35 is the plane graph of the integrated circuit solar cell 3500 of the additional embodiment according to the present invention, and it is similar to the embodiment of Figure 34 A-34C.As shown in the figure, the groove base electrode 3504 of the right-angled intersection grid of inclination is embedded in the P type substrate zone, and P type substrate zone forms the P-N rectifying junction with the array in square N type district 3510 respectively.Also be provided with mesh electrode 3508, it is electrically connected to N type district 3510.
Figure 36 A is the plane graph of the solar cell 3600 of the additional embodiment according to the present invention, and Figure 36 B is that the I-I ' along the line of the solar cell 3600 of Figure 36 A cuts open the sectional view of getting.Shown in Figure 36 A-36B, the strip shaped electric poles 3608 of a plurality of relative thin be arranged on the optical receiving surface of solar cell 3600 and with a plurality of strip N types district 3610 (alongside) side by side, a plurality of strip N types district 3610 forms the P-N knot respectively with following substrate zone 3602 (for example P type).These electrodes 3608 are isolated by electric insulation sept 3609 (for example oxide spacer) and following substrate zone 3602 electricity.Figure 36 A-36B also illustrates the groove base electrode 3604 that is parallel to N type district 3610 and strip shaped electric poles 3608 extensions.These electrodes 3604 (it is electrically connected to substrate zone 3602) are isolated by electric insulation sept 3606 and contiguous N type district 3610 electricity.
Figure 37 A is the plane graph of the solar cell 3700 of the additional embodiment according to the present invention, and Figure 37 B is that the I-I ' along the line of the solar cell 3700 of Figure 37 A cuts open the sectional view of getting.Shown in Figure 37 A-37B, the strip shaped electric poles 3708 of a plurality of relative thin is arranged on the optical receiving surface of solar cell 3700, each electrode 3708 is clipped between a pair of strip N type district 3710, and strip N type district 3710 forms the P-N knot with following substrate zone 3702 (for example P type) respectively.These electrodes 3708 are isolated by electric insulation sept 3709 (for example oxide spacer) and following substrate zone 3702 electricity.Figure 37 A-37B also illustrates the groove base electrode 3704 that is parallel to N type district 3710 and strip shaped electric poles 3708 extensions.These electrodes 3704 (it is electrically connected to substrate zone 3702) are isolated by electric insulation sept 3706 and contiguous N type district 3710 electricity.
In drawing and description, typical preferred embodiment of the present invention is disclosed, although specific term is used, they only use with general and descriptive meaning rather than in order to limit, scope of the present invention is set forth by additional claims.
The present invention requires in the U.S. Provisional Application No.61/054 of submission on May 19th, 2008,233, the U.S. Provisional Application No.61/058 that submits on June 3rd, 2008,322, the priority of korean patent application No.2008-44062 that submits on May 13rd, 2008 and the korean patent application No.2008-49772 that submits on May 28th, 2008, and these openly are incorporated in this in the reference mode.
Claims (19)
1. solar cell comprises:
Substrate, have at the light on the described substrate and collect surface and the P-N rectifying junction in described substrate, described P-N rectifying junction is included in the base of first conductivity type in the described substrate and the semiconductor layer of second conductivity type that extends between described base and described light collection surface;
Groove extends through the described semiconductor layer of second conductivity type and enters the described base of first conductivity type;
First electrode, the bottom electrical of contiguous described groove is couple to the described base of first conductivity type;
Light transmission conductive layer is on the described semiconductor layer of second conductivity type; And
Second electrode is conductively coupled to the described semiconductor layer and the described light transmission conductive layer of second conductivity type.
2. solar cell as claimed in claim 1, wherein said light transmission conductive layer comprise the material of selecting from the group of being made of zinc oxide and indium tin oxide and combination thereof.
3. solar cell as claimed in claim 1, wherein said second electrode extend in the described groove and contact the sidewall of described semiconductor layer of second conductivity type and the sidewall of described light transmission conductive layer.
4. solar cell as claimed in claim 1 also is included in the anti-reflecting layer on the described light transmission conductive layer.
5. solar cell as claimed in claim 4, wherein said anti-reflecting layer cover described second electrode.
6. solar cell comprises:
Substrate, have at the light on the described substrate and collect surface and the P-N rectifying junction in described substrate, described P-N rectifying junction is included in the base of first conductivity type in the described substrate and the semiconductor layer of second conductivity type that extends between described base and described light collection surface;
Groove extends through the described semiconductor layer of second conductivity type and enters the described base of first conductivity type;
First electrode, the bottom electrical of contiguous described groove is couple to the described base of first conductivity type;
Anti-reflecting layer is collected on the surface at described light; And
Second electrode is conductively coupled to the described semiconductor layer of second conductivity type, and described second electrode has the upper surface with the coplanar planarization of upper surface of described anti-reflecting layer.
7. method that forms solar cell comprises:
The surface texturizing that makes silicon wafer has the base of first conductivity type to produce the Feng Hegu of localization in described surface in described silicon wafer;
The in-situ doped amorphous silicon layer of deposition second conductivity type on the described surface of veining, thus definition has the non-rectification heterojunction of the veining on described surface;
Be transformed into clean second conductivity type thereby be diffused into a part that makes described base the described base from described amorphous silicon layer from clean first conductivity type, in described base, form the boundary layer of second conductivity type by second type conductivity dopant with q.s;
Formation extends through described amorphous silicon layer and described boundary layer and enters groove in the described base;
Formation is conductively coupled to first electrode of described amorphous silicon layer; And
The bottom electrical that forms contiguous described groove is couple to second electrode of described base.
8. method as claimed in claim 7, wherein veining comprises that being exposed to etchant by the surface with described silicon wafer comes the described surface of etching, described etchant causes forming residue to be used as further etched localization etching mask on described surface.
9. method as claimed in claim 8, wherein veining comprises described surface is exposed to the dry ecthing agent that comprises chlorine and fluorine.
10. method as claimed in claim 7, the boundary layer that wherein in described base, forms second conductivity type comprise form have from
Arrive
Scope in the boundary layer of thickness.
11. the temperature that method as claimed in claim 10, the boundary layer that wherein forms second conductivity type in described base are included in 500 ℃ to 900 ℃ the scope is annealed to described amorphous silicon layer.
12. method as claimed in claim 10 wherein deposits in-situ doped amorphous silicon layer and comprises that deposition has from 1 * 10
19Cm
-3To 1 * 10
21Cm
-3The in-situ doped amorphous silicon layer of second conductivity type of the doping content in the scope.
13. method as claimed in claim 10 wherein deposits in-situ doped amorphous silicon layer and comprises the in-situ doped amorphous silicon layer that uses low-pressure chemical vapor deposition deposition techniques second conductivity type.
14. method as claimed in claim 7 wherein forms bottom deposit second electrode that second electrode is included in described groove; And wherein form first electrode and comprise that the top that is close to described groove deposits first electrode.
15. method as claimed in claim 14, wherein the electricity consumption dielectric spacer layer covers described second electrode before forming first electrode, and described electric insulation wall extends between the sidewall of described groove.
16. method as claimed in claim 14 wherein forms groove and comprises the latticed groove of formation, has the groove of a plurality of right-angled intersections of the described silicon wafer of extend past in described latticed groove.
17. method as claimed in claim 14, wherein said latticed groove comprise the outermost annular ditch groove of the periphery of contiguous described silicon wafer; And wherein after forming first electrode, carry out described first electrode of selective removal the part of described annular ditch groove and below described electric insulation wall in the part of described annular ditch groove, thereby expose described second electrode.
18. method as claimed in claim 17 also comprises a plurality of wire-bonded of the expose portion that is formed into described second electrode in the described annular ditch groove.
19. method as claimed in claim 17 wherein was injected into first type conductivity dopant described bottom of described groove before described bottom deposit second electrode of described groove.
Applications Claiming Priority (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080044062A KR20090118333A (en) | 2008-05-13 | 2008-05-13 | Solar cell and forming the same |
| KR44062/08 | 2008-05-13 | ||
| US5423308P | 2008-05-19 | 2008-05-19 | |
| US61/054,233 | 2008-05-19 | ||
| KR49772/08 | 2008-05-28 | ||
| KR1020080049772A KR20090123612A (en) | 2008-05-28 | 2008-05-28 | Solar cell and method of forming the same |
| US5832208P | 2008-06-03 | 2008-06-03 | |
| US61/058,322 | 2008-06-03 | ||
| US12/437,595 | 2009-05-08 | ||
| US12/437,583 US20090283145A1 (en) | 2008-05-13 | 2009-05-08 | Semiconductor Solar Cells Having Front Surface Electrodes |
| US12/437,583 | 2009-05-08 | ||
| US12/437,595 US7964499B2 (en) | 2008-05-13 | 2009-05-08 | Methods of forming semiconductor solar cells having front surface electrodes |
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| CN101621083A true CN101621083A (en) | 2010-01-06 |
| CN101621083B CN101621083B (en) | 2013-06-12 |
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| CN2009101393825A Expired - Fee Related CN101621083B (en) | 2008-05-13 | 2009-05-13 | Semiconductor solar cells having front surface electrodes and method for manufacturing the same |
| CN200910139390XA Expired - Fee Related CN101593780B (en) | 2008-05-13 | 2009-05-13 | Semiconductor solar cells having front surface electrodes and method for manufacturing the same |
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| CN200910139390XA Expired - Fee Related CN101593780B (en) | 2008-05-13 | 2009-05-13 | Semiconductor solar cells having front surface electrodes and method for manufacturing the same |
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| CN (2) | CN101621083B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102231398A (en) * | 2011-06-29 | 2011-11-02 | 中国科学院深圳先进技术研究院 | Copper-indium-gallium-selenium thin film battery with suede and preparation method |
| CN103843150A (en) * | 2011-12-27 | 2014-06-04 | 三洋电机株式会社 | Solar cell and method for manufacturing same |
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| KR20110071379A (en) * | 2009-12-21 | 2011-06-29 | 현대중공업 주식회사 | Method for fabricating back contact type hetero-junction solar cell |
| KR20110071375A (en) * | 2009-12-21 | 2011-06-29 | 현대중공업 주식회사 | Back contact type hetero-junction solar cell and method of fabricating the same |
| KR101410392B1 (en) * | 2009-12-30 | 2014-06-20 | 주성엔지니어링(주) | Hetero juction type Solar Cell and method of manufacturing the same |
| KR101579320B1 (en) * | 2010-05-12 | 2015-12-21 | 엘지전자 주식회사 | Solar cell |
| KR101579321B1 (en) * | 2010-05-17 | 2016-01-04 | 엘지전자 주식회사 | Method for manufacturing solar cell |
| CN102376819A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Forming method of solar battery |
| KR101276889B1 (en) * | 2010-12-09 | 2013-06-19 | 엘지전자 주식회사 | Solar cell |
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| CN102231398A (en) * | 2011-06-29 | 2011-11-02 | 中国科学院深圳先进技术研究院 | Copper-indium-gallium-selenium thin film battery with suede and preparation method |
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| CN103843150A (en) * | 2011-12-27 | 2014-06-04 | 三洋电机株式会社 | Solar cell and method for manufacturing same |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN101593780A (en) | 2009-12-02 |
| KR20090118333A (en) | 2009-11-18 |
| CN101593780B (en) | 2013-06-12 |
| CN101621083B (en) | 2013-06-12 |
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