CN101587688B - Power sequence control circuit, grid driver and liquid crystal display panel applied by power sequence control circuit - Google Patents
Power sequence control circuit, grid driver and liquid crystal display panel applied by power sequence control circuit Download PDFInfo
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- CN101587688B CN101587688B CN2008100971397A CN200810097139A CN101587688B CN 101587688 B CN101587688 B CN 101587688B CN 2008100971397 A CN2008100971397 A CN 2008100971397A CN 200810097139 A CN200810097139 A CN 200810097139A CN 101587688 B CN101587688 B CN 101587688B
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Abstract
The invention relates to a power sequence control circuit for receiving an input positive voltage and an input negative voltage. The circuit comprises a voltage raising unit, a voltage dropping unit and a current limit switch unit, wherein the voltage raising unit comprises a first end coupled to the input positive voltage, a second end coupled to a node and a control end used for receiving a fed back output positive voltage; the voltage dropping unit comprises a first end coupled to the node and a second end connected to an output negative voltage; and the current limit switch unit is provided with a first end used for receiving the input positive voltage, a second end used for outputting the output positive voltage and a control end coupled to the node. When the output negative voltage is dropped, the voltage dropping unit drops a control voltage which corresponds to the node, and when the control voltage is lower than a start critical value, the current limit switch unit is conducted so as to transmit the input positive voltage used as the output positive voltage.
Description
Technical field
The present invention is relevant for the gate drivers of a kind of LCD (LCD) panel, and particularly relevant for a kind of gate drivers with power supply sequent control circuit.
Background technology
General in the drive system of LCD, the order that applies voltage must suitably can not normally show otherwise can cause, even be to cause damage.For instance, be example with grid high voltage (VGH) and the grid low-voltage (VGL) that offers gate drivers, the mistake of both boot sequences just might cause circuit upset operation (for example pinning (latch-up)), and then damages integrated circuit.Wherein, VGH and VGL are operation positive voltage and operation negative voltage, are normally provided by power module, give gate drivers.If the VGH signal that enters gate drivers than VGL signal early to or the signal of VGH and VGL enter gate drivers with the time, just may cause immediate current, again because VGL voltage generally is to be connected in the substrate (substrate), therefore, can be when immediate current flows to substrate with the lifting of VGL voltage, if when this lifting effect makes VGL＞0.5～0.7V, just can form the phenomenon of pinning, or produce big electric current and then cause the damage of integrated circuit.
Its mode of avoiding is to make time that the VGL signal enters into gate drivers early than the VGH signal, to avoid causing the damage of integrated circuit.Generally speaking, can provide grid high voltage (VGHp) and grid low-voltage (VGLp) from power module (Power Block), wherein p represents the voltage signal of being sent by power module.VGHp and VGLp enter into before the gate drivers, must utilize outer member or go to change the order of voltage source by time schedule controller, make the VGLg that enters gate drivers early than VGHg, and wherein the g representative inputs to the operating voltage signal of gate drivers.
Fig. 1 illustrates the basic framework synoptic diagram of traditional liquid crystal device panel.Consult Fig. 1, time schedule controller 100 (Timing Controller, TCON), be mainly the core block in the time sequential routine of control display, cooperate each display frame (frame) display timing generator, the setting horizontal scanning starts, and will be converted to the data-signal that uses to source electrode driver 102 by the vision signal that interface is imported, and for example is the data of RGB generally.Data-signal is sent in the storer of source electrode driver 102, and the hydrous water simple scan, the appropriate time of Controlling Source driver 102.
As before discussing, if the voltage signal VGHp, the VGLp that are sent by power module 110 directly input to gate drivers 104, its input sequence does not guarantee VGLp input earlier.Therefore, can do the control of voltage input sequence by an external circuit 112 traditionally, produce suitable VGHg, VGLg and give gate drivers 104.
The mode that changes the voltage source order traditionally has a variety of.Fig. 2 illustrates the schematic diagram of mechanism that tradition changes the voltage source order.Consult Fig. 2, it is one of general classic method that RC postpones.Normally the VGHp that power module 110 is sent utilizes the mode that RC postpones, and makes it be slower than VGLp and enters into gate drivers 104.VGHp through a time delay T after, can be than the late gate drivers 104 that enters into of VGLp, shown in the top component among Fig. 2.This mode is the simplest mode, but its shortcoming is also arranged.Time delay, T depended on the value of R*C, was not suitable for usually resistor R and capacitor C are integrated in the IC interior, and it has the problem that can utilize area that takies, and also can cause the cost problem.Even utilize outer member to achieve the goal, also be to increase cost.When wanting powered-down,, cause the voltage VGHg that is stored on the electric capacity to discharge rapidly because the value of external capacitor C is not little again.If this moment is power-on once again, also have an opportunity to cause circuit to damage.
In addition, technology has and can control the order that VGH/VGL enters gate drivers by the matching timing controller traditionally.Yet these methods must be utilized outside resistor and capacitor, or outside timing control signal removes to control the VGH/VGL sequencing, can increase complexity and cost.
Summary of the invention
The invention provides a kind of power supply sequent control circuit of gate driving technology, so can effectively reach the order that the control voltage signal enters gate drivers.
The present invention proposes a kind of power supply sequent control circuit, receives an input positive voltage and an input negative voltage, to provide an output positive voltage and an output negative voltage to a gate drivers.Power supply sequent control circuit comprises that a voltage draws high the unit, has one first end and is coupled to this input positive voltage, and one second end is coupled to a node, and a control end receives this output positive voltage of feedback, and wherein to draw high the unit be MOS transistor to this voltage.One voltage drags down the unit to have one first end and is coupled to this node, and one second end is connected to this output negative voltage, and wherein to drag down the unit be MOS transistor to this voltage.One current limiting switch unit has one first termination and receives this input positive voltage, and one second end is exported this output positive voltage, and a control end is coupled to this node, and wherein this current limiting switch unit is MOS transistor or BJT transistor.Wherein when this output negative voltage descends, this voltage drags down the unit the pairing control voltage of this node is drawn and falls, and when this control voltage was lower than a startup critical value, this current limiting switch cell conduction was sent out as this output positive voltage should import positive voltage.
The present invention also proposes a kind of gate drivers, in order to drive a display panels.Gate drivers comprises a gate driver circuit, in order to drive this display panels.One power supply sequent control circuit receives an input positive voltage and an input negative voltage, to provide an output positive voltage and an output negative voltage to this gate driver circuit.Power supply sequent control circuit comprises that a voltage draws high (pull-up) unit, there is one the one the first end to be coupled to this input positive voltage, one second end is coupled to a node, and a control end receives this output positive voltage of feedback, and wherein to draw high the unit be MOS transistor to this voltage.One voltage drags down (pull-down) unit has one first end to be coupled to this node, and one second end is connected to this output negative voltage, and wherein to drag down the unit be MOS transistor to this voltage.One current limiting switch unit has one first termination and receives this input positive voltage, and one second end is exported this output positive voltage, and a control end is coupled to this node, and wherein this current limiting switch unit is MOS transistor or BJT transistor.When this output negative voltage descended, this voltage dragged down the unit and the pairing control voltage of this node is drawn falls, and when this control voltage was lower than a startup critical value, this current limiting switch cell conduction was sent out as this output positive voltage should import positive voltage.
The present invention also proposes a kind of display panels, comprises a pixel display unit, and a plurality of pixels are arranged; The one source pole driver; One gate drivers, the wherein demonstration of this source electrode driver and these those pixels of gate driver drive; One power supply unit provides an operation positive voltage and an operation negative voltage; One power supply sequent control circuit; And time schedule controller.Power supply sequent control circuit receives this operation positive voltage and this operation negative voltage as an input positive voltage and an input negative voltage, and exports this operation positive voltage and this operation negative voltage to this gate drivers is exported negative voltage to export positive voltage and as one.This power supply sequent control circuit comprises that a voltage draws high (pull-up) unit, there is one first end to be coupled to this input positive voltage, one second end is coupled to a node, and a control end receives this output positive voltage of feedback, and wherein to draw high the unit be MOS transistor to this voltage.One voltage drags down (pull-down) unit, has one first end to be coupled to this node, and one second end is coupled to this output negative voltage, and wherein to drag down the unit be MOS transistor to this voltage.One current limiting switch unit has one first termination to receive this input positive voltage, and one second end is exported this output positive voltage, and a control end is coupled to this node, and wherein this current limiting switch unit is MOS transistor or BJT transistor.Wherein when this output negative voltage descends, this voltage drags down the unit and the pairing control voltage of this node is drawn falls, and this control voltage is when being lower than a startup critical value, and this current limiting switch cell conduction was sent out as this output positive voltage should import positive voltage.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example this voltage drag down the unit MOS transistor as a resistor, be connected in this voltage and drag down between this first end of unit and this second end that this voltage drags down the unit.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example voltage is drawn high the unit and is comprised one first path, this first path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example voltage is drawn high the unit and is more comprised at least one the second paths, and this second path is identical and in parallel with this first path.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example voltage drags down the unit and comprises one first path, this first path comprises at least one nmos pass transistor, be connected in series between this first end and this second end, and a grid of this nmos pass transistor is connected in a system low-voltage.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example voltage drags down the unit and more comprises at least one the second paths, and this second path is identical and in parallel with this first path.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example voltage this first path of dragging down the unit comprises that more at least one diode connector connects with this nmos pass transistor.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example the current limiting switch unit comprises one first path, this first path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example the current limiting switch unit comprises at least one the second paths, this second path is identical and in parallel with this first path.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example the current limiting switch unit comprises one first path, this first path comprises at least one BJT transistor, be connected in series between this first end and this second end, and the transistorized base stage of this BJT is connected in this control end.
According to one embodiment of the invention, described power supply sequent control circuit, wherein for example the current limiting switch unit comprises at least one the second paths, this second path is identical and in parallel with this first path.
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the basic framework synoptic diagram of traditional liquid crystal device panel.
Fig. 2 illustrates the schematic diagram of mechanism that tradition changes the voltage source order.
Fig. 3 (a) and 3 (b) illustrate according to one embodiment of the invention power controling machine system synoptic diagram.
Fig. 4 illustrates according to one embodiment of the invention, the synoptic diagram of power supply sequent control circuit.
Fig. 5 illustrates according to one embodiment of the invention, the system architecture synoptic diagram of display panels (LCD Panel).
Fig. 6 illustrates according to one embodiment of the invention, the synoptic diagram of power supply sequent control circuit.
Fig. 7 illustrates according to one embodiment of the invention, the variation synoptic diagram of current signal.
Fig. 8 illustrates according to one embodiment of the invention, the power supply sequent control circuit design diagram.
Fig. 9 (a) illustrates according to the embodiment of the invention to 9 (d), several mode synoptic diagram that diode connects.
[main element symbol description]
100: time schedule controller
102: source electrode driver
104: gate pole driver
106: the picture element display panel
108: sub picture element
110: power zone block
112: external circuit
200,202:PMOS electric crystal
204,208:PMOS electric crystal
206,210:NMOS electric crystal
300: gate pole driver
302: power supply sequent control circuit
400,406: voltage is drawn high the unit
402,408: the current limiting switch unit
404,410: voltage drags down the unit
400a～400c: path
404a～404c: path
402a, 402b: path
Embodiment
The present invention can utilize the critical voltage of MOS transistor to trigger by the making of integrated circuit, to change the order of voltage source.Particularly, the present invention can need not resistor and capacitor in an embodiment, therefore for example circuit directly can be incorporated in the integrated circuit of gate drivers.That is to say that the present invention can not need resistor, capacitor more or control signal, just can reach the order that changes voltage source.
The present invention is for utilizing originally at the current limliting MOS of gate drivers inside resistance, make the input timing that the mode of extending and then utilizing the MOS element to trigger changes VGH and VGL, with the VGH/VGL voltage signal that can guarantee to send from power module, when entering gate drivers inside, can utilize circuit framework of the present invention to make VGH when VGL reaches a certain magnitude of voltage, just enter into gate drivers, avoid causing circuit to damage.
In the present invention, the design of MOS size of component ratio just can determine whether this mechanism can be moved, and can determine the range of application of VGH and VGL voltage simultaneously.Therefore the present invention does not need outer member and signal just to reach, and therefore can be integrated in the integrated circuit of gate drivers yet, does not cause too big influence for chip (chip) area.And, can save the cost that increases outer member to whole liquid crystal display systems.
Below describe the present invention, but the present invention is not subject to illustrated embodiment for some embodiment, and also suitably combination mutually between the implementation column of being lifted.
Fig. 3 illustrates according to one embodiment of the invention, power controling machine system synoptic diagram.Consult Fig. 3 (a), mechanism of the present invention is value as negative voltage signal VGLp during less than a critical value, and the VGHp that is produced by power module just can export to the internal circuit of gate drivers.In addition, because the current-limiting circuit that the present invention utilizes gate drivers originally just must possess is used as power control circuit in addition, therefore, before introducing power control circuit of the present invention, introduce the framework of current-limiting circuit earlier.See also Fig. 3 (b) at this, Fig. 3 (b) is the fundamental mechanism of current-limiting circuit.Present embodiment be with the PMOS transistor as the characteristic of resistance as design basis, on the path between VGHp and the VGHg, be provided with a PMOS transistor 200.In addition, the present invention also can adopt a plurality of identical paths in parallel, shown in Fig. 3 (b), except PMOS transistor 200, also is provided with the PMOS transistor 202 identical with PMOS transistor 200 on the path.VGHp is the positive voltage signal of input, and VGHg is the positive voltage signal that inputs to gate drivers.VGLp is the negative voltage signal of input, and it is identical with the negative voltage signal VGLg that will input to gate drivers, is the grid that is connected PMOS transistor 200.
The metering function of Fig. 3 (b) is as described below: gate drivers generally needs the circuit of current limliting (current-limit), is used for the externally current limliting between the voltage VGHp and builtin voltage VGHg.Because during the LCD system closing, must (voltage level of G1～Gn) be moved VGHg to all output channels of gate drivers, and then open thin film transistor (TFT) (TFT) on all pixels, so that stored electric charge on capacitor C s and liquid crystal capacitance Clc on the pixel is bled off, the phenomenon of avoiding next system boot to have ghost produces, therefore, when system closing, must have current limiting mechanism, avoiding producing instantaneous large-current in the discharge process, and cause circuit to damage; Current limliting MOS resistor the 200, the 202nd is used as the usefulness of aforesaid current limiting mechanism, to avoid the generation of instantaneous large-current, in a preferred embodiment of the present invention, the W/L of MOS resistor 200,202 has enough big value than being designed to, can normal operation to guarantee current limiting mechanism.
Based on the circuit mechanism of this Fig. 3, the present invention proposes power supply sequent control circuit.Fig. 4 illustrates according to one embodiment of the invention, the synoptic diagram of power supply sequent control circuit.Consult Fig. 4,, cooperate whole gate driving, more reach the effect of control power supply order according to the mechanism of Fig. 3.Present embodiment is an example with two identical path parallel connections, yet with regard to basic function, a path can be reached.The PMOS resistor 200,202 that cooperates current limliting, it is as the circuit of Fig. 3, but the grid of PMOS resistor 200,202 is connected to the control end of control voltage VA, VB.In addition, a PMOS transistor 204 is used as resistor and is used, and is connected first end of input voltage VGHp and has between two end points of control end of voltage VA.Similarly, a PMOS transistor 208 is used as resistor and uses, be connected first end of input voltage VGHp and have between two end points of control end of voltage VB.The grid of PMOS transistor 204,208 is connected to output voltage V GHg by the mode of feedbacking.One nmos pass transistor 206 is used as resistor and is used, and is connected the end points of voltage VA and has between the end points of output voltage V GLp, and its grid is connected to a system low-voltage VCC, for example is ground voltage GND.One nmos pass transistor 210 is used as resistor and is used, and is connected the end points of voltage VB and has between the end points of output voltage V GLp, and its grid is connected to a system low-voltage VCC, for example is ground voltage GND.
The operation mechanism of the power supply sequent control circuit of this embodiment is as follows.If VGHp enters in the gate driver circuit simultaneously early than VGLp=VGLg=0V or VGHp and VGLp,,, make VA=VB=VGHp so PMOS transistor 204,208 can conductings because the initial set value of VGHg is 0V.PMOS transistor 200,202 is a closed condition, and this moment, inner VGHg still was 0V.
When VGLp=VGLg=VGL begins when dropping to a certain magnitude of voltage, nmos pass transistor 206,210 conductings this moment, and then voltage VA and VB be pulled to the VGL level make 200,202 conductings of PMOS transistor.This moment, inner positive voltage VGHg just reached the VGHp level, and it is late to enter gate driver circuit than VGLg.When stable state, PMOS transistor the 204, the 206th, closed condition for example can avoid constituting DC path, as VGHp → PMOS transistor 204,206 → nmos pass transistor 206,210 → VGL, causes power consumption.So, no matter can needing only by PMOS transistor 204,206 and nmos pass transistor 206,210, one embodiment of the invention just why can reach the external voltage source sequence, and the order that enters into gate driver circuit inside all be VGLg early than VGHg, the situation of guaranteeing not have pinning (latch-up) takes place.
In design, it for example only must guarantee that the driving force of nmos pass transistor 206,210 is greater than PMOS transistor 204,206 in all voltage ranges of application.The area of these four MOS transistor need not used very greatly again, can not take usable area, also can reduce immediate current.Wherein, because VGHp is the gate drivers internal source voltage, when closing, VGHp can do the action of discharge rapidly, does not have in the known techniques to produce because of the slow excessively problem of external voltage regulation capacitor guiding discharge.
Framework of the present invention can directly be integrated in the gate driver circuit, reduces the element cost, and can not account for too large chip area.The problem of when stable state, also not having the direct-current short circuit electric current.In addition, voltage applied range of the present invention is as long as guarantee that in design the driving force of nmos pass transistor 206,210 is greater than PMOS transistor 204,206.According to breadboard measurement, the voltage scope of application can be VGHp=5V～25V; VGLp=-5V～-20V.In addition, when power-off, VGHp can do the action of discharge rapidly, does not have because of the slow excessively problem generation of external big electric capacity of voltage regulation guiding discharge.Again, other control signals (for example control signal that is additionally provided by time schedule controller 100) are not provided the present embodiment circuit, just can reach the effect that changes the power supply order.
Fig. 5 illustrates according to one embodiment of the invention, the system architecture synoptic diagram of display panels (LCD Panel).Consult Fig. 5, the circuit 302 that will describe as Fig. 4 with gate driving 104 be integrated into gate drivers 300, be applied on the display panels, promote the ability of display panels.
Fig. 6 illustrates according to one embodiment of the invention, the synoptic diagram of power supply sequent control circuit.Circuit according to Fig. 4 is the basis, and the power supply sequent control circuit of one embodiment of the invention receives an input positive voltage VGHp and an input negative voltage VGLP, to provide an output positive voltage VGHg and an output negative voltage VGLg to a gate drivers.Power supply sequent control circuit comprises that a voltage draws high unit 400,406, has one first termination to receive input positive voltage VGHp, output terminal output one control voltage VA, VB, and a control end receives the output positive voltage VGHg of feedback.Control voltage VA, VB and an output terminal that one voltage drags down unit 404,410 has one first termination receipts voltage to draw high unit 400,406 outputs are connected to output negative voltage VGLp=VGLg.One current limiting switch unit 402,408 has one first termination to receive this input positive voltage, output terminal output output positive voltage VGHg, and a control end receives control voltage VA, VB that voltage is drawn high unit 400,406 outputs.When voltage drags down the output negative voltage VGLg of output terminal of unit 406,410 toward this input negative voltage VGLp when decline, the control voltage VA, the VB that also voltage are drawn high unit 400,406 outputs draw and fall, and draw when being reduced to a startup critical value, 402,408 conductings of current limiting switch unit are sent out as output positive voltage VGHg will import positive voltage VGHp.
On operation mechanism, on a paths, mainly can be divided into three aforesaid 400,402,404.When the VGHp rising descended early than VGLp, VA/VB can be drawn high VGHp, and current limiting switch unit 402 is a closed condition at this moment, VGHg=0V.When VGLp=VGLg=VGL dropped to a voltage level, voltage draws high unit 400 and voltage drags down unit 404 unlatchings, and its design is IPL1＞IPH1, IPL2＞IPH2.When stable state, VA/VB can be pulled down to VGLp, and current limiting switch unit 402 is an opening at this moment, VGHg=VGHp.Fig. 7 illustrates according to one embodiment of the invention, the variation synoptic diagram of current signal.Consult Fig. 7, change as can be seen from the electric current of three pieces 400,402,404, VGHg can be later than VGLg and enter gate drivers.
Fig. 8 illustrates according to one embodiment of the invention, the power supply sequent control circuit design diagram.Consult Fig. 8, voltage is drawn high unit 400, and the quantity that voltage drags down unit 404 and current limiting switch unit 402 employed MOS transistor need not to limit, and multiple combination can be arranged.The end points of opening among the figure, expression has multiple choices according to need.
Draw high unit 400 with voltage, can be only only with a PMOS (PH1) or two PMOS (PH1, PH2) being connected in series, even extend to N PMOS (PH1, PH2 ...., PHN-1, PHN).In addition, two path parallel connections of preferred mode such as Fig. 4, however the quantity of path 400a, 400b, 400c also can change according to actual the need.
Drag down unit 404 with voltage, can be only only with a NMOS (PL1) or two NMOS (PL1, PL2) with the series system connection, even extend to N NMOS (PL1, PL2 ...., PLN-1 PLN) connects with series system.In addition, two path parallel connections of preferred mode such as Fig. 4, yet the quantity of path 404a, 404b, 404c also can change according to actual the need.According to different voltage ranges of application, (diode connect, DC), it is for example shown in Figure 9 can to increase the diode connection again.Fig. 9 illustrates according to the embodiment of the invention, several mode synoptic diagram that diode connects.Drag down in the unit 404 in voltage, diode connects square and can be one or many BJT transistors, for example PNP or NPN, and again or the MOS element, for example PMOS or NMOS present with the diode ways of connecting, and the combination that also can be BJT and MOS presents.
With current limiting switch unit 402, it for example can be reached with PMOS (MCL) or with the BJT (QCL) of PNP, for example shown in path 402a, the 402b.
The present invention utilizes power supply sequent control circuit and gate drivers to integrate, and reaches the control of power supply order.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (33)
1. a power supply sequent control circuit receives an input positive voltage and an input negative voltage, to provide an output positive voltage and an output negative voltage to a gate drivers, comprising:
One voltage is drawn high the unit, has one first end and is coupled to this input positive voltage, and one second end is coupled to a node, and a control end receives this output positive voltage of feedback, and wherein to draw high the unit be MOS transistor to this voltage;
One voltage drags down the unit, have one first end and be coupled to this node, and one second end is connected to this output negative voltage, and wherein to drag down the unit be MOS transistor to this voltage; And
One current limiting switch unit has one first termination and receives this input positive voltage, and one second end is exported this output positive voltage, and a control end is coupled to this node, and wherein this current limiting switch unit is MOS transistor or BJT transistor;
Wherein when this output negative voltage descends, this voltage drags down the unit the pairing control voltage of this node is drawn and falls, and when this control voltage was lower than a startup critical value, this current limiting switch cell conduction was sent out as this output positive voltage should import positive voltage.
2. power supply sequent control circuit as claimed in claim 1, wherein this voltage drag down the unit MOS transistor as a resistor, be connected in this voltage and drag down between this first end of unit and this second end that this voltage drags down the unit.
3. power supply sequent control circuit as claimed in claim 1, wherein this voltage is drawn high the unit and is comprised one first path, this first path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
4. power supply sequent control circuit as claimed in claim 3, wherein this voltage is drawn high the unit and is more comprised at least one the second paths, and this second path is identical and in parallel with this first path.
5. power supply sequent control circuit as claimed in claim 1, wherein this voltage drags down the unit and comprises one first path, this first path comprises at least one nmos pass transistor, be connected in series between this first end and this second end, and a grid of this nmos pass transistor is connected in a system low-voltage.
6. power supply sequent control circuit as claimed in claim 5, wherein this voltage drags down the unit and more comprises at least one the second paths, and this second path is identical and in parallel with this first path.
7. power supply sequent control circuit as claimed in claim 5, wherein this voltage this first path of dragging down the unit comprises that more at least one diode connector connects with this nmos pass transistor.
8. power supply sequent control circuit as claimed in claim 1 is arranged in the liquid crystal indicator, and wherein the discharge operation that carried out when closing for this liquid crystal indicator of this current limiting switch unit carries out a current limitation operation.
9. power supply sequent control circuit as claimed in claim 1, wherein this current limiting switch unit comprises one first path, this first path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
10. power supply sequent control circuit as claimed in claim 9, wherein this current limiting switch unit comprises at least one the second paths, this second path is identical and in parallel with this first path.
11. power supply sequent control circuit as claimed in claim 1, wherein this current limiting switch unit comprises one first path, this first path comprises at least one BJT transistor, be connected in series between this first end and this second end, and the transistorized base stage of this BJT is connected in this control end.
12. power supply sequent control circuit as claimed in claim 11, wherein this current limiting switch unit comprises at least one the second paths, and this second path is identical and in parallel with this first path.
13. a gate drivers in order to drive a display panels, comprising:
One gate driver circuit is in order to drive this display panels; And
One power supply sequent control circuit receives an input positive voltage and an input negative voltage, and to provide an output positive voltage and an output negative voltage to this gate driver circuit, this power supply sequent control circuit comprises:
One voltage is drawn high the unit, has one first end to be coupled to this input positive voltage, and one second end is coupled to a node, and a control end receives this output positive voltage of feedback, and wherein to draw high the unit be MOS transistor to this voltage;
One voltage drags down the unit, has one first end to be coupled to this node, and one second end is connected to this output negative voltage, and wherein to drag down the unit be MOS transistor to this voltage; And
One current limiting switch unit has one first termination and receives this input positive voltage, and one second end is exported this output positive voltage, and a control end is coupled to this node, and wherein this current limiting switch unit is MOS transistor or BJT transistor,
Wherein when this output negative voltage descends, this voltage drags down the unit the pairing control voltage of this node is drawn and falls, and when this control voltage was lower than a startup critical value, this current limiting switch cell conduction was sent out as this output positive voltage should import positive voltage.
14. gate drivers as claimed in claim 13, wherein this power supply sequent control circuit and this gate driver circuit are integrated in a grid drive chip.
15. gate drivers as claimed in claim 13, wherein this voltage of this power supply sequent control circuit drag down the unit MOS transistor as a resistor, be connected in this voltage and drag down between this first end of unit and this second end that this voltage drags down the unit.
16. gate drivers as claimed in claim 13, wherein this voltage of this power supply sequent control circuit is drawn high the unit, comprise one first path, this first path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
17. gate drivers as claimed in claim 16, wherein this voltage of this power supply sequent control circuit is drawn high the unit and is more comprised at least one the second paths, and this second path is identical and in parallel with this first path.
18. gate drivers as claimed in claim 13, wherein this voltage of this power supply sequent control circuit drags down the unit and comprises one first path, this first path comprises at least one nmos pass transistor, be connected in series between this first end and this second end, and a grid of this nmos pass transistor is connected in a system low-voltage.
19. gate drivers as claimed in claim 18, wherein this voltage of this power supply sequent control circuit drags down the unit and more comprises at least one the second paths, and this second path is identical and in parallel with this first path.
20. gate drivers as claimed in claim 18, wherein this voltage of this power supply sequent control circuit this first path of dragging down the unit comprises that more at least one diode connector connects with this nmos pass transistor.
21. gate drivers as claimed in claim 13, wherein this current limiting switch unit of this power supply sequent control circuit comprises one first path, this first path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
22. gate drivers as claimed in claim 21, wherein this current limiting switch unit of this power supply sequent control circuit more comprises at least one the second paths, and this second path is identical and in parallel with this first path.
23. gate drivers as claimed in claim 13, wherein this current limiting switch unit of this power supply sequent control circuit comprises one first path, this first path comprises at least one BJT transistor, be connected in series between this first end and this second end, and the transistorized base stage of this BJT is connected in this control end.
24. gate drivers as claimed in claim 23, wherein this current limiting switch unit of this power supply sequent control circuit more comprises at least one the second paths, and this second path is identical and in parallel with this first path.
25. gate drivers as claimed in claim 13, be in order to drive a liquid crystal indicator, wherein this current limiting switch unit of this power supply sequent control circuit carries out a current limitation operation for the discharge operation that this liquid crystal indicator is carried out when closing.
26. a display panels comprises:
One pixel display unit has a plurality of pixels;
The one source pole driver;
One gate drivers, the wherein demonstration of this source electrode driver and these those pixels of gate driver drive;
One power supply unit provides an operation positive voltage and an operation negative voltage;
One power supply sequent control circuit, receive this operation positive voltage and this operation negative voltage as an input positive voltage and an input negative voltage, and export this operation positive voltage and this operation negative voltage to this gate drivers to export negative voltage with one as an output positive voltage, this power supply sequent control circuit comprises:
One voltage is drawn high the unit, has one first end to be coupled to this input positive voltage, and one second end is coupled to a node, and a control end receives this output positive voltage of feedback, and wherein to draw high the unit be MOS transistor to this voltage;
One voltage drags down the unit, has one first end to be coupled to this node, and one second end is coupled to this output negative voltage, and wherein to drag down the unit be MOS transistor to this voltage; And
One current limiting switch unit has one first termination to receive this input positive voltage, and one second end is exported this output positive voltage, and a control end is coupled to this node, and wherein this current limiting switch unit is MOS transistor or BJT transistor, and
Time schedule controller is controlled this source electrode driver, this gate drivers, this power supply unit and this power supply sequent control circuit, with this pixel display unit of indirect driving,
Wherein when this output negative voltage descends, this voltage drags down the unit and the pairing control voltage of this node is drawn falls, and this control voltage is when being lower than a startup critical value, and this current limiting switch cell conduction was sent out as this output positive voltage should import positive voltage.
27. display panels as claimed in claim 26, wherein this power supply sequent control circuit and this gate drivers are other two unit of branch, or a grid drive chip that combines.
28. display panels as claimed in claim 26, wherein this voltage of this power supply sequent control circuit drag down the unit MOS transistor as a resistor, be connected in this voltage and drag down between this first end of unit and this second end that this voltage drags down the unit.
29. display panels as claimed in claim 26, wherein this voltage of this power supply sequent control circuit is drawn high the unit, comprise at least one path, this path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
30. display panels as claimed in claim 26, wherein this voltage of this power supply sequent control circuit drags down the unit and comprises at least one path, this path comprises at least one nmos pass transistor, be connected in series between this first end and this second end, and a grid of this nmos pass transistor is connected in a system low-voltage.
31. display panels as claimed in claim 26, wherein this current limiting switch unit of this power supply sequent control circuit comprises at least one path, this path comprises at least one PMOS transistor, be connected in series between this first end and this second end, and the transistorized grid of this PMOS is connected in this control end.
32. display panels as claimed in claim 26, wherein this current limiting switch unit of this power supply sequent control circuit comprises at least one path, this path comprises at least one BJT transistor, be connected in series between this first end and this second end, and the transistorized base stage of this BJT is connected in this control end.
33. display panels as claimed in claim 26, wherein this current limiting switch unit of this power supply sequent control circuit carries out a current limitation operation for the discharge operation that this display panels is carried out when closing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100971397A CN101587688B (en) | 2008-05-19 | 2008-05-19 | Power sequence control circuit, grid driver and liquid crystal display panel applied by power sequence control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100971397A CN101587688B (en) | 2008-05-19 | 2008-05-19 | Power sequence control circuit, grid driver and liquid crystal display panel applied by power sequence control circuit |
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| CN101587688A CN101587688A (en) | 2009-11-25 |
| CN101587688B true CN101587688B (en) | 2011-11-09 |
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| US9590609B1 (en) * | 2015-11-11 | 2017-03-07 | Delphi Technologies Inc. | Gate driver with short circuit protection |
| CN105448257B (en) * | 2015-12-23 | 2018-05-04 | 南京中电熊猫液晶显示科技有限公司 | A kind of DC/DC power supply changeover devices being connected with liquid crystal display panel |
| TWI637367B (en) * | 2016-09-12 | 2018-10-01 | 瑞鼎科技股份有限公司 | Gate driver |
| JP6811748B2 (en) * | 2017-07-17 | 2021-01-13 | シトロニックス テクノロジー コーポレーション | Touch display drive circuit |
| TWI632539B (en) * | 2017-11-28 | 2018-08-11 | 友達光電股份有限公司 | Scan circuit |
| US11315513B2 (en) * | 2017-12-20 | 2022-04-26 | Sitronix Technology Corp. | Driving circuit for display panel and high voltage tolerant circuit |
| CN108599750A (en) * | 2018-01-23 | 2018-09-28 | 电子科技大学 | A kind of single supply driving circuit of SiC-BJT |
| US11062650B2 (en) * | 2019-09-20 | 2021-07-13 | Novatek Microelectronics Corp. | Sensing circuit and a source driver of a display device |
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