CN101582451A - Thin film transistor - Google Patents

Thin film transistor Download PDF

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Publication number
CN101582451A
CN101582451A CNA2008100672747A CN200810067274A CN101582451A CN 101582451 A CN101582451 A CN 101582451A CN A2008100672747 A CNA2008100672747 A CN A2008100672747A CN 200810067274 A CN200810067274 A CN 200810067274A CN 101582451 A CN101582451 A CN 101582451A
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CN
China
Prior art keywords
thin
film transistor
carbon nano
semiconductor layer
tube
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Pending
Application number
CNA2008100672747A
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Chinese (zh)
Inventor
姜开利
李群庆
范守善
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Tsinghua University
Hongfujin Precision Industry Shenzhen Co Ltd
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Application filed by Tsinghua University, Hongfujin Precision Industry Shenzhen Co Ltd filed Critical Tsinghua University
Priority to CNA2008100672747A priority Critical patent/CN101582451A/en
Priority to US12/384,293 priority patent/US20090283753A1/en
Priority to EP09160164.1A priority patent/EP2120274B1/en
Priority to JP2009117605A priority patent/JP5231325B2/en
Publication of CN101582451A publication Critical patent/CN101582451A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate

Abstract

The invention relates to a thin film transistor, comprising a source electrode, a leakage electrode, a semiconductor layer and a grid electrode. The leakage electrode and the source electrode at intervals; the grid electrode, the semiconductor layer, the source electrode and the leakage electrode are arranged in an insulating way through an insulating layer, wherein the semiconductor layer comprises a plurality of carbon nano tubes, and two ends of at least part of the carbon nano tubes are electrically connected with the source electrode and the leakage electrode respectively.

Description

Thin-film transistor
Technical field
The present invention relates to a kind of thin-film transistor, relate in particular to a kind of thin-film transistor based on carbon nano-tube.
Background technology
(Thin Film Transistor TFT) is a kind of key electronic component in the modern microelectric technique to thin-film transistor, has been widely used in fields such as flat-panel monitor at present.Thin-film transistor mainly comprises grid, insulating barrier, semiconductor layer, source electrode and drain electrode.Wherein, source electrode and drain electrode are provided with at interval and are electrically connected with semiconductor layer, and grid is by insulating barrier and semiconductor layer and source electrode and the setting of drain electrode spacer insulator.The zone of described semiconductor layer between described source electrode and drain electrode forms a channel region.Grid in the thin-film transistor, source electrode, drain electrode constitute by electric conducting material, and this electric conducting material is generally metal or alloy.When on grid, applying a voltage, channel region in the semiconductor layer that is provided with at interval by insulating barrier with grid can accumulate charge carrier, when carrier accumulation to a certain degree, with between the source drain that semiconductor layer is electrically connected with conducting, drain thereby there is electric current to flow to from source electrode.In actual applications, the requirement to thin-film transistor is to wish to obtain bigger switch current ratio.The factor that influences above-mentioned switch current ratio is except that the preparation technology of thin-film transistor, and the carrier mobility of semi-conducting material is for influencing one of most important influencing factor of switch current ratio in the thin-film transistor semiconductor layer.
In the prior art, the material that forms semiconductor layer in the thin-film transistor is (R.E.I.Schropp such as amorphous silicon, polysilicon or semiconducting organic polymer, B.Stannowski, J.K.Rath, New challengesin thin film transistor research, Journal of Non-Crystalline Solids, 299-302,1304-1310 (2002)).Comparatively ripe with amorphous silicon, but in amorphous silicon film transistor as the manufacturing technology of the amorphous silicon film transistor of semiconductor layer, owing to contain a large amount of dangling bonds usually in the semiconductor layer, make that the mobility of charge carrier rate is very low (to be generally less than 1cm 2V -1s -1), thereby cause the response speed of thin-film transistor slower.With polysilicon as the thin-film transistor of semiconductor layer with respect to the thin-film transistor of amorphous silicon as semiconductor layer, have higher carrier mobility and (generally be about 10cm 2V -1s -1), so response speed is also very fast.But polycrystalline SiTFT low temperature manufacturing cost is higher, and method is complicated, and large tracts of land is made difficulty, and the off-state current of polycrystalline SiTFT is bigger.Compared to above-mentioned traditional inorganic thin-film transistors, the OTFT that adopts semiconducting organic polymer to do semiconductor layer have cost low, make the low advantage of temperature, and OTFT has higher pliability.But because organic semiconductor mostly is the great-jump-forward conduction at normal temperatures, show higher resistivity, lower carrier mobility, make that the response speed of OTFT is slower.
Carbon nano-tube has excellent mechanics and electric property.And along with the variation of carbon nano-tube spiral way, carbon nano-tube can present metallicity or semiconductive.The carbon nano-tube of semiconductive has higher carrier mobility (generally can reach 1000～1500cm 2V -1s -1), be to make transistorized ideal material.Existing report adopts the semiconductor layer of the carbon nanotube layer of semiconductive carbon nano tube formation as thin-film transistor in the prior art.In the carbon nanotube layer of the prior art, carbon nano-tube is lack of alignment or arranges perpendicular to substrate, forms a disordered carbon nanotube layer or a carbon nano pipe array.Yet, in above-mentioned disordered carbon nanotube layer, the carbon nano-tube random distribution.The conducting path of charge carrier in above-mentioned disordered carbon nanotube layer is longer, the thin-film transistor that is unfavorable for obtaining to have the higher carrier mobility.In addition, above-mentioned disordered carbon nanotube layer is to form by ink-jet method, mutually combines by binding agent between the carbon nano-tube in the carbon nanotube layer, and therefore, this carbon nanotube layer is a loose structure comparatively, and pliability is relatively poor, is unfavorable for making flexible thin-film transistor.In above-mentioned carbon nano pipe array, the carbon nano-tube orientation is perpendicular to the substrate direction.Because carbon nano-tube has the axial transmission performance of charge carrier preferably, and the transmission performance of radial direction is relatively poor, so the thin-film transistor that is unfavorable for obtaining to have the higher carrier mobility equally perpendicular to substrate direction carbon nanotubes arranged.So the arrangement mode of above-mentioned two kinds of carbon nano-tube all can not effectively utilize the high carrier mobility of carbon nano-tube.Therefore, the thin-film transistor that available technology adopting disordered carbon nanotube layer or carbon nano pipe array are made semiconductor layer is unfavorable for obtaining having the thin-film transistor of higher carrier mobility and higher response speed, and the pliability of thin-film transistor of the prior art is relatively poor.
In sum, necessaryly provide a kind of thin-film transistor, this thin-film transistor has higher carrier mobility, higher response speed, and pliability preferably.
Summary of the invention
A kind of thin-film transistor comprises: one source pole; One drain electrode, this drain electrode and this source electrode are provided with at interval; Semi-conductor layer; And a grid, this grid is by an insulating barrier and this semiconductor layer, source electrode and drain electrode insulation setting; Wherein, this semiconductor layer comprises a plurality of carbon nano-tube, and is electrically connected with described source electrode and drain electrode respectively to the two ends of small part carbon nano-tube.
The thin-film transistor of the semiconductor layer that the carbon nano-tube that a plurality of two ends of the employing that the technical program embodiment provides are electrically connected with described source electrode and drain electrode respectively forms has the following advantages: one, because forming the two ends of the carbon nano-tube of semiconductor layer is electrically connected with described source electrode and drain electrode respectively, so charge carrier has short transmission path by source electrode through semiconductor layer to drain directions transmission, can effectively utilize simultaneously the axial transmission characteristic of carbon nano-tube, thereby help obtaining to have the thin-film transistor of bigger carrier mobility, and then help improving the response speed of thin-film transistor.They are two years old, because carbon nano-tube has excellent mechanical property, then be arranged of preferred orient and two ends have toughness and mechanical strength preferably with the semiconductor layer that described source electrode and the carbon nano-tube that is electrically connected of drain electrode are formed respectively, help making flexible thin-film transistor by a plurality of.
Description of drawings
Fig. 1 is the sectional structure schematic diagram of the thin-film transistor of the technical program first embodiment.
Fig. 2 is the stereoscan photograph of carbon nano-tube film in the thin-film transistor of the technical program first embodiment.
Fig. 3 is the structural representation of the thin-film transistor of the technical program first embodiment when working.
Fig. 4 is the sectional structure schematic diagram of the technical program second embodiment thin-film transistor.
Embodiment
Describe the thin-film transistor that the technical program embodiment provides in detail below with reference to accompanying drawing.
See also Fig. 1, the technical program first embodiment provides a kind of thin-film transistor 10, and this thin-film transistor 10 is a top gate type, and it comprises semi-conductor layer 140, one source pole 151, drain electrode 152, one insulating barrier 130 and a grid 120.Described thin-film transistor 10 is formed on an insulated substrate 110 surfaces.
Above-mentioned semiconductor layer 140 is arranged at above-mentioned insulated substrate 110 surfaces.Above-mentioned source electrode 151 and drain and 152 be arranged at intervals at above-mentioned semiconductor layer 140 surfaces.Above-mentioned insulating barrier 130 is arranged at above-mentioned semiconductor layer 140 surfaces.Above-mentioned grid 120 is arranged at above-mentioned insulating barrier 130 surfaces, and is provided with by this insulating barrier 130 and this semiconductor layer 140 and source electrode 151 and 152 insulation that drain.Described semiconductor layer 140 forms a raceway groove 156 at described source electrode 151 and the zone that drains between 152.
Described source electrode 151 and drain and 152 can be arranged at intervals at the upper surface of described semiconductor layer 140 between described insulating barrier 130 and semiconductor layer 140, at this moment, described source electrode 151, drain electrode 152 and grid 120 are arranged at the same one side of described semiconductor layer 140, form a coplanar type thin-film transistor 10.Perhaps, described source electrode 151 and drain and 152 can be arranged at intervals at the lower surface of described semiconductor layer 140 between described insulated substrate 110 and semiconductor layer 140, at this moment, described source electrode 151, drain electrode 152 and grid 120 are arranged at the not coplanar of described semiconductor layer 140, form a staggered thin-film transistor 10.Be appreciated that above-mentioned source electrode 151 and 152 the position that is provided with of draining is not limited to described semiconductor layer 140 surfaces.As long as guarantee above-mentioned source electrode 151 and drain 152 to be provided with at interval, and electrically contact with above-mentioned semiconductor layer 140 and to get final product.
Described insulated substrate 110 plays a supportive role, and its material may be selected to be hard material or flexible materials such as plastics, resin such as glass, quartz, pottery, diamond, silicon chip.In the present embodiment, the material of described insulated substrate 110 is a glass.Described insulated substrate 110 is used for thin-film transistor 10 is provided support.Described insulated substrate 110 also can be selected the substrate in the large scale integrated circuit for use, and a plurality of thin-film transistor 10 can be formed on the same insulated substrate 110 formation thin-film transistor display panel or other thin-film transistor semiconductor device according to predetermined rule or graphical-set.
Described semiconductor layer 140 comprises a plurality of semiconductive carbon nano tubes, described a plurality of carbon nano-tube is parallel to the surface of described semiconductor layer 140, mutually combine by Van der Waals force between described a plurality of carbon nano-tube, and be electrically connected with described source electrode 151 and drain electrode 152 respectively to the two ends of small part carbon nano-tube.Described semiconductor layer 140 can comprise a carbon nano-tube film, and this carbon nano-tube film comprises a plurality of carbon nano-tube that are parallel to each other.Further, described a plurality of carbon nano-tube has length about equally.Preferably, described carbon nano-tube is all closely arranged along described source electrode 151 to the direction of drain electrode 152.Described carbon nano-tube can be Single Walled Carbon Nanotube or double-walled carbon nano-tube.The diameter of described Single Walled Carbon Nanotube is 0.5 nanometer～50 nanometers, and the diameter of described double-walled carbon nano-tube is 1.0 nanometers～50 nanometers.Preferably, the diameter of described carbon nano-tube is less than 10 nanometers.Described semiconductor layer 140 also can comprise the carbon nano-tube film that two or more are overlapped.Have an intersecting angle α between the carbon nano-tube in the adjacent two layers carbon nano-tube film, α is more than or equal to 0 degree and smaller or equal to 90 degree.The length of described semiconductor layer 140 is 1 micron～100 microns, and width is 1 micron～1 millimeter, and thickness is 0.5 nanometer～100 micron.The length of described raceway groove 156 is 1 micron～100 microns, and width is 1 micron～1 millimeter.
Among the technical program embodiment, described semiconductor layer 140 is a carbon nano-tube film.See also Fig. 2, described carbon nano-tube film comprises a plurality of carbon nano-tube that are parallel to each other.Combine closely by Van der Waals force between described a plurality of carbon nano-tube.Carbon nano-tube in this carbon nano-tube film is closely arranged along described source electrode 151 to drain electrode 152 directions.The length of described semiconductor layer 140 is 50 microns, and width is 300 microns, and thickness is 5 nanometers.The length of described raceway groove 156 is 40 microns, and width is 300 microns.
Described source electrode 151, drain electrode 152 and grid 120 are made up of electric conducting material.Preferably, described source electrode 151, drain electrode 152 and grid 120 are layer of conductive film.The thickness of this conductive film is 0.5 nanometer～100 micron.The material of this conductive film can be metal, alloy, indium tin oxide (ITO), antimony tin oxide (ATO), conductive silver glue, conducting polymer or conductive carbon nanotube etc.This metal or alloy material can be aluminium, copper, tungsten, molybdenum, gold, titanium, neodymium, palladium, caesium or its alloy.In the present embodiment, the material of described source electrode 151, drain electrode 152 and grid 120 is the Metal Palladium film, and thickness is 5 nanometers.Described Metal Palladium and carbon nano-tube have wetting effect preferably, help described source electrode 151 and drain 152 and described semiconductor layer 140 between form good electrical contact, reduce ohmic contact resistance.
Described insulating barrier 130 materials are hard material or flexible materials such as benzocyclobutene (BCB), polyester or acrylic resin such as silicon nitride, silica.The thickness of this insulating barrier 130 is 0.5 nanometer～100 micron.In the present embodiment, the material of described insulating barrier 130 is a silicon nitride.Be appreciated that according to concrete formation technology difference above-mentioned insulating barrier 130 needn't cover above-mentioned source electrode 151, drain electrode 152 and semiconductor layer 140 fully, if can guarantee semiconductor layer 140, source electrode 151 and drain 152 with grid 120 insulation that are oppositely arranged.
See also Fig. 3, during use, described source electrode 151 ground connection, in described drain electrode 152, apply a voltage Vds, on described grid 120, execute a voltage Vg, produce electric field in the raceway groove 156 of grid 120 voltage Vg in semiconductor layer 140, and at the surface generation induction charge carrier of raceway groove 156 near grid 120.Along with the increase of grid 120 voltage Vg, described raceway groove 156 changes the carrier accumulation layer into gradually near the surface of grid 120, when carrier accumulation arrives to a certain degree, will and drain at described source electrode 151 and produce electric current between 152.Because forming the two ends of the part carbon nano-tube of described semiconductor layer 140 is electrically connected with described source electrode 151 and drain electrode 152 respectively, so charge carrier has short transmission path by source electrode 151 through semiconductor layer 140 to drain electrode 152 directions transmission, thereby makes the thin-film transistor 10 of acquisition have bigger carrier mobility and higher response speed.
The technical program embodiment adopts from source electrode 151 to the carbon nano-tube that drain electrode 152 directions are arranged of preferred orient and makes semiconductor layer 140, and the two ends of described carbon nano-tube are respectively with described source electrode 151 and drain and 152 be electrically connected, spacing between the described carbon nano-tube is 20 microns, and the carrier mobility of described thin-film transistor 10 is higher than 10cm 2/ V -1s -1, switch current ratio is 100～1,000,000.Preferably, the carrier mobility of described thin-film transistor is 10～1500cm 2/ V -1s -1
See also Fig. 4, the technical program second embodiment provides a kind of thin-film transistor 20, and this thin-film transistor 20 is a bottom gate type, and it comprises a grid 220, an insulating barrier 230, semi-conductor layer 240, one source pole 251 and a drain electrode 252.This thin-film transistor 20 is arranged on the insulated substrate 210.
The structure of the technical program second embodiment thin-film transistor 20 and the structure of the thin-film transistor 10 among first embodiment are basic identical, and its difference is: above-mentioned grid 220 is arranged at described insulated substrate 210 surfaces; Above-mentioned insulating barrier 230 is arranged at this grid 220 surfaces; Above-mentioned semiconductor layer 240 is arranged at this insulating barrier 230 surfaces, is provided with by insulating barrier 230 and grid 220 insulation; The above-mentioned source electrode 251 and 252 intervals that drain are provided with and electrically contact with above-mentioned semiconductor layer 240, and this source electrode 251, drain electrode 252 and semiconductor layer 240 are by insulating barrier 230 and above-mentioned grid 220 electric insulations.
The described source electrode 251 and 252 upper surfaces that can be arranged at intervals at this semiconductor layer 240 that drain, at this moment, described source electrode 251, drain electrode 252 and grid 220 are arranged at the not coplanar of described semiconductor layer 240, form a reverse-staggered thin-film transistor 20.Perhaps, the described source electrode 251 and 252 lower surfaces that can be arranged at intervals at this semiconductor layer 240 that drain, between described insulating barrier 230 and semiconductor layer 240, at this moment, described source electrode 251, drain electrode 252 and grid 220 are arranged at the same one side of described semiconductor layer 240, form a contrary coplanar type thin-film transistor 20.
The carbon nano-tube that the employing part two ends that the technical program embodiment provides are electrically connected with described source electrode and drain electrode respectively has the following advantages as the thin-film transistor of semiconductor layer: one, because forming the two ends to the small part carbon nano-tube of semiconductor layer is electrically connected with described source electrode and drain electrode respectively, so charge carrier has short transmission path by source electrode through semiconductor layer to drain directions transmission, thereby help obtaining to have the thin-film transistor of bigger carrier mobility, and then help improving the response speed of thin-film transistor.Its two because carbon nano-tube has excellent mechanical property, then have toughness and mechanical strength preferably, thereby help preparing flexible thin-film transistor by the two-layer or two-layer semiconductor layer of forming with upper edge different directions carbon nanotubes arranged film.Its three because carbon nano-tube at high temperature can not be affected, so the semiconductor layer of being made up of this carbon nano-tube at high temperature still has higher carrier mobility.So this thin-film transistor can be applicable to the high temperature field.Its four because carbon nano-tube has higher conductive coefficient, the heat that is produced in the time of can effectively thin-film transistor being worked is derived, and is integrated in heat dissipation problem in the large scale integrated circuit thereby help solving thin-film transistor.
In addition, those skilled in the art also can do other and change in spirit of the present invention, and these variations of doing according to spirit of the present invention certainly all should be included in the present invention's scope required for protection.

Claims (18)

1. thin-film transistor comprises:
One source pole;
One drain electrode, this drain electrode and this source electrode are provided with at interval;
Semi-conductor layer; And
One grid, this grid is provided with by an insulating barrier and this semiconductor layer, source electrode and drain electrode insulation;
It is characterized in that this semiconductor layer comprises a plurality of carbon nano-tube, and be electrically connected with described source electrode and drain electrode respectively to the two ends of small part carbon nano-tube.
2. thin-film transistor as claimed in claim 1 is characterized in that, described carbon nano-tube is a semiconductive carbon nano tube.
3. thin-film transistor as claimed in claim 1 is characterized in that described a plurality of carbon nano-tube are parallel to the surface of described semiconductor layer.
4. thin-film transistor as claimed in claim 1 is characterized in that, described a plurality of carbon nano-tube are parallel to each other.
5. thin-film transistor as claimed in claim 1 is characterized in that, described carbon nano-tube is arranged of preferred orient along the direction of described source electrode to drain electrode.
6. thin-film transistor as claimed in claim 1 is characterized in that, described semiconductor layer comprises one deck carbon nano-tube film at least, and this carbon nano-tube film comprises a plurality of carbon nano-tube that are parallel to each other.
7. thin-film transistor as claimed in claim 6, it is characterized in that, described semiconductor layer comprises two-layer at least overlapped carbon nano-tube film, combine closely by Van der Waals force between the adjacent two layers carbon nano-tube film, and have an intersecting angle α between the carbon nano-tube in the adjacent two layers carbon nano-tube film, α is more than or equal to 0 degree and smaller or equal to 90 degree.
8. thin-film transistor as claimed in claim 1 is characterized in that, described carbon nano-tube is Single Walled Carbon Nanotube or double-walled carbon nano-tube, and the diameter of described carbon nano-tube is less than 10 nanometers.
9. thin-film transistor as claimed in claim 1 is characterized in that described insulating barrier is arranged between described grid and the semiconductor layer.
10. thin-film transistor as claimed in claim 1 is characterized in that, the material of described insulating barrier is silicon nitride, silica, benzocyclobutene, polyester or acrylic resin.
11. thin-film transistor as claimed in claim 1 is characterized in that, described source electrode and drain electrode are arranged at described semiconductor layer surface.
12. thin-film transistor as claimed in claim 1 is characterized in that, the material of described grid, source electrode and drain electrode is metal, alloy, indium tin oxide, antimony tin oxide, conductive silver glue, conducting polymer or conductive carbon nanotube.
13. thin-film transistor as claimed in claim 12 is characterized in that, the material of described grid, source electrode and drain electrode is palladium, caesium, aluminium, copper, tungsten, molybdenum, gold, titanium, neodymium or its alloy.
14. thin-film transistor as claimed in claim 1, it is characterized in that, described thin-film transistor is arranged on the insulated substrate, wherein, described semiconductor layer is arranged at this insulated substrate surface, and described source electrode and drain electrode are arranged at intervals at described semiconductor layer surface, and described insulating barrier is arranged at described semiconductor layer surface, described grid is arranged at described surface of insulating layer, and by this insulating barrier and this semiconductor layer, source electrode and drain electrode electric insulation.
15. thin-film transistor as claimed in claim 1, it is characterized in that, described thin-film transistor is arranged on the insulated substrate, wherein, described grid is arranged at this insulated substrate surface, and described insulating barrier is arranged at described gate surface, and described semiconductor layer is arranged at described surface of insulating layer, and by described insulating barrier and grid electric insulation, described source electrode and drain electrode are arranged at intervals at described semiconductor layer surface and by insulating barrier and above-mentioned grid electric insulation.
16., it is characterized in that the material of described insulated substrate is glass, quartz, pottery, diamond, plastics or resin as claim 14 or 15 described thin-film transistors.
17. thin-film transistor as claimed in claim 1 is characterized in that, the carrier mobility of described thin-film transistor is 10～1500cm 2/ V -1s -1, switch current ratio is 100～1,000,000.
18. thin-film transistor as claimed in claim 1, it is characterized in that, described thin-film transistor further comprises a raceway groove, this raceway groove is the zone of described semiconductor layer between described source electrode and drain electrode, the length of this raceway groove and described semiconductor layer is 1 micron～100 microns, width is 1 micron～1 millimeter, and thickness is 0.5 nanometer～100 micron.
CNA2008100672747A 2008-05-14 2008-05-16 Thin film transistor Pending CN101582451A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CNA2008100672747A CN101582451A (en) 2008-05-16 2008-05-16 Thin film transistor
US12/384,293 US20090283753A1 (en) 2008-05-16 2009-04-02 Thin film transistor
EP09160164.1A EP2120274B1 (en) 2008-05-14 2009-05-13 Carbon Nanotube Thin Film Transistor
JP2009117605A JP5231325B2 (en) 2008-05-16 2009-05-14 Thin film transistor

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CNA2008100672747A CN101582451A (en) 2008-05-16 2008-05-16 Thin film transistor

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JP (1) JP5231325B2 (en)
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