CN101572551A - Time-to-digit converter and method thereof - Google Patents
Time-to-digit converter and method thereof Download PDFInfo
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Abstract
The invention relates to a time-to-digit converter and a method thereof. The time-to-digit converter acquires instantaneous values of signals to be detected to form discrete signals through at least four triggers at respective corresponding reference clocks, delays corresponding effective edges of corresponding reference clocks of various triggers, calculates the effective level time of the signals to be detected by acquiring the distance between two corresponding discrete signals of the signals to be detected when the signals to be detected are overturned from the effective edges, and outputs the signals in a form of digital signals. The time-to-digit converter saves the number of hardware and reduces the area of chips as well.
Description
Technical field
The present invention relates to a kind of time-to-digit converter and method.
Background technology
Time-to-digit converter (TDC, Time-to-digital Converter) is a kind of timer that is converted to digital signal the time interval.The most basic time-to-digit converter is a method of utilizing the oscillator counting, promptly a counter is in time range to be measured, pulse is counted to string number, and the number by the digit pulse that will obtain in time inside counting to be measured is as the digital signal output of expression time to be measured.Although existing oscillator counting can be realized stable high-speed pulse, thing followed power consumption and noise are difficult to accept.
The patent No. a kind of structure of time-to-digit converter 500 that has been 7205924 U.S. Patent Publication.With reference to shown in Figure 1, comprise the delay chain that the differential signal that is used for the inverter 518 of the phase place negate of measured signal HCLK, is used to adjust the phase difference of the complementary input signal HCLK that received and HCLK produces circuit 502, produces redundancy unit 504 that circuit 502 links to each other with differential signal and link to each other with redundancy unit 504 and be made up of 48 delay cells 506.Described differential signal produces circuit 502 and is made of 4 NAND gate 508, and is both-end output.Described redundancy unit 504 comprises two inverters 510, and described inverter links to each other with the both-end output of differential signal generation circuit 502 respectively.Described delay cell 506 comprises two identical inverters 512 and inverter 516 and trigger 514, described inverter 512 and inverter 516 link to each other with the output of two inverters of redundancy unit 504 respectively, described trigger 514 is the both-end input, the trigger of single-ended output, the input of the both-end of described trigger 514 also link to each other with the output of two inverters of redundancy unit respectively.
The operation principle that described time-to-digit converter is measured the time of measured signal HCLK and exported digital signal is described as follows: differential signal produces that circuit 502 receives measured signal HCLK and through the anti-phase measured signal HCLK of inverter 518, export one group of phase place opposite complementary signal mutually, to the delay chain of forming by delay cell 506, when reference clock FREF arrives, trigger 514 in each delay cell 506 receives complementary signal and the output through previous delay units delay, thereby delay chain is exported a series of high level and low level, the number of high level is represented the high level width of measured signal individual pulse, and low level number is represented the width at interval between two adjacent high level pulses of measured signal.According to this operation principle, if, just need to adopt to have the delay cell 506 of littler time of delay for the digital signal that makes described time-to-digit converter output reaches higher precision.And when measured signal has long pulse duration, then just need very many delay cell 506, will increase chip area like this, in addition, if each delay cell 506 that will will be wherein all do time of delay very little, and all equate, implement also difficult undoubtedly.。
Summary of the invention
The invention provides a kind of time-to-digit converter and method, solve the bigger problem of prior art time-to-digit converter area.
For addressing the above problem, the invention provides a kind of time-to-digit converter, comprising:
At least four triggers, be used for the corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal, the corresponding effective edge of wherein said each trigger corresponding reference clock is along postponing successively;
At least two commencing signal unit, be used for continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along delay successively, and middle discrete signal is corresponding with described commencing signal unit;
At least two pulse units, be used at the discrete signal in the centre of continuous three discrete signals that obtained double when the same effective value, pairing reference clock state reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
At least two end signal unit, be used for when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along delay successively, and middle discrete signal is corresponding with described end signal unit;
Counting unit is used for the pulse count signal to being obtained;
First coding unit is used for the commencing signal element address that obtains exporting effective commencing signal according to the effective commencing signal that is obtained;
Second coding unit is used for the end signal element address that obtains exporting effective end signal according to the effective end signal that is obtained;
Subtrator is used to calculate the commencing signal element address of the effective commencing signal of described output and exports the distance of the end signal element address of effective end signal.
The present invention also provides a kind of time-to-digit converter, comprising:
At least four triggers, be used for the corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal, the corresponding effective edge of wherein said each trigger corresponding reference clock is along postponing successively;
At least two logical blocks, be used for continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal; Be used at the discrete signal of the trigger of correspondence output double during for same effective value, pairing reference clock state reach effective edge along the time output pulse signal; Be used for when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Counting unit is used for the pulse count signal to being obtained;
First coding unit is used for the commencing signal element address that obtains exporting effective commencing signal according to the effective commencing signal that is obtained;
Second coding unit is used for the end signal element address that obtains exporting effective end signal according to the effective end signal that is obtained;
Subtrator is used to calculate the commencing signal element address of the effective commencing signal of described output and exports the distance of the end signal element address of effective end signal.
Correspondingly, the invention also discloses a kind of time data conversion method, comprise the following steps:
The corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal;
Continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Double when the same effective value at the discrete signal in the centre of continuous three discrete signals that obtained, pairing reference clock state reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
When continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
To described pulse count signal;
Obtain exporting the commencing signal element address of effective commencing signal according to the effective commencing signal that is obtained;
Obtain exporting the end signal element address of effective end signal according to the effective end signal that is obtained;
Calculate the commencing signal element address of the effective commencing signal of described output and export the distance of the end signal element address of effective end signal.
Compared with prior art, above-mentioned disclosed time-to-digit converter and method have the following advantages: above-mentioned disclosed time-to-digit converter and method form discrete signal by at least 4 triggers obtain measured signal under corresponding reference clock separately instantaneous value, the corresponding effective edge of described each trigger corresponding reference clock is along postponing successively, and by obtain when measured signal to effective edge along upset and from effective edge along the significant level time that the distance between two corresponding discrete signals of upset is calculated measured signal, with the form output of digital signal.Since the distance between described two discrete signals just can be calculated in conjunction with the phase delay of described reference clock described apart from time corresponding, i.e. significant level time of described measured signal.Therefore, the significant level time of described measured signal is only relevant with the phase delay of described reference clock, and the digital signal of the representative time of output is also more accurate.And, fix in order to the flip flop number that obtains described measured signal instantaneous value, and need not significant level time of mating measured signal by delay chain as the prior art.Make trigger to reuse, only need less trigger just can obtain bigger time figure conversion range, thereby saved hardware quantity, also reduced chip area.
Description of drawings
Fig. 1 is existing gate time quantizer circuit figure;
Fig. 2 is first kind of execution mode schematic diagram of time-to-digit converter of the present invention;
Fig. 3 is the circuit diagram of the pulse unit of time-to-digit converter shown in Figure 2;
Fig. 4 is the circuit diagram of the commencing signal unit of time-to-digit converter shown in Figure 2;
Fig. 5 is the circuit diagram of the end signal unit of time-to-digit converter shown in Figure 2;
Fig. 6 is first coding unit of time-to-digit converter shown in Figure 2 or the encoder circuit figure of second coding unit;
Fig. 7 is second kind of execution mode schematic diagram of time-to-digit converter of the present invention;
Fig. 8 is the logic unit circuit figure of time-to-digit converter shown in Figure 7;
Fig. 9 is a kind of execution mode flow chart of time data conversion method of the present invention.
Embodiment
Time-to-digit converter disclosed in this invention forms discrete signal by at least 4 triggers obtain measured signal under corresponding reference clock separately instantaneous value, the corresponding effective edge of described each trigger corresponding reference clock is along postponing successively, and by obtain when measured signal to effective edge along upset and from effective edge along the significant level time that the distance between two corresponding discrete signals of upset is calculated measured signal, with the form output of digital signal.
With reference to shown in Figure 2, first kind of execution mode of time-to-digit converter of the present invention comprises:
At least four trigger 1a, 1b, 1c, 1d, be used for the corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that output is obtained forms discrete signal, and the corresponding effective edge of wherein said each trigger corresponding reference clock is along postponing successively;
At least two commencing signal unit 2,2 ', be used for continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along delay successively, and middle discrete signal is corresponding with described commencing signal unit;
At least two pulse units 3,3 ', be used at the discrete signal in the centre of continuous three discrete signals that obtained double when the same effective value, pairing reference clock state reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
At least two end signal unit 4,4 ', be used for when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along delay successively, and middle discrete signal is corresponding with described end signal unit;
Make that below by a concrete example above-mentioned explanation is clearer.
Described time-to-digit converter is to receive measured signal by trigger under reference clock to form discrete signal.If a plurality of triggers are arranged, and it is all different to control the reference clock phase place of each trigger, and the instantaneous value of the measured signal that so described a plurality of triggers receive under corresponding reference clock separately is just different, thereby the discrete signal of output also is different.Described reference clock usually by free ring shake (FRO, Free-running Ring Oscillator) provide.For example described free ring oscillator provides 32 different reference clocks, the effective edge of a back reference clock has certain phase delay along the corresponding effective edge edge of previous relatively reference clock in described 32 reference clocks, for example second reference clock is than first delayed reference clock 50ps, and the 3rd reference clock is than second delayed reference clock 50ps....
Continue with reference to shown in Figure 2, the quantity of described trigger and the described free ring reference clock number that provides of shaking is corresponding.For example, described free ring shakes provides 32 reference clocks, and then the quantity of described trigger also is 32, and described trigger is the rising edge d type flip flop, described d type flip flop is at the rising edge of corresponding reference clock, and the instantaneous value of the measured signal that output is obtained at this moment forms discrete signal.Below in order to narrate unified and convenience, do following the setting: the quantity of trigger is N, N=1,2,3.....32, the 1st to corresponding successively from left to right first reference clock of N trigger, second reference clock, the 3rd reference clock ... N reference clock.For example, when first reference clock rising edge, measured signal instantaneous value at this moment is low level " 0 ", and then the discrete signal of first trigger output also is " 0 "; And because the rising edge of second reference clock has delay with respect to the rising edge of first reference clock, when the rising edge of second reference clock, the instantaneous value of measured signal may overturn and " 1 " into high level, and then the discrete signal of second trigger output is exactly " 1 ".
The quantity of described pulse unit is identical with the quantity of described trigger, also is 32.Suppose that current pulse unit is a N pulse unit, corresponding N trigger, then described N trigger left side adjacent flip-flops is N-1 trigger, described N temporary the right, unit adjacent flip-flops is N+1 trigger.And described each trigger corresponding reference clock also is respectively N-1 reference clock, a N reference clock and N+1 reference clock.With reference to shown in Figure 3, described pulse unit comprises: be used for the not gate with the discrete signal negate of N-1 trigger output; Be used for carrying out through the discrete signal of the discrete signal of the discrete signal of negate, a N trigger output, a N+1 trigger output with computing hold the T trigger 13 that links to each other with output described and door 12 with door, T, selecting side s links to each other with the output of described T trigger 13, according to the output of T trigger 13 selected cell 15 with the output of the signal on the first input end in1 or the second input in2.Described first input end in1 connects N reference clock, and the second input in2 connects constant Unit 0.Described pulse unit also comprise be used for to the T trigger carry out clearly 0 so that the T trigger become initial condition or door 11, described or door 11 connects the output of N-1 trigger and the output of N trigger, when N-1 and N trigger are output as " 0 ", to described T trigger 13 clear 0.
For example, when the discrete signal of N-1 trigger, a N trigger and N+1 trigger output was 011, the output discrete signal " 0 " of N-1 trigger became " 1 " after not gate 10 negates.The output discrete signal " 1 " of N trigger and the output discrete signal " 1 " of N+1 trigger and through the signal of N-1 trigger after the negate through with door 12 with computing after to the T end output " 1 " of T trigger 13.Described T trigger is a trailing edge T trigger, and by the principle of trailing edge T trigger, when T was 1, at the trailing edge of clock, the T trigger can and be exported the initial condition upset, and T is 0 o'clock, and at the trailing edge of clock, the output of T trigger remains unchanged.The initial condition of described T trigger is traditionally arranged to be " 0 ".Therefore, when with door 12 during to the T of T trigger end output " 1 ", at the trailing edge of N reference clock, T trigger 13 is with the initial condition upset and export " 1 ".And the selecting side s of selected cell 15 selects the signal output of first input end in1 when s is 1, selects the signal output of the second input in2 when s is 0.Because T trigger 13 is output as " 1 ", the selecting side s that connects the selected cell 15 of T trigger 13 outputs also is " 1 ".Therefore, when T trigger 13 exports 1 at N reference clock trailing edge, selected cell 15 is selected N reference clock output on the first input end in1, because at this moment N reference clock also is in low level " 0 ", so the output signal of selected cell 15 temporarily still is " 0 ".And when N reference clock rising edge arrived, selected cell will be exported high level signal " 1 ".When the next trailing edge of N reference clock arrives, if N-1, the output of N trigger still is high level " 1 ", then because the T of T trigger end is " 0 ", the output of T trigger remains unchanged, therefore selected cell 15 is still selected N reference clock output, and then when the rising edge of N reference clock arrived, selected cell 15 continued output high level " 1 ".Up to N-1, N trigger while during output low level, just stop output pulse signal.If N trigger exported n high level continuously like this, then pulse unit 3 can be exported the pulse signal of n high level.
According to above-mentioned description, have only when N-1, N and N+1 trigger are output as 011, T trigger 13 just can be exported high level, and selected cell 15 just has the pulse signal of high level and exports.Thereby this moment except N pulse unit, the output of other pulse unit all is low level.
Described commencing signal unit and described pulse unit are supporting, and quantity also is 32.Suppose that current commencing signal unit is N commencing signal unit, corresponding N trigger, then described N trigger left side adjacent flip-flops is N-1 trigger, described N temporary the right, unit adjacent flip-flops is N+1 trigger.And described each trigger corresponding reference clock also is respectively N-1 reference clock, a N reference clock and N+1 reference clock.With reference to shown in Figure 4, comprise: be used for the not gate 20 of the discrete signal negate of N-1 trigger output, be used for carry out through the discrete signal of the signal of negate, a N trigger output, discrete signal that a N+1 trigger is exported with computing with door 21, T holds the T trigger 22 that links to each other with output described and door 21.For example, when the output signal of described three triggers was 011, the output discrete signal " 0 " of N-1 trigger became " 1 " after not gate 20 negates.The output discrete signal " 1 " of N trigger and the output discrete signal " 1 " of N+1 trigger and through the signal of N-1 trigger after the negate through with door 21 with computing after to the T end output " 1 " of T trigger 22.Described T trigger is a trailing edge T trigger, and by the principle of trailing edge T trigger, when T was 1, at the trailing edge of clock, the T trigger can and be exported the initial condition upset, and T is 0 o'clock, and at the trailing edge of clock, the output of T trigger remains unchanged.The initial condition of described T trigger is traditionally arranged to be " 0 ", the clear 0 clear 0 end CLR control by the clear 0 signal CLR of connection of described T trigger.Therefore, when with door 21 during to the T of T trigger 22 end output " 1 ", at the trailing edge of N reference clock, T trigger 22 is with the initial condition upset and export " 1 ", promptly exports effective commencing signal.
Described end signal unit and described commencing signal unit are supporting, and quantity also is 32.Suppose that current end signal unit is N end signal unit, corresponding N trigger, then described N trigger left side adjacent flip-flops is N-1 trigger, described N temporary the right, unit adjacent flip-flops is N+1 trigger.And described each trigger corresponding reference clock also is respectively N-1 reference clock, a N reference clock and N+1 reference clock.With reference to shown in Figure 5, comprise: be used for the not gate 30 of the discrete signal negate of N-1 trigger output, be used for the NOR gate 31 of carrying out NOR-operation with through the signal of the signal of negate, a N trigger output, signal that a N+1 trigger is exported, T holds the T trigger 32 that links to each other with the output of described NOR gate 31.For example, when the output signal of described three triggers was 100, the output signal of N-1 trigger " 1 " became " 0 " after not gate 30 negates.The output signal " 0 " of output signal of N trigger " 0 " and N+1 trigger and through the T end output " 1 " after the NOR-operation of NOR gate 31 of the signal of N-1 trigger after the negate to T trigger 32.Described T trigger is a trailing edge T trigger, and by the principle of trailing edge T trigger, when T was 1, at the trailing edge of clock, the T trigger can and be exported the initial condition upset, and T is 0 o'clock, and at the trailing edge of clock, the output of T trigger remains unchanged.The initial condition of described T trigger is traditionally arranged to be " 0 ", the clear 0 clear 0 end CLR control by the clear 0 signal CLR of connection of described T trigger.Therefore, when NOR gate 31 during to the T of T trigger 32 end output " 1 ", at the trailing edge of N reference clock, T trigger 32 is with the initial condition upset and export " 1 ", promptly exports effective end signal.
When handling for measured signal with the level pulse that grows tall, for same trigger, may on the corresponding reference clock reaches, jump along the time, the instantaneous value of the measured signal that is received is once more for " 1 ", at this time just needing counting unit to write down is which time obtains " 1 ".The function of setting counting unit is output " 1 " when obtaining for the second time the high level pulse signal of pulse unit output, and promptly the count results of counting unit is that the high level pulse number of signals that pulse unit is exported subtracts 1.Described counting unit comprises: that the pulse signal of paired pulses unit output carries out exclusive disjunction or door, the counter that the high level output of described or door is counted and count results subtracted 1 and the subtracter of output.The output of described counter constitutes the high position of the output signal of described time-to-digit converter, and representative should add the product that blanking time between twice output of same trigger " 1 " and same trigger are exported the number of times of " 1 " once more when the result of calculation of high level pulse of the described measured signal of output.For example, counting unit output " 1 ", the number of times of then representing same trigger to export " 1 " once more is 1, then the result of calculation of the high level pulse of described measured signal just should add the blanking time between 1 times twice output of same trigger " 1 ".32 reference clocks that have phase delay successively are provided in this example, the blanking time between twice output of then described same trigger " 1 ", promptly refer to the upward jumping edge of the 1st reference clock and going up the time of jumping between the edge of the 32nd reference clock.
By above analysis as can be known, the signal transient of the satisfied effective commencing signal of output or effective end signal condition all has only a kind of, and therefore described 32 commencing signal unit or end signal unit all have only a meeting output useful signal.Described first coding unit and second coding unit are exactly in order to know which commencing signal unit or end signal unit exported useful signal.Described first coding unit is identical with the structure of second coding unit.
Be example with first coding unit below, which commencing signal unit what described first coding unit obtained by the output signal of 32 commencing signal unit being obtained is encoded to export effective commencing signal is, suppose that be 0～31 by from left to right order to the 1st to the 32nd commencing signal element number, then available 52 system numbers are represented the 1st to the 32nd commencing signal unit, and with the described numbering address of signal element to start with.If, need not extra coding, therefore only need choose 1xxxx, x1xxx, xx1xx, xxx1x, the output signal coding of the commencing signal unit that xxxx1 representative numbering is corresponding because the 1st commencing signal unit output commencing signal is exactly 00000.
Details are as follows to choose the mode of output signal of described commencing signal unit: suppose that 52 system numbers data bit from left to right is the 1st data bit to the 5 data bit, connect the output of the commencing signal unit that is numbered 1xxxx with an encoder, 1xxxx is that the 1st data bit is 152 system numbers, promptly 10000～11111, Dai Biao commencing signal unit is numbered 16～31 respectively; Connect the output of the commencing signal unit that is numbered x1xxx with encoder, x1xxx is that the 2nd data bit is 152 system numbers, promptly 01000～01111,11000～11111, and Dai Biao commencing signal unit is numbered 8～15,24～31 respectively; Connect the output of the commencing signal unit that is numbered xx1xx with an encoder, xx1xx is that the 3rd data bit is 152 system numbers, promptly 00100～00111,01100～01111,10100～10111,11100～11111, Dai Biao commencing signal unit is numbered 4～7,12～15,20～23,28～31 respectively; Connect the output of the commencing signal unit that is numbered xxx1x with an encoder, xxx1x is that the 4th data bit is 152 system numbers, promptly 00010～00011,00110～00111,01010～01011,01110～01111,10010～10011,10110～10111,11010～11011,11110～11111, Dai Biao commencing signal unit is numbered 2～3,6～7,10～11,14～15,18～19,22～23,26～27,30～31 respectively; Connect the output of the commencing signal unit that is numbered xxxx1 with an encoder, xxxx1 is that the 5th data bit is 152 system numbers, promptly 00001,00011,00101,00111,01001,01011,01101,01111,10001,10011,10101,10111,11001,11011,11101,11111, Dai Biao commencing signal unit is numbered 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31 respectively.
Mode by the above-mentioned output signal of choosing the commencing signal unit as can be known, the commencing signal that any one output high level is arranged in described 32 commencing signal unit, connect the commencing signal that the encoder of described commencing signal unit output can both pass through to be obtained and encode, thereby which commencing signal unit what obtain exporting commencing signal is.Wherein, the simplest coded system is exactly that the output signal of 16 commencing signal unit that each encoder is obtained is carried out exclusive disjunction, as long as any one output high level commencing signal is arranged in 16 commencing signal unit that described encoder connects, the output of described encoder is high level just.With 1xxxx, x1xxx, xx1xx, xxx1x, the output sequence arrangement of xxxx1 corresponding codes device becomes 52 system numbers, just can represent to export the numbering of the commencing signal unit of high level commencing signal.
Because 16 exclusive disjunction is directly used or door realizes that delay can be very long, the encoder in this example uses NOR gate and NAND gate to realize the exclusive disjunction of 16 signals.With reference to shown in Figure 6, described encoder comprises the level Four circuit, first order circuit is used to receive the output signal of commencing signal unit, comprise 2 input NOR gate 41～48, the input of described 8 NOR gate links to each other with described 16 commencing signal unit, for example, and NOR gate 41 received signal D1, D2, NOR gate 42 receives output signal D3, D4, by that analogy; Second level circuit comprises 2 input nand gates 410～413, described NAND gate 410～413 is respectively applied for the output of the NOR gate 41～48 that receives the first order, for example, NAND gate 410 receives the output of NOR gate 41 and NOR gate 42, NAND gate 411 receives the output of NOR gate 43 and NOR gate 44, by that analogy; Tertiary circuit comprises 2 input NOR gate 414～415, described NOR gate 414～415 is respectively applied for the output that receives partial NAND gate 410～413, for example, NOR gate 414 receives the output of NAND gate 410 and NAND gate 411, and NOR gate 415 receives the output of NAND gate 412 and NAND gate 413; Fourth stage circuit comprises 2 input nand gates 416, and described NAND gate 416 is used to receive the output of NOR gate 414 and NOR gate 415.
Described encoder is exemplified below: what effective commencing signal was exported in supposition is to be numbered 8 commencing signal unit.Aforesaid, the encoder that links to each other with the output that is numbered 8 commencing signal unit is the encoder that above-mentioned being connected is numbered the commencing signal unit of 1xxxx, continue with reference to shown in Figure 6, suppose that the output signal that is numbered 8 commencing signal unit inputs to the D1 end of the NOR gate 41 of described encoder, then the signal of D1 end is a high level, and other inputs D2～D16 of described encoder is because the output of the commencing signal unit that connects all is low level, then have only NOR gate 41 to be output as 0 in the first order NOR gate, the output of other NOR gate all is 1, have only NAND gate 410 to be output as 1 in the NAND gate of the second level, the output of other NAND gate all is 0, third level NOR gate 414 is output as 0, NOR gate 415 is output as 1, and fourth stage NAND gate 416 is output as 1.And other connections are numbered 1xxxx, xx1xx, xxx1x, the encoder of the commencing signal unit of xxxx1 do not link to each other with the output that is numbered 8 commencing signal unit, therefore the output of described four encoders all is 0, then with 1xxxx, x1xxx, xx1xx, xxx1x, the output sequence arrangement of xxxx1 corresponding codes unit becomes 52 system numbers, is exactly 01000, promptly exports the commencing signal element address (01000=8) of effective commencing signal.
Described subtrator is used for effective commencing signal element address of effective end signal element address of second coding unit output and the output of first coding unit is subtracted each other, and obtains to receive to jump the trigger on edge on the measured signal and receive the distance of jumping the trigger on edge under the measured signal.The output of described subtrator also is 52 system numbers, with the output of the described subtrator low level as the output signal of described time-to-digit converter.
If the time of the high level pulse of described measured signal less than going up of the 1st reference clock jump going up of edge and the 32nd reference clock jump along between time, then the high position of described time-to-digit converter is output as 00000, and low level output is exactly the output of described subtrator.And if the time of the high level pulse of described measured signal greater than going up of the 1st reference clock jump going up of edge and the 32nd reference clock jump along between time, then the high position of described time-to-digit converter is output as the output of described counting unit, and low level output is exactly the output of described subtrator.For example, receiving the distance of jumping the trigger on edge on the measured signal and receiving the trigger on jumping edge under the measured signal is 5, and described counting unit is output as 2, and then the output high position of described time-to-digit converter is 00010, low level is 00101, and complete output is exactly 0001000101.It is exactly 2 * 32+5=69 that described 10 2 system output signals are converted to 10 system numbers, phase delay by the adjacent reference clock of supposing before is 50ps, going up the following time of jumping between the edge of jumping edge and measured signal of so described measured signal, promptly the high level pulse width of measured signal is 69 * 50=3450ps.Therefore, the value of the digital signal of the last output of described time data transducer is exactly the multiple of the phase delay of described adjacent reference clock in fact.
With reference to shown in Figure 7, second kind of execution mode of time-to-digit converter of the present invention comprises: at least four trigger 100a, 100b, 100c, 100d; Logical block 200,200 '; Counting unit 500; First coding unit 600; Second coding unit 700 and subtrator 800, described trigger 100a, 100b, 100c, 100d; Counting unit 500; First coding unit 600; Second coding unit 700 and subtrator 800 respectively with aforesaid trigger 1a, 1b, 1c, 1d; Counting unit 5; First coding unit 6; Second coding unit 7 and subtrator 8 are identical, have just described no longer one by one here.And the function of described logical block 200 is aforesaid pulse unit 3, the function summation of commencing signal unit 2 and end signal unit 4, be described logical block 200 be used for continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal; Be used at the discrete signal of the trigger of correspondence output double during for same effective value, pairing reference clock state reach effective edge along the time output pulse signal; Be used for when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively.Described logical block 200 ' function and described logical block 200 identical.
In conjunction with Fig. 3, Fig. 4, Fig. 5 and shown in Figure 8, described logical block 200,200 ' circuit be exactly with pulse unit in fact, the parts that have identical function in commencing signal unit and the end signal unit are merged into common component, for example with the not gate in the pulse unit 10, not gate 20 in the commencing signal unit and the not gate 30 in the end signal unit merge into shared not gate 10 ', with in the pulse unit with door 12 and commencing signal unit in door 21 merge into shared and door 12 ', miscellaneous part is all identical with parts in the corresponding unit, for example or door 11 ' with pulse unit in or 11 identical, T trigger 13 ' identical with T trigger 13 in the pulse unit, constant 0 unit 14 ' identical with constant 0 unit 14 in the pulse unit, selected cell 15 ' identical with selected cell 15 in the pulse unit, T trigger 16 ' identical with T trigger 22 in the commencing signal unit, NOR gate 17 ' identical with NOR gate 31 in the end signal unit, T trigger 18 ' identical with T trigger 32 in the end signal unit.Describe the description that please refer to paired pulses unit, commencing signal unit and end signal unit in above-mentioned first kind of execution mode about each functions of components wherein, just repeated no more here.
Correspondingly, a kind of execution mode of time figure conversion method of the present invention with reference to shown in Figure 9, comprising:
Step s1, the corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal;
Step s2, continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Step s3, double when the same effective value at the discrete signal in the centre of continuous three discrete signals that obtained, pairing reference clock state reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Step s4, when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Step s5 is to described pulse count signal;
Step s6, the commencing signal element address that obtains exporting effective commencing signal according to the effective commencing signal that is obtained;
Step s7, the end signal element address that obtains exporting effective end signal according to the effective end signal that is obtained;
Step s8 calculates the commencing signal element address of the effective commencing signal of described output and exports the distance of the end signal element address of effective end signal.
Described time data conversion method please refer to above-mentioned explanation for the time data transducer, has just repeated no more here.
In sum, above-mentioned disclosed time-to-digit converter forms discrete signal by at least 4 triggers obtain measured signal under corresponding reference clock separately instantaneous value, the corresponding effective edge of described each trigger corresponding reference clock is along postponing successively, and by obtain when measured signal to effective edge along upset and from effective edge along the significant level time that the distance between two corresponding discrete signals of upset is calculated measured signal, with the form output of digital signal.Since the distance between described two discrete signals just can be calculated in conjunction with the phase delay of described reference clock described apart from time corresponding, i.e. significant level time of described measured signal.Therefore, the significant level time of described measured signal is only relevant with the phase delay of described reference clock, and the digital signal of the representative time of output is also more accurate.And, fix in order to the flip flop number that obtains described measured signal instantaneous value, and need not significant level time of mating measured signal by delay chain as the prior art.Make trigger to reuse, only need less trigger just can obtain bigger time figure conversion range, thereby saved hardware quantity, also reduced chip area.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. a time-to-digit converter is characterized in that, comprising:
At least four triggers, be used for the corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal, the corresponding effective edge of wherein said each trigger corresponding reference clock is along postponing successively;
At least two commencing signal unit, be used for continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along delay successively, and middle discrete signal is corresponding with described commencing signal unit;
At least two pulse units, be used at the discrete signal in the centre of continuous three discrete signals that obtained double when the same effective value, pairing reference clock state reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
At least two end signal unit, be used for when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along delay successively, and middle discrete signal is corresponding with described end signal unit;
Counting unit is used for the pulse count signal to being obtained;
First coding unit is used for the commencing signal element address that obtains exporting effective commencing signal according to the effective commencing signal that is obtained;
Second coding unit is used for the end signal element address that obtains exporting effective end signal according to the effective end signal that is obtained;
Subtrator is used to calculate the commencing signal element address of the effective commencing signal of described output and exports the distance of the end signal element address of effective end signal.
2. time-to-digit converter as claimed in claim 1 is characterized in that, described commencing signal unit, pulse unit and end signal unit corresponding reference clock are identical with the reference clock of pairing trigger.
3. time-to-digit converter as claimed in claim 1 is characterized in that, described trigger is a d type flip flop.
4. time-to-digit converter as claimed in claim 1 is characterized in that, described pulse unit comprises, is used for continuous three discrete signals that will be obtained, the not gate of discrete signal negate of delay minimum of corresponding reference clock; Be used for will through the discrete signal of negate and other two discrete signals carry out with computing with door; T end and the described T trigger that links to each other with the output of door; The selecting side links to each other with the output of described T trigger, according to the output of T trigger with the selected cell of the output of the signal on the first input end or second input as pulse signal.
5. time-to-digit converter as claimed in claim 1 is characterized in that, described commencing signal unit comprises, is used for continuous three discrete signals that will be obtained, the not gate of discrete signal negate of delay minimum of corresponding reference clock; Be used for will through the discrete signal of negate and other two discrete signals carry out with computing with door; The T end links to each other with the output of door with described, the T trigger of output commencing signal.
6. time-to-digit converter as claimed in claim 1 is characterized in that, described end signal unit comprises, is used for continuous three discrete signals that will be obtained, the not gate of discrete signal negate of delay minimum of corresponding reference clock; Being used for will be through discrete signal and other two NOR gate that discrete signal carries out NOR-operation of negate; The T end links to each other the T trigger of end of output signal with the output of described NOR gate.
7. a time-to-digit converter is characterized in that, comprising:
At least four triggers, be used for the corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal, the corresponding effective edge of wherein said each trigger corresponding reference clock is along postponing successively;
At least two logical blocks, be used for continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal; Be used at the discrete signal of the trigger of correspondence output double during for same effective value, pairing reference clock state reach effective edge along the time output pulse signal; Be used for when continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Counting unit is used for the pulse count signal to being obtained;
First coding unit is used for the commencing signal element address that obtains exporting effective commencing signal according to the effective commencing signal that is obtained;
Second coding unit is used for the end signal element address that obtains exporting effective end signal according to the effective end signal that is obtained;
Subtrator is used to calculate the commencing signal element address of the effective commencing signal of described output and exports the distance of the end signal element address of effective end signal.
8. time-to-digit converter as claimed in claim 7 is characterized in that, described logical block corresponding reference clock is identical with the reference clock of pairing trigger.
9. time-to-digit converter as claimed in claim 7 is characterized in that, described trigger is a d type flip flop.
10. time-to-digit converter as claimed in claim 7 is characterized in that, described logical block comprises, is used for continuous three discrete signals that will be obtained, the not gate of discrete signal negate of delay minimum of corresponding reference clock; Be used for will through the discrete signal of negate and other two discrete signals carry out with computing with door; T end and the described T trigger that links to each other with the output of door; The selecting side links to each other with the output of described T trigger, according to the output of T trigger with the selected cell of the output of the signal on the first input end or second input as pulse signal; The T end links to each other with the output of door with described, the T trigger of output commencing signal; Being used for will be through discrete signal and other two NOR gate that discrete signal carries out NOR-operation of negate; The T end links to each other the T trigger of end of output signal with the output of described NOR gate.
11. a time figure conversion method is characterized in that, comprises the following steps:
The corresponding reference clock reach effective edge along the time, the instantaneous value of the measured signal that obtained of output forms discrete signal;
Continuous three discrete signals that obtained represent measured signal to effective edge along when upset, the corresponding reference clock reach effective edge along the time export effective commencing signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
Double when the same effective value at the discrete signal in the centre of continuous three discrete signals that obtained, pairing reference clock state reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
When continuous three discrete signals that obtained are represented measured signal from effective edge along upset, pairing reference clock state reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;
To described pulse count signal;
Obtain exporting the commencing signal element address of effective commencing signal according to the effective commencing signal that is obtained;
Obtain exporting the end signal element address of effective end signal according to the effective end signal that is obtained;
Calculate the commencing signal element address of the effective commencing signal of described output and export the distance of the end signal element address of effective end signal.
12. time figure conversion method as claimed in claim 11 is characterized in that, described output pulse signal comprises: in continuous three discrete signals that obtained, the discrete signal negate of delay minimum of corresponding reference clock; To carry out and computing through discrete signal and other two discrete signals of negate; Export triggering signal according to described with result computing; According to described triggering signal output pulse signal.
13. time figure conversion method as claimed in claim 11 is characterized in that, described output commencing signal comprises: in continuous three discrete signals that obtained, the discrete signal negate of delay minimum of corresponding reference clock; To carry out and computing through discrete signal and other two discrete signals of negate; Export triggering signal according to described with result computing; According to described triggering signal output commencing signal.
14. time figure conversion method as claimed in claim 11 is characterized in that, described end of output signal comprises: in continuous three discrete signals that obtained, the discrete signal negate of delay minimum of corresponding reference clock; To carry out NOR-operation through discrete signal and other two discrete signals of negate; Result according to described NOR-operation exports triggering signal; According to described triggering signal end of output signal.
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| CN102291138A (en) * | 2011-07-08 | 2011-12-21 | 东南大学 | Stochastic time-digital converter |
| CN102109812B (en) * | 2009-12-23 | 2012-07-04 | 中国科学院微电子研究所 | Differential delay chain time-to-digital converter |
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| WO2014173050A1 (en) * | 2013-04-27 | 2014-10-30 | 江西三川水表股份有限公司 | Annular time to digital converter and method thereof |
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| US6670800B2 (en) * | 2002-05-08 | 2003-12-30 | Intel Corporation | Timing variation measurements |
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| CN105763196B (en) * | 2016-03-10 | 2018-11-27 | 中国科学技术大学 | A kind of delay interpolation type time-to-digit converter |
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| CN108988864B (en) * | 2017-05-30 | 2024-03-26 | 英飞凌科技奥地利有限公司 | System and method for oversampling data converter |
| CN113759388A (en) * | 2020-06-02 | 2021-12-07 | 华中科技大学 | Time-of-flight measurement system and method of TDC-shared laser receiver |
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