CN101562140B - Packaging method for improving antistatic capability of integrated circuit chip - Google Patents
Packaging method for improving antistatic capability of integrated circuit chip Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
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- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention discloses a packaging method for improving the antistatic capability of an integrated circuit chip, which comprises the following steps: manufacturing a power line loop and a ground line loop on the packaging tube shell; connecting one or more capacitors and a resistor between the power line loop and the ground line loop; leading one or more places of the integrated circuit chip connected with the power line inside the chip to a power line loop; one or more of the integrated circuit chips are wired to a ground loop where they are connected to the internal ground of the chip. By using the invention, chips with poor ESD protection capability in the integrated circuit can achieve good ESD protection capability after being packaged.
Description
Technical field
The present invention relates to the semiconductor packaging field, relate in particular to a kind of method for packing that improves antistatic capability of integrated circuit chip.
Background technology
Along with the development of semicon industry, particularly enter after the deep-submicron yardstick, the puncture voltage of oxide layer will reduce significantly on the one hand; Some producer adopts the silicon SOI technology on the insulator on the other hand, because silicon fiml is thin in the SOI technology, the passage of bleed off electrostatic discharge protective (ESD) electric current is narrow, heat-sinking capability is also very different relatively, make the non-constant of anti-ESD ability of its efferent duct, even the method that has reached the small resistor of having to connect between the diode of output complementary metal oxide semiconductors (CMOS) (CMOS) and bleed off ESD electric current is improved the anti-ESD ability of efferent duct.
Owing to will in the process of chip manufacturing, design the structure that addresses the above problem, need spend a large amount of areas to design diode (751,752,753,754), VDD/VSS loop wire (102,101) and POWER CLAMP (a kind of being placed between power line and the ground wire, when circuit bears ESD voltage, form the structure of a conductive path from the power line to the ground wire) structure, cost is big and effect is very difficult promotes significantly, even the performance that needs to reduce product just can make product reach an acceptable ESD protective capacities.
In addition, in the compound semiconductor circuit of high frequency, because very strict to the control of I/O PAD parasitic capacitance, it is just difficult more to improve its anti-ESD ability.Thus, in August, 2007, the industrial development commission of ESD aspect has announced a white paper, has proposed the anti-ESD ability of reduction chip internal structure, is transformed into the demand that improves the anti-ESD ability in product encapsulation back, to reduce the manufacturing cost of chip.
Improve the method for the anti-ESD ability of product after encapsulating, technology is chiefly directed on the circuit board method that circuit by adding bleed off ESD electric current or material improve the anti-ESD performance of product before, these are for the relatively poor situation of the anti-ESD ability of foregoing chip internal structure, the problem that ESD damages occurs after then can't solving Chip Packaging in transportation.Also have to be proposed on the encapsulating structure method that adds cascading water pipe (CLAMP) structure, because the keeping voltage and will do operating voltage in product of its structural requirement cascading water pipe that adopts, the effect of cascading water pipe is also had a greatly reduced quality.
Summary of the invention
(1) technical problem that will solve
In view of this, The present invention be directed to the problems referred to above, a kind of method for packing that improves antistatic capability of integrated circuit chip is provided, this method is relatively poor for some self ESD protective capacities, but the good situation of diode (751,752,753,754) positively biased ducting capacity of placing between each pressure welding pad (PAD) of chip internal and the VDD/VSS is very effective; When the ESD electric current arrives; because electric capacity absorbs the effect of ESD electric current; with the voltage limit at electric capacity two ends in level far below circuit voltage; thus; except diode participates in the bleed off electric current; other all metal-oxide-semiconductor structures all are in non-breakdown conditions (close, metal-oxide-semiconductor unlatching/inferior opening), have reached the purpose of protection chip circuit.
(2) technical scheme
For achieving the above object, the invention provides a kind of method for packing that improves antistatic capability of integrated circuit chip, this method comprises:
On the encapsulation shell, make a power line loop 22 and a ground line loop 21;
Between power line loop 22 and ground line loop 21, be connected one or more electric capacity 10 and a resistance 13;
The place that the one or more of integrated circuit (IC) chip 71 are linked to each other with chip internal power line 102 goes between on the power line loop 22;
The place that the one or more of integrated circuit (IC) chip 71 are linked to each other with chip internal ground wire 101 goes between on the ground line loop 21.
Preferably, described power line loop 22 is to be made in encapsulation shell surface or inner ring-type circuit, in some cases with the power line VDD 102 of integrated circuit (IC) chip 71 inside as power line loop 22.
Preferably, described power line loop 22 usefulness aluminium, copper, gold or corresponding alloy are made, and thickness is 10 μ m to 500 μ m, and width is greater than 100 μ m.
Preferably, described some situation is that the voltage that the input/output circuitry of integrated circuit (IC) chip 71, internal circuit are born in the case can damage below the voltage at it in electrostatic discharge protective ESD process, comprises following several situation and combination:
A, described electric capacity 10 adopt big capacitance;
The input/output circuitry of b, integrated circuit (IC) chip 71, internal circuit can bear higher voltage under worst situation;
Adopt diode between c, I/O pressure welding pad PAD and the chip internal power line 102/ chip internal ground wire 101 than large tracts of land or girth;
D, chip internal power line 102 wider width particularly have the situation of multiple layer metal as chip internal power line 102;
E, integrated circuit (IC) chip 71 anti-ESD Capability Requirements are not high.
Preferably, described bigger, higher, broad, not high, be meant above a to e the resultant effect of totally 5 factors can satisfy in the ESD process, the voltage that integrated circuit (IC) chip 71 input/output circuitry, internal circuits are born is benchmark damaging below the voltage at it.
Preferably, described ground line loop 21 is to be made in encapsulation shell surface or inner ring-type circuit, in some cases with the ground wire VSS 101 of integrated circuit (IC) chip 71 inside as ground line loop 21.
Preferably, described ground line loop 21 usefulness aluminium, copper, gold or corresponding alloy are made, and thickness is 10 μ m to 500 μ m, and width is greater than 100 μ m.
Preferably, described some situation is that the voltage that the input/output circuitry of integrated circuit (IC) chip 71, internal circuit are born in the case can damage below the voltage at it in electrostatic discharge protective ESD process, comprises following several situation and combination:
A, described electric capacity 10 adopt big capacitance;
The input/output circuitry of b, integrated circuit (IC) chip 71, internal circuit can bear higher voltage under worst situation;
Adopt diode between c, I/O pressure welding pad PAD and the chip internal power line 102/ chip internal ground wire 101 than large tracts of land or girth;
D, chip internal ground wire 101 wider width particularly have the situation of multiple layer metal as chip internal ground wire 101;
E, integrated circuit (IC) chip 71 anti-ESD Capability Requirements are not high.
Preferably, described bigger, higher, broad, not high, be meant above a to e the resultant effect of totally 5 factors can satisfy in the ESD process, the voltage that integrated circuit (IC) chip 71 input/output circuitry, internal circuits are born is benchmark damaging below the voltage at it.
Preferably, described electric capacity 10 is patch capacitors, is installed in encapsulation shell surface or inner, and capacitance is 0.05 μ F to 50 μ F.
Preferably, described resistance 13 is Chip-Rs, is installed in encapsulation shell surface or inner, resistance value be 10k ohm to 100M ohm, the metal-oxide semiconductor (MOS) metal-oxide-semiconductor with integrated circuit 71 inside uses as resistance 13 in some cases.
Preferably, described some situation is that input/two-way end is in floating, when chip internal power line 102 is in the positive voltage bias state, can utilizes metal-oxide-semiconductor to open or inferiorly open electric charge bleed off that the electric leakage mode stores electric capacity 10 to the situation that satisfies the esd protection demand;
The metal-oxide-semiconductor of described integrated circuit 71 inside comprises the metal-oxide-semiconductor structure 721 in input (711,712), output mos pipe (731,732) and the internal circuit.
Preferably, describedly between power line loop 22 and ground line loop 21, be connected one or more electric capacity 10, be meant between most of situation power line loop 22 and ground line loop 21 and be connected an electric capacity, but under following situation, to obtain good ESD protective capacities, need to connect a plurality of equally distributed electric capacity:
A, when power line loop 22 and ground line loop 21 width are narrower, particularly during as corresponding loop, adopt a plurality of electric capacity with chip internal power line 102/ chip internal ground wire 101, protect the ESD ability with the anti-electrostatic discharging that promotes chip;
B, when needing better voltage source filtering performance, power supply adopts a plurality of electric capacity, to promote chip performance;
C, the ESD voltage ratio that can bear at inner each metal-oxide-semiconductor of integrated circuit (IC) chip 71 are lower, when particularly being used in the ESD protection on the deep-submicron yardstick chip, adopt a plurality of electric capacity, to promote the anti-ESD ability of chip.
Preferably, the described place that the one or more of integrated circuit (IC) chip 71 are linked to each other with chip internal power line 102 goes between on the power line loop 22, be that power supply PAD with integrated circuit (IC) chip 71 is connected on the power supply PAD46 of encapsulating structure by line 44, but can have a strong impact in the dead resistance on the chip internal power line 102 under the situation of the anti-ESD ability of chip, the accessory power supply PAD of chip internal is connected on the power line loop 22 by lead-in wire (32,34,36,38).
Preferably, the described place that the one or more of integrated circuit (IC) chip 71 are linked to each other with chip internal ground wire 101 goes between on the ground line loop 21, be that ground wire PAD with integrated circuit (IC) chip 71 is connected on the ground connection PAD43 of encapsulating structure by line 41, but can have a strong impact in the dead resistance on the chip internal ground wire 101 under the situation of the anti-ESD ability of chip, the auxiliary ground wire PAD of chip internal is connected on the ground line loop 21 by lead-in wire (31,33,35,37).
Preferably, when this method was used AC-battery power source, described electric capacity 10 or resistance 13 further adopted following connected mode: the line loop method of attachment of common-battery source, line loop method of attachment altogether, method of attachment and simplification method of attachment comprehensively.
Preferably, described AC-battery power source is to use the voltage source with different magnitudes of voltage in same integrated circuit (IC) chip 71, or uses the voltage source with identical magnitude of voltage that insulation request is arranged.
Preferably, described electric capacity 10 adopts line loop method of attachment altogether to comprise: with all independently power line (22,24)/ground wire (21,23) be connected one or more electric capacity respectively with a certain common ground, and at the other resistance of placing in parallel of each group electric capacity, this common ground is any in each independent ground wire (21,23).
Preferably, described electric capacity 10 adopts common-battery source line loop methods of attachment to comprise: with all independently power line (22,24)/ground wire (21,23) be connected one or more electric capacity respectively with a certain public power wire, and at the other resistance of placing in parallel of each group electric capacity, this public power wire is any in each independent current source line (22,24).
Preferably, described electric capacity 10 adopts comprehensive method of attachment to comprise: will any independent current source line (22,24) be connected one or more electric capacity respectively with any one independent ground wire (21,23) in the integrated circuit, and at the other parallel connection placement of each group electric capacity one resistance.
Preferably, described electric capacity 10 adopts to be simplified methods of attachment and comprises: with the one or more independent current sources in the integrated circuit with independently between respectively be connected one or more electric capacity, and at other placement one resistance in parallel of each group electric capacity.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilize the present invention, can reduce the voltage drop between VDD and the VSS significantly in the ESD process, it is excessive to integrated circuit (IC) chip 71 anti-ESD Effect on Performance to reduce the voltage drop in the ESD process of CLAMP cascading water tubular construction;
2, utilize the present invention, can reduce integrated circuit (IC) chip internal power cord 102/ chip internal ground wire 101 dead resistance problems integrated circuit (IC) chip 71 anti-ESD Effect on Performance;
3, utilize the present invention, can reduce the voltage drop of integrated circuit between ESD process chips internal power cord 102/ chip internal ground wire 101 significantly;
4, utilize the present invention, when AC-battery power source, adopt many capacitive, can reduce between independent current source line and independent current source line, independent ground wire and the independent ground wire POWER PLAN (a kind ofly be placed between independent current source line and the independent current source line, the structure between independent ground wire and the ground wire, when circuit bears ESD voltage, can between them, form conductive channel) structural voltage drop is to the anti-ESD Effect on Performance of integrated circuit;
5, utilize the present invention, can be in time the negative electrical charge (electric charge that comprises electric capacity 10 accumulation) of accumulation on the positive charge of accumulation on the VDD loop wire 102 or the VSS loop wire 101 be discharged, it is too much to prevent that electric capacity 10 from bearing repeatedly the electric charge that stores behind the ESD voltage, and overtension causes the problem of chip failure.
6, utilize the present invention, all in all, can make the relatively poor chip of some self anti-ESD abilities, the ESD barrier propterty obtains significantly to promote after encapsulation.
7, utilize the present invention, can also improve the power filter performance.
Description of drawings
Fig. 1 is the structural representation of single supply provided by the invention, single capacitor, single resistance packaged type;
Fig. 2 is the position view after Fig. 1 construction packages;
Current path schematic diagram when Fig. 3 applies positive ESD voltage for Fig. 1 structure input to output;
Fig. 4 absorbs the analog circuit schematic diagram of ESD voltage wave for electric capacity;
Fig. 5 is Fig. 4 Simulation result;
Fig. 6 for Fig. 1 structure capacitive storage ESD electric charge after, pass through add the analog result of resistance bleed off electric charge process;
Fig. 7 is one 1.2 μ m technology microcontroller circuits when input/two-way end suspension joint, the electric leakage situation under the different electrical power voltage;
Fig. 8 is the IV characteristic curve after 0.1 μ m SOI technology NMOS (N type metal oxide semiconductor) pipe punctures;
The situation of change that Fig. 9 reduces along with grid thickness for grid oxygen puncture voltage;
Figure 10 is the common ground line loop syndeton under a kind of AC-battery power source that the present invention relates to;
Figure 11 is the comprehensive syndeton under a kind of AC-battery power source that the present invention relates to;
Electric current when Figure 12 applies positive ESD voltage for a kind of input of Figure 10 structure to the output path of flowing through;
Electric current when Figure 13 applies positive ESD voltage for a kind of input of Figure 11 structure to the output path of flowing through;
Figure 14 is for being the simplified structure under a kind of AC-battery power source that the present invention relates to, and the electric current of input when output the is applied positive ESD voltage path of flowing through;
Figure 15 considers loop wire 102,101 for Fig. 3 structure dead resistance, power line 102, ground wire 101 be used as power supply loop 22, ESD (ESD voltage be input 61 pair outputs apply positive ESD voltage) the current path situation of line loop 21 when using;
Figure 16 Fig. 3 structure considers that loop wire 102,101 has dead resistance, adopt power line loop 22 and ground line loop 21, and ESD (ESD voltage be input 61 pair outputs apply positive ESD voltage) the current path situation of IC interior power line 102/ ground wire 101 many places when being connected with power supply loop 22/ ground line loop 21.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The method for packing of this raising antistatic capability of integrated circuit chip provided by the invention, employing adds the method for electric capacity between VDD and VSS, ESD voltage is dropped to a very low level to be added on the integrated circuit, and with electric capacity two ends parallel resistor will be stored on this electric capacity electric charge effectively bleed off fall, can guarantee that the chip internal circuit does not come to harm, and has guaranteed that effectively chip has good ESD barrier propterty after encapsulation when to bear blanking time be 1 second repeatedly ESD voltage.
Fig. 1 is the encapsulating structure of the exemplary band ESD electric capacity protection of a kind of single supply of the present invention.This encapsulating structure comprise integrated circuit 71, esd protection electric capacity 10, bleed off ESD stored charge with resistance 13, power line loop 22, line loop 21, electric power connection line 32,34,36,38,44 and ground wire connecting line 31,33,35,37,41.Electric capacity 10 is connected with power line loop 22 with resistance 13 1 ends, and the other end is connected with ground line loop 21; Power line loop 22 links together by the power line 102 of electric power connection line 32,34,36,38,44 and integrated circuit 71 inside, and ground line loop 21 links together by the power line 101 of ground wire connecting line 31,33,35,37,41 and integrated circuit 71 inside.
Wherein, esd protection electric capacity 10 is patch capacitors, and capacitance is at 0.05 μ F to 50 μ F; Bleed off ESD stored charge is Chip-Rs with resistance 13, and resistance value 10k ohm is to 1G ohm; At input end when floating, power line are in the positive voltage bias state; open or inferiorly open electric leakage and come bleed off electric capacity 10 store charges to the situation that satisfies the esd protection demand under at the metal-oxide-semiconductor that can utilize integrated circuit 74 inside, can utilize integrated circuit 71 self as bleed off ESD stored charge resistance 13.Power line loop 22 and ground line loop 21 usefulness aluminium, copper, gold or corresponding alloy are produced on the surperficial or inner of encapsulation shell 100, and its thickness is 10 μ m to 500 μ m, and width is greater than 100 μ m.
When not adopting loop structure, if bearing the ESD voltage stress, integrated circuit 71 is not damaged, then the power supply loop wire 102 of IC interior and ground wire loop wire 101 can be used as power line loop 22 and 21 uses of ground line loop.Connecting line the 31,33,35,37, the 41st between connecting line 32,34,36,38,44 between ic power loop wire and the power line loop 22 and integrated circuit ground wire loop wire and the ground line loop 21, the power service duct of integrated circuit 71, also be the impedance path that makes the ESD electric current enter loop 21,22, be used to reduce the impedance problems of too on the ESD current channel that power supply loop wire 102 and 101 impedances of ground wire loop wire because of integrated circuit 71 inside bring more greatly.
Integrated circuit is at the voltage source that has used different magnitudes of voltage or the voltage source of the identical magnitude of voltage of insulation request is arranged, when promptly needing the AC-battery power source power supply, the electric capacity method of attachment of ESD safeguard structure has common-battery source line loop (22,24) and the common loop method of attachment and the method for attachment comprehensively of line loop (21,23) altogether.Wherein altogether in the line loop method, all independently power line (22,24)/ground wire (21,23) all be connected the method for one group of (one or more) electric capacity with a certain common ground.This common ground can be selected one arbitrarily in each independent ground wire (21,23).In the line loop method of common-battery source, all independently power line (22,24)/ground wire (21,23) all be connected the method for one group of (one or more) electric capacity with a certain public power wire.This public power wire can select one arbitrarily in each independent current source line (22,24).In the method for attachment, any independent current source line (22,24) all will be connected one group of (one or more) electric capacity with any one independent ground wire (21,23) comprehensively.
In the method for attachment of these electric capacity, the common-battery source line loop of corresponding resistor or the common loop method of attachment and the method for attachment comprehensively of line loop altogether then are to organize corresponding electric capacity next door at each, electric resistance structure of placement in parallel; And when integrated circuit 71 self can satisfy the stored charge demand of bleed off electric capacity, can use integrated circuit 71 inner metal-oxide-semiconductors to use in the presence of described resistance.
In addition; when the anti-ESD of integrated circuit 71 self is very capable; the esd protection framework of AC-battery power source also can adopt the method for attachment of simplification, promptly only need one or more independent current sources of integrated circuit with independently between respectively be connected one group of electric capacity (one or more) and a resistance.
In front in the protection framework of the AC-battery power source of Lun Shuing; each independent current source of being discussed, adopt the power line loop, structures such as line loop, lead-in wire method, electric capacity, resistance in size, size, with the replacement method of internal circuit etc., all consistent with aforementioned single supply situation.
Below will be described in more detail the present invention by concrete experimental data:
The mode of inserting electric capacity when the present invention adopts a kind of the encapsulation between power line and ground wire absorbs the ESD voltage wave.Amount of charge expression formula according to capacitance stores:
Q=U * C, wherein,
Q is the amount of charge that electric capacity stores, the unit coulomb;
U is the voltage at electric capacity two ends, the unit volt;
C is an electric capacity, the unit farad.
When the capacitance that adds between power line and ground wire is enough big:
The model configuration figure Fig. 4 that absorbs the ESD voltage wave by electric capacity as can be known, the C1 stored charge ability of ESD voltage generation circuit is:
Q1＝U1×C1
Be connected between power line VDD and the ground wire VSS, capacitor C 2 (practical application is electric capacity 10) the stored charge ability that is used for absorbing the ESD voltage wave is:
Q2＝U2×C2
Because C2 (μ F level), can think under the limiting case that the electric charge that preceding C1 charge stored Q1 of ESD voltage release and ESD voltage release back capacitor C 2 absorb equates than the big several magnitude of C1 (hundred pF levels), that is:
Q1＝Q2
Can know by HBM model (human body discharging model), under 8000V HBM ESD,
U1＝8000V，C1＝100pF
Q1=8000 * 100 * 1e-12=8e-7 coulomb
When the electric capacity that is connected between power line and the ground wire was 0.47 μ F, C2 was 0.47 μ F, then has:
Q2＝Q1＝8e-7＝U2×0.47×1e-6
U2＝1.7V。
Analog result as shown in Figure 5.
In addition, when the capacitor C 2 that is connected between VDD and the VSS is 4.7 μ F, can calculate U2=0.17V by formula Q1=Q2.
For bleed off capacitor C 2 charge stored, too much to prevent capacitor C 2 charge stored, the accumulation of capacitor C 2 both end voltage is too high, need be in electric capacity two ends parallel connection one resistance R 2.Institute's parallel resistance will be considered two factors, on the one hand can be with electric charge bleed off to a lower level of capacitance stores in the enough short time, and the static leakage that brings on the other hand will be in an acceptable scope.
Fig. 6 is that when parallel resistance was 1M ohm, capacitance voltage is situation over time after capacitor C 2 was born 8000V ESD voltage.After side circuit bears ESD voltage, because input 61 (Fig. 3) is in floating, internal circuit is in inferior opening greatly, between power vd D (102) and VSS (101) less leak resistance is arranged, and a kind of microcontroller circuit measured result as shown in Figure 7.
As can be seen from Figure 7, input 61 is under floating, and after the voltage on the power line 102 was greater than 1.1V, the resistance between power line 102 and the ground wire 101 was less than 1M ohm.Be that the circuit bleed off that most of electric charge can be in inferior opening from integrated circuit 71 inside falls, the voltage (U2) between power line 102 and ground wire 101 is less than 1.1V.This shows that the energy force rate result shown in Figure 6 of resistance R 2 and integrated circuit 71 1 time-out bleed off ESD electric currents will get well.
On the basis of analog result, consider actual conditions again, because the resistivity of aluminium is 2.6548 * 10
-8Ω .m, the resistivity of copper is 1.678 * 10
-8Ω .m is equivalent to the thick aluminum steel of 1 μ m, and 120 μ m are wide, and resistance was 1 ohm when 4.5mm was long, or the thick copper cash of 1 μ m, and 120 μ m are wide, and resistance was 1 ohm when 7.15mm was long.Suppose to adopt 4 layers of copper wiring to be used for VDD 102 and VSS101 line, thickness is respectively 0.5 μ m/0.5 μ m/0.5 μ m/1 μ m.Be that gross thickness is 2.5 μ m, length is 17.8mm during 1 Ohmic resistance.A VDD/VSS ring of the chip line loop resistance of a 8mm * 8mm is about 2 ohm respectively.
Adopt single capacitor, and power line 102, ground wire 101 in the presence of power supply loop 22, line loop 21 when using, as shown in figure 15, as can be seen from the figure, after electric current comes out from input PAD 61, both sides from power line flow to electric capacity 10 respectively, through flowing into output PAD 63 behind the electric capacity again from the ground wire both sides, so line loop resistance can seen the parallel resistance of two ground wire semi-rings of series connection after the parallel connection of two power line semi-rings.All-in resistance is about 1 ohm.During 8000V ESD voltage, electric current is about 5.3 amperes.Pressure drop on loop wire is 5.3V.
See that from Fig. 8 and Fig. 9 obvious voltage drop is excessive.The present invention adopts power line loop and ground line loop, and the head it off that power line 102 and power line loop 22 and ground wire 101 and ground line loop 21 linked together in many places, as shown in figure 16, consider that PAD connecting line 31,33,35,37,41 and 32,34,36,38,44 equal diameters are 50 μ m, length is 3mm, and resistivity is 2.5 * 10
-8Ω .m, power line loop 22, and 21 thickness be 100 μ m, width is 200um, girth is 40mm, resistivity is 1.678 * 10
-8Ω .m; Then the dead resistance of connecting line is connected with ground wire connecting line 33,35 in parallel by loop 21,22 after can being similar to and regarding electric power connection line 34,36 parallel connections as, resistance value is 0.038 ohm, half power line loop of two parallel connections and 0.017 ohm of dead resistance after half ground line loop of two parallel connections is connected, power line 102 then can be regarded as the parallel resistance that two power lines 1/8 encircle back two ground wires, 1/8 ring of connecting in parallel with ground wire 101, and line loop resistance is 0.25 ohm.
Thus, when 8000V ESD voltage, the voltage on the connecting line is reduced to 0.2V, and the pressure drop on the loop is 0.09V, and the pressure drop on the loop wire is 1.33V, and stagnation pressure is reduced to 1.62V.Effect significantly promotes.
From the analog result of front, the voltage at electric capacity two ends can reach 0.17V to 1.7V, and numerical value is along with electric capacity differs in size.And adopt CLAMP (cascading water pipe) structure, suppose to adopt NMOS CLAMP structure, as shown in Figure 8, when 5V, reaching 5.3A needs 1766 μ m/0.1 μ m pipes, and reaching 5.3A when 4.5V needs 3500 μ m/0.1 μ m pipes, and reaching 5.3A when 4V needs 6050 μ m/0.1 μ m pipes.Adopt diode CLAMP structure, limiting voltage is 1.1 times of vdd voltages (otherwise having the electric leakage problem), is about 2V, and is all in all, high a lot of than capacitance structure voltage (0.17V to 1.7V).
Under many power supplys situation, adopting POWER PLAN structure (diode 755,756 and 757,758 is seen Figure 14) between power supply 102 and the power supply 104 and between ground wire 101 and the ground wire 103 usually.This diode structure area area with respect to NMOS cascading water tubular construction is smaller relatively, but usually when the big ESD electric current of bleed off, the diode both end voltage also can reach more than the 2V, in the deep-submicron device, the bleed off ability of circuit is also had bigger influence.And use Figure 10, particularly Figure 11 structure, then can avoid on POWER PLAN diode, producing the problem of pressure drop.
Figure 10 is a kind of common ground wire loop structure of AC-battery power source, and VDD2 104, VDD1 102, VSS2 103 have an electric capacity to be connected with VSS1 101.Applying positive ESD voltage with the output 63 between the input between VDD1 and the VSS1 61 couples of VDD2, VSS2 is example, as shown in figure 12, the ESD electric current flow into the power line 102 of integrated circuit from diode 752, and enter power line loop 22 by connecting line 44, enter the VSS2 line by capacitor I 10, the H10 that connects between VDD1 loop 22 and the VSS2 loop 23 afterwards, and get back to integrated circuit 71 inside by connecting line 241, enter VSS2 line 103, and by diode 753 enter output PAD 63, i.e. the ground end of ESD test macro.Here, capacitor I 10 has been served as traditional NMOS cascading water tubular construction, H10 has then served as POWER PLAN diode structure, capacitor I 10, H10 have dropped to a low-down level with the voltage drop of cascading water pipe and POWER PLAN diode respectively, reduce the voltage drop on the ESD current path significantly, improved the anti-ESD ability of product.
Figure 11 is a kind of comprehensive syndeton of AC-battery power source, loop connection method difference together, this structure is that all independent current sources 102,104 all will have electric capacity to be connected with independent ground wire 101,103, has realized just can bearing with a capacitance structure purpose of cascading water tubular construction and the effect of POWER PLAN diode structure.Applying positive ESD voltage with the output 63 between the input between VDD1 and the VSS1 61 couples of VDD2, VSS2 is example, as shown in figure 13, the ESD electric current flow into the power line 102 of integrated circuit from diode 752, and enter power line loop 22 by connecting line 44, enter the VSS2 line by the electric capacity D10 between VDD1 loop 22 and the VSS2 loop 23 afterwards, get back to integrated circuit 71 inside by connecting line 241, enter VSS2 line 103, and by diode 753 enter output PAD 63, i.e. the ground end of ESD test macro.Here, electric capacity D10 has served as traditional NMOS cascading water tubular construction, the effect of two structures of POWERPLAN diode structure, and voltage drop has been dropped to a lower level, has further improved the anti-ESD ability of product.
In the SOI circuit of some critical sizes big (as 1.2 μ m technologies), metal-oxide-semiconductor can bear bigger voltage after (snapback) worn in rapid counterattack (can bear 9V as the NMOS pipe, the PMOS pipe can bear 15V), behind the ESD protection circuit of suitable processing integrated circuit 71 inside, POWER PLAN diode just can satisfy the anti-ESD demand of integrated circuit 71, the AC-battery power source simplified structure of designing thus as shown in figure 14, the ESD electric current flow into the power line 102 of integrated circuit from diode 752, and enter power line loop 22 by connecting line 44, enter the VSS1 line by the electric capacity 10 between VDD1 loop 22 and the VSS1 loop 21 afterwards, and get back to integrated circuit 71 inside by connecting line 41, enter VSS1 line 101, enter VSS2 line 103 by POWER PLAN diode 757, enter output PAD 63, i.e. the ground end of ESD test macro by diode 753 again.
Here, electric capacity D10 has served as traditional NMOS cascading water tubular construction, reduced voltage drop maximum on the traditional E SD safeguard structure current path significantly, though POWER PLAN diode drop is still than higher, but because the anti-ESD ability of integrated circuit 71 self is just more intense, so can satisfy the ESD protection requirements of circuit, reached the purpose that satisfies the ESD protection requirements with simple package structure.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (21)
1. a method for packing that improves antistatic capability of integrated circuit chip is characterized in that, this method comprises:
On the encapsulation shell, make a power line loop (22) and a ground line loop (21);
Between power line loop (22) and ground line loop (21), be connected one or more electric capacity (10) and a resistance (13);
The place that the one or more of integrated circuit (IC) chip (71) are linked to each other with chip internal power line (102) goes between on the power line loop (22);
The place that the one or more of integrated circuit (IC) chip (71) are linked to each other with chip internal ground wire (101) goes between on the ground line loop (21).
2. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1, it is characterized in that, described power line loop (22) is to be made in encapsulation shell surface or inner ring-type circuit, and in some cases that integrated circuit (IC) chip (71) is inner power line VDD (102) is as power line loop (22).
3. the method for packing of raising antistatic capability of integrated circuit chip according to claim 2 is characterized in that, described power line loop (22) is made with aluminium, copper, gold or corresponding alloy, and thickness is 10 μ m to 500 μ m, and width is greater than 100 μ m.
4. the method for packing of raising antistatic capability of integrated circuit chip according to claim 2, it is characterized in that, described some situation is in electrostatic discharge protective ESD process, the input/output circuitry of integrated circuit (IC) chip (71), the voltage that internal circuit is born in the case can damage below the voltage at it, comprise following several situation and combination:
A, described electric capacity (10) adopt big capacitance;
Input/output circuitry, the internal circuit of b, integrated circuit (IC) chip (71) can bear higher voltage under worst situation;
Adopt diode between c, I/O pressure welding pad PAD and chip internal power line (102)/chip internal ground wire (101) than large tracts of land or girth;
D, chip internal power line (102) wider width have the situation of multiple layer metal as chip internal power line (102);
E, the anti-ESD Capability Requirement of integrated circuit (IC) chip (71) are not high.
5. the method for packing of raising antistatic capability of integrated circuit chip according to claim 4, it is characterized in that, described bigger, higher, broad, not high, be meant above a to e the resultant effect of totally 5 factors can satisfy in the ESD process, integrated circuit (IC) chip (71) voltage that input/output circuitry, internal circuit bore is benchmark damaging below the voltage at it.
6. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1, it is characterized in that, described ground line loop (21) is to be made in encapsulation shell surface or inner ring-type circuit, and in some cases that integrated circuit (IC) chip (71) is inner ground wire VSS (101) is as ground line loop (21).
7. the method for packing of raising antistatic capability of integrated circuit chip according to claim 6 is characterized in that, described ground line loop (21) is made with aluminium, copper, gold or corresponding alloy, and thickness is 10 μ m to 500 μ m, and width is greater than 100 μ m.
8. the method for packing of raising antistatic capability of integrated circuit chip according to claim 6, it is characterized in that, described some situation is in electrostatic discharge protective ESD process, the input/output circuitry of integrated circuit (IC) chip (71), the voltage that internal circuit is born in the case can damage below the voltage at it, comprise following several situation and combination:
A, described electric capacity (10) adopt big capacitance;
Input/output circuitry, the internal circuit of b, integrated circuit (IC) chip (71) can bear higher voltage under worst situation;
Adopt diode between c, I/O pressure welding pad PAD and chip internal power line (102)/chip internal ground wire (101) than large tracts of land or girth;
D, chip internal ground wire (101) wider width have the situation of multiple layer metal as chip internal ground wire (101);
E, the anti-ESD Capability Requirement of integrated circuit (IC) chip (71) are not high.
9. the method for packing of raising antistatic capability of integrated circuit chip according to claim 8, it is characterized in that, described bigger, higher, broad, not high, be meant above a to e the resultant effect of totally 5 factors can satisfy in the ESD process, integrated circuit (IC) chip (71) voltage that input/output circuitry, internal circuit bore is benchmark damaging below the voltage at it.
10. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1 is characterized in that, described electric capacity (10) is patch capacitor, is installed in encapsulation shell surface or inner, and capacitance is 0.05 μ F to 50 μ F.
11. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1, it is characterized in that, described resistance (13) is Chip-R, be installed in encapsulation shell surface or inner, resistance value be 10k ohm to 100M ohm, in some cases that integrated circuit (71) is inner metal-oxide semiconductor (MOS) metal-oxide-semiconductor uses as resistance (13).
12. the method for packing of raising antistatic capability of integrated circuit chip according to claim 11 is characterized in that,
Described some situation is that input/two-way end is in floating, when chip internal power line (102) is in the positive voltage bias state, can utilizes metal-oxide-semiconductor to open or inferiorly open electric charge bleed off that the electric leakage mode stores electric capacity (10) to the situation that satisfies the esd protection demand;
The inner metal-oxide-semiconductor of described integrated circuit (71) comprises the metal-oxide-semiconductor structure (721) in input (711,712), output mos pipe (731,732) and the internal circuit.
13. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1, it is characterized in that, describedly between power line loop (22) and ground line loop (21), be connected one or more electric capacity (10), be meant between most of situation power line loop (22) and ground line loop (21) and be connected an electric capacity, but under following situation, to obtain good ESD protective capacities, need to connect a plurality of equally distributed electric capacity:
A, at power line loop (22) and ground line loop (21) when width is narrower, particularly during as corresponding loop, adopt a plurality of electric capacity with chip internal power line (102)/chip internal ground wire (101), protect the ESD ability with the anti-electrostatic discharging that promotes chip;
B, when needing better voltage source filtering performance, power supply adopts a plurality of electric capacity, to promote chip performance;
C, the ESD voltage ratio that can bear at inner each metal-oxide-semiconductor of integrated circuit (IC) chip (71) are lower, when being used in the ESD protection on the deep-submicron yardstick chip, adopt a plurality of electric capacity, to promote the anti-ESD ability of chip.
14. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1, it is characterized in that, the described place that the one or more of integrated circuit (IC) chip (71) are linked to each other with chip internal power line (102) goes between on the power line loop (22), be that power supply PAD with integrated circuit (IC) chip (71) is connected on the power supply PAD (46) of encapsulating structure by line (44), but the dead resistance on chip internal power line (102) can have a strong impact under the situation of the anti-ESD ability of chip, with the accessory power supply PAD of chip internal by lead-in wire (32,34,36,38) be connected on the power line loop (22).
15. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1, it is characterized in that, the described place that the one or more of integrated circuit (IC) chip (71) are linked to each other with chip internal ground wire (101) goes between on the ground line loop (21), be that ground wire PAD with integrated circuit (IC) chip (71) is connected on the ground connection PAD (43) of encapsulating structure by line (41), but the dead resistance on chip internal ground wire (101) can have a strong impact under the situation of the anti-ESD ability of chip, with the auxiliary ground wire PAD of chip internal by lead-in wire (31,33,35,37) be connected on the ground line loop (21).
16. the method for packing of raising antistatic capability of integrated circuit chip according to claim 1 is characterized in that, when this method was used AC-battery power source, described electric capacity (10) or resistance (13) further adopted following connected mode:
The line loop method of attachment of common-battery source, line loop method of attachment altogether, method of attachment and simplification method of attachment comprehensively.
17. the method for packing of raising antistatic capability of integrated circuit chip according to claim 16, it is characterized in that, described AC-battery power source is to use the voltage source with different magnitudes of voltage in same integrated circuit (IC) chip (71), or uses the voltage source with identical magnitude of voltage that insulation request is arranged.
18. the method for packing of raising antistatic capability of integrated circuit chip according to claim 16 is characterized in that, described electric capacity (10) adopts line loop method of attachment altogether to comprise:
With all independently power line (22,24)/ground wire (21,23) be connected one or more electric capacity respectively with a certain common ground, and at the other in parallel resistance of placing of each group electric capacity, this common ground is any in each independent ground wire (21,23).
19. the method for packing of raising antistatic capability of integrated circuit chip according to claim 16 is characterized in that, described electric capacity (10) adopts common-battery source line loop method of attachment to comprise:
With all independently power line (22,24)/ground wire (21,23) be connected one or more electric capacity respectively with a certain public power wire, and at the other in parallel resistance of placing of each group electric capacity, this public power wire is any in each independent current source line (22,24).
20. the method for packing of raising antistatic capability of integrated circuit chip according to claim 16 is characterized in that, described electric capacity (10) adopts comprehensive method of attachment to comprise:
Any independent current source line (22,24) is connected one or more electric capacity respectively with any one independent ground wire (21,23) in the integrated circuit, and at the other resistance of placing in parallel of each group electric capacity.
21. the method for packing of raising antistatic capability of integrated circuit chip according to claim 16 is characterized in that, described electric capacity (10) adopts the simplification method of attachment to comprise:
Respectively be connected one or more electric capacity with between the one or more independent current source lines in the integrated circuit and the independent ground wire, and at the other resistance of placing in parallel of each group electric capacity.
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| CN103021893B (en) * | 2012-12-30 | 2015-06-03 | 深圳中科***集成技术有限公司 | Processing method for multi-way electrostatic discharge protection device |
| CN105279096B (en) * | 2014-07-04 | 2019-04-02 | 群联电子股份有限公司 | Module and memory storage apparatus is electroplated with it in system-in-package structure |
| CN105047642B (en) * | 2015-08-12 | 2024-01-19 | 深圳市槟城电子股份有限公司 | Port protection circuit integrated package |
| CN108037325B (en) * | 2017-11-24 | 2020-07-21 | 中国科学院微电子研究所 | Low-leakage connector |
| CN108767917B (en) * | 2018-05-24 | 2021-01-01 | 南京中感微电子有限公司 | Battery protection system |
| CN108461844A (en) * | 2018-05-24 | 2018-08-28 | 南京中感微电子有限公司 | Battery protection chip and battery protection chip |
| CN112218449B (en) * | 2019-07-09 | 2021-08-27 | 梅州市鸿利线路板有限公司 | Double-sided circuit board processing technology |
| CN111900158B (en) * | 2020-08-07 | 2024-02-20 | 深圳市中明科技股份有限公司 | Method for ESD protection of integrated circuit |
| CN114501967B (en) * | 2022-01-20 | 2023-03-24 | 绵阳惠科光电科技有限公司 | Display panel and electronic device |
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