CN101552605A - An interface circuit capable of tolerating high voltage input - Google Patents
An interface circuit capable of tolerating high voltage input Download PDFInfo
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- CN101552605A CN101552605A CNA2009100844485A CN200910084448A CN101552605A CN 101552605 A CN101552605 A CN 101552605A CN A2009100844485 A CNA2009100844485 A CN A2009100844485A CN 200910084448 A CN200910084448 A CN 200910084448A CN 101552605 A CN101552605 A CN 101552605A
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Abstract
An interface circuit capable of tolerating high voltage input, I/O pin connecting external, a pull-up/ pull-down structure provides high/low power level of output to the I/O pin. An impedance control circuit shuts the pull-up/ pull-down structure in receiving mode, and activates the pull-up/ pull-down structure in transmission mode. A pull-up/ pull-down protection structure protects the pull-up/ pull-down structure in receiving mode. A gate protection circuit provides protection voltage to the pull-up protection structure in receiving mode. A N-well bias circuit provides a bias voltage that equaling to internal power supply for the pull-up structure and the N-well where the PMOS located in of the pull-up protection structure in transmission mode; and in a receiving mode, if voltage of the I/O pin is higher than voltage of the internal power supply, providing a bias voltage that approaching to voltage of the I/O pin to the pull-up structure and the N-well where the PMOS located in of the pull-up protection structure, otherwise, providing a bias voltage that equaling to internal power supply. Well bias drive circuit provides driving signal to the N-well bias circuit in transmission mode.
Description
Technical field
The present invention relates to a kind of interface circuit that can bear the external high voltage input.
Background technology
Along with the continuous progress of CMOS technology, circuit design is rapidly to deep submicron process evolution, and supply voltage also progressively is reduced to 2.5V or 1.8V.Yet some peripheral components chips still are operated on the higher voltage level, and for example 3.3V or 5V cause may having different voltage standards in the system and move at the same time.For example, when the chip that an internal interface circuit voltage is 2.5V must be received on 3.3V or the 5V external interface, or internal interface circuit voltage chip that is 3.3V is must receive on the 5V external interface time, if in chip I/O Interface design, do not consider problem of withstand voltage, will cause various problems, for example oxide layer breakdown, cause Hot-carrier Degradation Effects and form leakage current or the like, will cause designed interface circuit sharply to shorten useful life.
In order to solve the problem of withstand voltage that may exist in the above-mentioned interface circuit, various solutions have been proposed, adopt following three kinds of schemes to realize the withstand voltage of device at present usually:
(1) utilizes process modification.For example adopt multiple-grid oxide layer technology, with might exist the transistor of overpressure problems all to use the thick-oxide transistors device to replace, the shortcoming of this method is to add more mask plate in production line, thereby increases technological process, has increased manufacturing cost greatly;
(2) in the basic technology production line, use extension drain terminal device.When layout design, might be subjected to the transistor drain area increasing that overvoltage threatens, and utilize the dead resistance branch of drain electrode self to subtract part voltage.This method does not need special technology, but compares with normal component, and the performance of its unit are device becomes very poor;
(3) utilize the standard technology device.Circuit structure by innovation solves high voltage tolerance problem, guarantees that the voltage difference of all crystals tube terminal all satisfies process constraint.Because this method need not special process, and the required device area change is little, therefore just adopted by most of designing institutes.Existing NMOS-blocking technology; the dynamic cascode biasing circuit of in " the A new charge pumpcircuit dealing with gate-oxide reliability issue in low-voltage processes " that delivered on the circuits and systems in 2004, mentioning as M.-D.Ker and charge pump circuit etc.; though can realize high withstand voltage design; but need use a large amount of auxiliary circuits in order to reach the protection purpose; circuit control is complicated, and can take a large amount of chip areas.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, but the interface circuit that provides a kind of tolerating high voltage that adopts low pressure process to realize to import.
Technical solution of the present invention is: but the interface circuit of a kind of tolerating high voltage input, comprise output driving circuit, input buffer and impedance control circuit, output driving circuit comprises PMOS transistor M20, M21 and nmos pass transistor M22, M23, impedance control circuit comprises inverter I5 and I6 and NAND gate K1 and K2, mode control signal TS is connected to the first input end of NAND gate K1 and K2 simultaneously, data output signal DATA_OUT is connected to second input of NAND gate K1 behind inverter I6, data output signal DATA_OUT also directly is connected to second input of NAND gate K2, the output of NAND gate K1 is connected to the gate terminal of PMOS transistor M20, the source electrode termination voltage source V CCO of PMOS transistor M20, the drain electrode end of PMOS transistor M20 is connected to the source terminal of PMOS transistor M21, the drain electrode end of PMOS transistor M21 links to each other with the drain electrode end of nmos pass transistor M22 as the I/O end of interface circuit, and the gate terminal of the source terminal of PMOS transistor M21 is connected to reference potential; The output of NAND gate K2 is connected to the gate terminal of nmos pass transistor M23 behind inverter I5, the source electrode termination reference potential of nmos pass transistor M23, the source terminal of the drain electrode termination nmos pass transistor M22 of nmos pass transistor M23 and the input of input buffer, the grid termination voltage source V CCO of nmos pass transistor M22; Interface circuit is a transmission mode when mode control signal TS=1; interface circuit carries out data output; interface circuit is a receiving mode when mode control signal TS=0; interface circuit output high resistant signal; external input signal is through the input buffer input interface circuit; also comprise gate protection circuit in the interface circuit, the gate terminal of gate protection circuit control PMOS transistor M21, damage voltage source V CCO when preventing that voltage when interface circuit I/O end is higher than the voltage of voltage source V CCO.
Described gate protection circuit comprises that PMOS transistor M15, median voltage generation circuit and pulse produce circuit, the gate terminal of PMOS transistor M15 drain electrode termination PMOS transistor M21, the drain electrode end of PMOS transistor M15 source electrode termination nmos pass transistor M22; The median voltage generation circuit produces one and is higher than reference potential and is lower than the median voltage of voltage source V CCO voltage and acts on the gate terminal of PMOS transistor M15, makes the drain electrode end of PMOS transistor M15 provide the identical voltage of holding with interface circuit I/O of input voltage value for the gate terminal of PMOS transistor M21; When interface circuit changed receiving mode into by transmission mode, pulse produced the gate terminal that circuit produces a pulse signal and acts on PMOS transistor M15, the recovery time when improving mode switch.
Described median voltage generation circuit comprises nmos pass transistor M10, M11, M14 and PMOS transistor M12, M13; The gate terminal of nmos pass transistor M10 and drain electrode end are connected to voltage source V CCO simultaneously, the drain electrode end of source electrode termination nmos pass transistor M11; The gate terminal of nmos pass transistor M11 and drain electrode end are connected to the source terminal of nmos pass transistor M10 simultaneously, and source terminal connects the output of gate terminal, PMOS transistor M12 source terminal and the pulse generation circuit of PMOS transistor M15 simultaneously; The gate terminal of PMOS transistor M12 and drain electrode end are connected to the source terminal of PMOS transistor M13 simultaneously; The gate terminal of PMOS transistor M13 and drain electrode end are connected to the drain electrode end of nmos pass transistor M14 simultaneously; The source electrode termination reference potential of nmos pass transistor M14, gate terminal is by the inverted signal TS1 control of mode control signal TS.
Described pulse produces circuit and comprises PMOS transistor M8, nmos pass transistor M9, inverter I1～I4 and NOR gate N1; The input termination mode control signal TS of inverter I1, output is connected to the gate terminal of PMOS transistor M8 and the input of inverter I2 and I3 simultaneously; The output of inverter I3 is connected to the input of inverter I4, and the output of inverter I2 and inverter I4 is connected to two inputs of NOR gate N1 respectively, the gate terminal of the output control nmos pass transistor M9 of NOR gate N1; The source electrode termination voltage source V CCO of PMOS transistor M8, drain electrode end link to each other with the drain electrode end of nmos pass transistor M9 and produce the output of circuit, the source electrode termination reference potential of nmos pass transistor M9 as pulse.
Also comprise N trap biasing circuit in the described interface circuit, when interface circuit is operated in transmission mode, described N trap biasing circuit provides the bias voltage identical with voltage source V CCO for the residing N trap of PMOS transistor M20 and M21, when interface circuit is operated in receiving mode, if the input voltage of interface circuit I/O end is higher than the voltage of voltage source V CCO, described N trap biasing circuit provides the identical bias voltage of holding with interface circuit I/O of input voltage for the residing N trap of PMOS transistor M20 and M21.
Described N trap biasing circuit comprises PMOS transistor M1～M5, the source terminal of PMOS transistor M5 links to each other with voltage source V CCO, the drain electrode end of PMOS transistor M5 links to each other with its residing N trap and is connected on PMOS transistor M20 and the residing N trap of the M21 N_WELL, and the gate terminal of PMOS transistor M5 is connected to mode control signal TS; The source terminal of PMOS transistor M1 and M2 all is connected to voltage source V CCO, and drain electrode end and residing N trap all are connected to N_WELL, and the gate terminal of PMOS transistor M1 is connected to the I/O end of interface circuit, and the gate terminal of PMOS transistor M2 is connected to N_WELL; The drain electrode end of PMOS transistor M3 and M4 all is connected to the I/O end of interface circuit, and source terminal and residing N trap all are connected to N_WELL, the grid termination voltage source V CCO of PMOS transistor M3, and the gate terminal of PMOS transistor M4 is connected to N_WELL.
Also be connected with the trap bias drive circuit between the gate terminal of described PMOS transistor M5 and the mode control signal TS, described trap bias drive circuit for N trap biasing circuit provides drive signal, comprises nmos pass transistor M6 and M7 when transmission mode; The grid termination mode control signal TS of nmos pass transistor M6, source electrode termination reference potential, the source terminal of drain electrode termination nmos pass transistor M7; The grid termination voltage source V CCO of nmos pass transistor M7, the gate terminal of drain electrode termination PMOS transistor M5.
The present invention's advantage compared with prior art is:
(1) the invention provides one can be operated in transmission and receive two kinds of interface circuits under the pattern, when interface circuit is operated in receiving mode, the I/O pin can be accepted the high level signal that is higher than interface supply voltage VCCO in this chip that produces from other circuit in the board level system, and any transistor in can interface circuit constitutes the threat of reliability aspect; Solve the device withstand voltage problem of interface circuit when the receiving mode by drawing on providing, do not need technology is made improvements or adopt special process, saved manufacturing cost greatly with drop-down protection structure;
(2) the present invention is by providing gate protection circuit, guarantee that interface circuit draws protective circuit on adding after, the high level input on the I/O pin can docking port supply voltage VCCO injection current, influences the correct work of interface circuit;
(3) the present invention produces circuit by adopt pulse in gate protection circuit, has accelerated the transformation of interface circuit from data-transmission mode to the Data Receiving pattern;
(4) the present invention is by providing N trap biasing circuit, guaranteed that interface circuit is no matter under transmission mode still is receiving mode, the residing N trap of PMOS transistor in the output driving buffer all is in a stable maximum potential, solve the electric leakage problem that parasitic diode can cause when voltage is higher than the N trap potential on the I/O pin, also improved the ability of system's antinoise and anti-breech lock simultaneously.
Description of drawings
But Fig. 1 is the theory diagram of the interface circuit of the present invention's tolerating high voltage input.
Embodiment
As shown in Figure 1, but be the theory diagram of the interface circuit of the present invention's tolerating high voltage input, comprise output driving circuit 1, input buffer 2, gate protection circuit 3, impedance control circuit 4, N trap biasing circuit 5 and trap bias drive circuit 6.Under the control of mode control signal TS, this interface circuit can be in transmission mode (being that the I/O pin is as output pin), perhaps is in receiving mode (being that the I/O pin is as input pin).When circuit was in transmission mode, the DATA_OUT signal was a data output signal.When circuit was in receiving mode, the DATA_IN signal received outer signals and is input to interface circuit inside.
If mode control signal TS is changed to transmission mode with this interface circuit, impedance control circuit 4 receives the data output signal DATA_OUT that the inner configurable logic blocks of fpga chip (CLB) produces, draw drive signal D1 and drop-down drive signal D2 in the generation, output driving circuit 1 draws output signal or drop-down output signal on producing the I/O pin under the control of D1 and D2.Simultaneously, when being in transmission mode, the TS control signal can enable trap bias drive circuit 6, trap bias control signal when producing output state acts on output driving circuit 1 and N trap biasing circuit 5, makes the output driving circuit 1 of N trap biasing circuit 5 when being in transmission mode that a N trap potential N_WELL who equals supply voltage VCCO is provided.
If mode control signal TS is changed to receiving mode with this interface circuit, impedance control circuit 4 no longer receives the data output signal DATA_OUT that the inner configurable logic blocks of fpga chip (CLB) produces, and draws drive signal D1 and drop-down drive signal D2 to make output driving circuit 1 be in high-impedance state in its generation simultaneously.The I/O pin receives outer input data, produces input signal IN1 by output driving circuit 1, produces the signal DATA_IN that sends into internal logic circuit behind input buffer 2.If input is high-voltage signal, after drop-down protection structure (transistor M22) processing in the output driving circuit 1, produce a logic high that pull-down structure (transistor M23) and input buffer 2 is not had the overvoltage damage.During receiving mode; mode control signal TS enables gate protection circuit 3; this moment, gate protection circuit 3 drew the grid G 1 of protection structure (transistor M21) that a protection voltage is provided in the output driving circuit 1; trap bias drive circuit 6 is in by state, not can on draw the protection structure (transistor M21) grid G 1 exert an influence.Equally; when receiving mode; N trap biasing circuit 5 can compare input signal and the internal source voltage VCCO on the I/O pin; for the N trap of PMOS pipe in the output driving circuit 1 provides a maximum potential; if the voltage of I/O pin is higher than internal source voltage VCCO voltage for last pull-up structure and on draw the PMOS transistor residing N trap of protection in the structure that a bias voltage near the I/O pin voltage is provided; if instead being lower than internal source voltage VCCO voltage, the voltage of I/O pin then still provides a bias voltage that equals internal source voltage VCCO for the N trap; the parasitic diode forward conduction of avoiding in the output driving circuit 1 P+ drain electrode and N trap by the PMOS pipe to constitute produces the path that leaks electricity.
When the I/O pin was used as input, the input voltage that the external world provides might surpass the supply voltage VCCO of interface circuit.When the input voltage value on the I/O pin was higher than VCCO, output driving circuit 1 was converted to IN1 with the incoming signal level on the I/O pin, and IN1 produces the DATA_IN signal through input buffer (2), sends into internal logic circuit.Generally speaking, require in the chip interface agreement 5V withstand voltage LVTTL, LVCOMS2 and PCI5 arranged, adopting the supply voltage VCCO of the interface circuit of LVTTL or PCI5 agreement is 3.3V, is 2.5V and adopt the supply voltage VCCO of the interface circuit of LVCOMS2 agreement.Here equaling 3.3V with VCCO is that example illustrates.When the supply voltage of interface circuit was 3.3V, the incoming level that the outside offers the I/O pin might must guarantee during design that all crystals pipe any two ends pressure reduction in the output driving circuit 1 is no more than 3.6V up to 5V.In order to realize this protection to output driving circuit 1, interface circuit of gate protection circuit 3 meeting generations is in the gate protection voltage under the receiving mode, to guarantee that all crystals pipe any two ends pressure reduction is no more than 3.6V in the output driving circuit 1.
Below the main modular among Fig. 1 is explained in detail.
One, impedance control circuit 4
Two, output driving circuit 1
When transmission mode, that a part of circuit (getting final product so that the I/O pin bears more high-tension that a part of circuit than interface circuit internal power source voltage VCCO) for withstand voltage design in the output driving circuit 1 is not worked; When receiving mode, the output buffer partial circuit in the output driving circuit 1 is not worked, and works for the partial circuit of withstand voltage design.
The control relative complex of pair pmos transistor M21 some.When applying the 5V input signal on the I/O pin, M21 must by, guaranteeing that electric current can not be circulated into the VCCO from the I/O pin, this just requires the voltage enough high (magnitude of voltage that is not less than on the I/O pin deducts threshold voltage, is approximately 4.3V) at grid G 1 place of PMOS transistor M21.Among the present invention, the output by gate protection circuit 3 for the grid of PMOS transistor M21 provides one to equal the 5V voltage imported on the I/O pin, is closed PMOS transistor M21 when receiving mode, introduce face gate protection circuit 3 as follows in detail.And when interface circuit is operated in output mode, nmos pass transistor M6 with the grid of PMOS transistor M21 drop-down be 0.The source electrode termination reference potential of nmos pass transistor M6, in order to protect M6 pipe, access nmos pass transistor M7 between the drain electrode of M6 and G1 point, the grid of M7 meets VCCO, even the voltage that G1 is ordered during receiving mode reaches 5V like this, the voltage that M6 drains can not surpass 3.6V yet.
Three, N trap biasing circuit 5
When receiving mode, can tolerate the I/O pin input voltage of 5V in order to make interface circuit, be connected to the transistorized N trap of PMOS voltage on the I/O pin and must be equal to or higher than voltage on the I/O pin.Because the diode of a parasitism of existence if there is electric current to continue to flow through this parasitic diode, can cause extra power consumption between the drain electrode of the P+ type of PMOS transistor M20, PMOS transistor M21 and N trap, also can influence transistorized operate as normal.Introduced the N trap biasing circuit of forming by PMOS transistor M1～M5 5 among the present invention for this reason.When the big threshold value of the voltage ratio N trap voltage on the I/O pin, PMOS transistor M4 can conducting, will move the voltage than the low threshold value of the voltage on the I/O pin on the N trap to.As interface circuit internal power source voltage VCCO during than the big threshold value of N trap voltage, can conducting at PMOS transistor M2, will move voltage on the N trap to than the low threshold value of VCCO.Draw on providing further, when the big threshold value of the voltage ratio VCCO on the I/O pin, PMOS transistor M3 conducting is with the voltage of moving on the N trap voltage on the I/O pin.When the voltage ratio VCCO on the I/O pin hanged down a threshold value, PMOS transistor M1 conducting will be moved VCCO on the N trap voltage.The employing transistor comes driving N trap voltage, compares only to rely on parasitic diode to come to have increased the ability of system's antinoise and anti-breech lock to the charging of N trap.
When transmission mode, trap bias drive circuit 6 is changed to 0 with the grid voltage of PMOS transistor M5, PMOS pipe M5 conducting, and this moment, N_WELL voltage equaled the voltage of interface power supply VCCO.
Four, gate protection circuit 3
As shown in the figure, during transmission mode, TS=1, the inverted signal TS1=0 of TS, PMOS transistor M8 conducting is high level with drawing on the G2 point, PMOS transistor M 15 by, this moment gate protection circuit 3 be in by state.NOR gate N1 is output as 0, and nmos pass transistor M9 closes.During TS1=0, nmos pass transistor M14 closes, and the median voltage generation circuit is not worked, and does not have quiescent dissipation.
During receiving mode, TS=0, TS1=1, PMOS transistor M8 are by, nmos pass transistor M14 conducting, and the stacked structure that nmos pass transistor M10, M11 and PMOS transistor M12, M13 form enables, and produces a median voltage and is added to the G2 point.The grid of M10, M11, M12, M13 is all received drain electrode separately, when the M14 conducting, the voltage that G2 is ordered is about VCCO/2, if the voltage on the I/O pin is 5V at this moment, PMOS pipe M15 conducting, and this moment, TS was a low level, M6 by, the G1 point voltage equals the voltage on the I/O pin, and voltage difference can not surpass 3.6V between any two ends of PMOS pipe.The ratio of the channel length of M10, M11, M12, M13 and channel width (L/W) is bigger, so equivalent resistance also very big (about 300K Ω) of these several metal-oxide-semiconductors, the equivalent resistance that is connected between voltage source V CCO and the reference voltage can reduce the quiescent dissipation from voltage source V CCO to ground when input pattern up to 1M Ω.
Pulse generation circuit has been accelerated the transformation from data-transmission mode to the Data Receiving pattern.This circuit only can produce a high pulse signal in a flash with nmos pass transistor M9 conducting at TS1 by what low level (transmission mode) was converted to high level (receiving mode), this high pulse signal only be present in that inverter I2, I3 have overturn and I4 also upset is not at that moment, the voltage that be added on 2 of the PMOS transistor M15 grid G this moment is 0, with the abundant conducting of M15,1 voltage of locating of the grid G of PMOS transistor M21 is pulled to rapidly with voltage on the I/O pin and equates.After inverter I4 also finished upset, the voltage that is added on 2 of the M15 grid G was stable VCCO/2.
Five, the trap bias drive circuit 6
At TS=1, when this interface circuit is in transmission mode, nmos pass transistor M6 conducting in the trap bias drive circuit 6, nmos pass transistor M7 also is in conducting state, for the grid G 1 of the PMOS transistor M21 in the output driving circuit 1 provides a low control signal, make it when the transmission high level, also be in conducting state; PMOS transistor gate in the N trap biasing circuit 5 links to each other with the grid G 1 of M21, and also be in conducting state this moment, for the N trap potential N_WELL in the output driving circuit 1 provides a bias voltage identical with voltage source V CCO.TS=0, when interface circuit is in receiving mode, trap bias drive circuit 6 by.
Six, input buffer 2
The content that is not described in detail in the specification of the present invention belongs to those skilled in the art's known technology.
Claims (7)
1, but a kind of interface circuit of tolerating high voltage input, comprise output driving circuit (1), input buffer (2) and impedance control circuit (3), output driving circuit comprises PMOS transistor M20, PMOS transistor M21 and nmos pass transistor M22, nmos pass transistor M23, impedance control circuit (3) comprises inverter I5 and inverter I6 and NAND gate K1 and NAND gate K2, mode control signal TS is connected to the first input end of NAND gate K1 and NAND gate K2 simultaneously, data output signal DATA_OUT is connected to second input of NAND gate K1 behind inverter I6, data output signal DATA_OUT also directly is connected to second input of NAND gate K2, the output of NAND gate K1 is connected to the gate terminal of PMOS transistor M20, the source electrode termination voltage source V CCO of PMOS transistor M20, the drain electrode end of PMOS transistor M20 is connected to the source terminal of PMOS transistor M21, the drain electrode end of PMOS transistor M21 links to each other with the drain electrode end of nmos pass transistor M22 as the I/O end of interface circuit, and the gate terminal of the source terminal of PMOS transistor M21 is connected to reference potential; The output of NAND gate K2 is connected to the gate terminal of nmos pass transistor M23 behind inverter I5, the source electrode termination reference potential of nmos pass transistor M23, the source terminal of the drain electrode termination nmos pass transistor M22 of nmos pass transistor M23 and the input of input buffer (2), the grid termination voltage source V CCO of nmos pass transistor M22; Interface circuit is a transmission mode when mode control signal TS=1; interface circuit carries out data output; interface circuit is a receiving mode when mode control signal TS=0; interface circuit output high resistant signal; external input signal is through input buffer (2) input interface circuit; it is characterized in that: also comprise gate protection circuit (3) in the interface circuit; the gate terminal of gate protection circuit control PMOS transistor M21, damage voltage source V CCO when preventing that voltage when interface circuit I/O end is higher than the voltage of voltage source V CCO.
But 2, the interface circuit of a kind of tolerating high voltage input according to claim 1, it is characterized in that: described gate protection circuit (3) comprises that PMOS transistor M15, median voltage generation circuit and pulse produce circuit, the gate terminal of PMOS transistor M15 drain electrode termination PMOS transistor M21, the drain electrode end of PMOS transistor M15 source electrode termination nmos pass transistor M22; The median voltage generation circuit produces one and is higher than reference potential and is lower than the median voltage of voltage source V CCO voltage and acts on the gate terminal of PMOS transistor M15, makes the drain electrode end of PMOS transistor M15 provide the identical voltage of holding with interface circuit I/O of input voltage value for the gate terminal of PMOS transistor M21; When interface circuit changed receiving mode into by transmission mode, pulse produced the gate terminal that circuit produces a pulse signal and acts on PMOS transistor M15, the recovery time when improving mode switch.
But 3, the interface circuit of a kind of tolerating high voltage input according to claim 2, it is characterized in that: described median voltage generation circuit comprises nmos pass transistor M10, nmos pass transistor M11, nmos pass transistor M14 and PMOS transistor M12, PMOS transistor M13; The gate terminal of nmos pass transistor M10 and drain electrode end are connected to voltage source V CCO simultaneously, the drain electrode end of source electrode termination nmos pass transistor M11; The gate terminal of nmos pass transistor M11 and drain electrode end are connected to the source terminal of nmos pass transistor M10 simultaneously, and source terminal connects the output of gate terminal, PMOS transistor M12 source terminal and the pulse generation circuit of PMOS transistor M15 simultaneously; The gate terminal of PMOS transistor M12 and drain electrode end are connected to the source terminal of PMOS transistor M13 simultaneously; The gate terminal of PMOS transistor M13 and drain electrode end are connected to the drain electrode end of nmos pass transistor M14 simultaneously; The source electrode termination reference potential of nmos pass transistor M14, gate terminal is by the inverted signal TS1 control of mode control signal TS.
But 4, according to the interface circuit of claim 2 or 3 described a kind of tolerating high voltage inputs, it is characterized in that: described pulse produces circuit and comprises PMOS transistor M8, nmos pass transistor M9, inverter I1, inverter I2, inverter I3, inverter I4 and NOR gate N1; The input termination mode control signal TS of inverter I1, output are connected to the gate terminal of PMOS transistor M8 and the input of inverter I2 and inverter I3 simultaneously; The output of inverter I3 is connected to the input of inverter I4, and the output of inverter I2 and inverter I4 is connected to two inputs of NOR gate N1 respectively, the gate terminal of the output control nmos pass transistor M9 of NOR gate N1; The source electrode termination voltage source V CCO of PMOS transistor M8, drain electrode end link to each other with the drain electrode end of nmos pass transistor M9 and produce the output of circuit, the source electrode termination reference potential of nmos pass transistor M9 as pulse.
5, but interface circuit according to claim 1 or 2 or 3 described a kind of tolerating high voltage inputs, it is characterized in that: also comprise N trap biasing circuit in the described interface circuit, when interface circuit is operated in transmission mode, described N trap biasing circuit provides the bias voltage identical with voltage source V CCO for PMOS transistor M20 with the residing N trap of PMOS transistor M21, when interface circuit is operated in receiving mode, if the input voltage of interface circuit I/O end is higher than the voltage of voltage source V CCO, described N trap biasing circuit provides the identical bias voltage of holding with interface circuit I/O of input voltage for PMOS transistor M20 with the residing N trap of PMOS transistor M21.
But 6, the interface circuit of a kind of tolerating high voltage input according to claim 5, it is characterized in that: described N trap biasing circuit comprises PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, the source terminal of PMOS transistor M5 links to each other with voltage source V CCO, the drain electrode end of PMOS transistor M5 links to each other with its residing N trap and is connected on PMOS transistor M20 and the residing N trap of the PMOS transistor M21 N_WELL, and the gate terminal of PMOS transistor M5 is connected to mode control signal TS; The source terminal of PMOS transistor M1 and PMOS transistor M2 all is connected to voltage source V CCO, and drain electrode end and residing N trap all are connected to N_WELL, and the gate terminal of PMOS transistor M1 is connected to the I/O end of interface circuit, and the gate terminal of PMOS transistor M2 is connected to N_WELL; The drain electrode end of PMOS transistor M3 and PMOS transistor M4 all is connected to the I/O end of interface circuit, and source terminal and residing N trap all are connected to N_WELL, the grid termination voltage source V CCO of PMOS transistor M3, and the gate terminal of PMOS transistor M4 is connected to N_WELL.
But 7, the interface circuit of a kind of tolerating high voltage input according to claim 6, it is characterized in that: also be connected with trap bias drive circuit (6) between the gate terminal of described PMOS transistor M5 and the mode control signal TS, for N trap biasing circuit provides drive signal, trap bias drive circuit (6) comprises nmos pass transistor M6 and nmos pass transistor M7 to described trap bias drive circuit (6) when transmission mode; The grid termination mode control signal TS of nmos pass transistor M6, source electrode termination reference potential, the source terminal of drain electrode termination nmos pass transistor M7; The grid termination voltage source V CCO of nmos pass transistor M7, the gate terminal of drain electrode termination PMOS transistor M5.
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| CNA2009100844485A CN101552605A (en) | 2009-05-19 | 2009-05-19 | An interface circuit capable of tolerating high voltage input |
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| CN103268133A (en) * | 2013-04-18 | 2013-08-28 | 北京大学 | Multi-working-voltage input-output pin unit circuit |
| CN103713678A (en) * | 2012-09-28 | 2014-04-09 | 富士通半导体股份有限公司 | Protection circuit, interface circuit, and communication system |
| CN104467799A (en) * | 2013-09-12 | 2015-03-25 | 珠海全志科技股份有限公司 | Input/output circuit device |
| CN104660247A (en) * | 2015-03-10 | 2015-05-27 | 北京大恒图像视觉有限公司 | Two-way interface circuit |
| CN105515596A (en) * | 2014-10-10 | 2016-04-20 | 三星电子株式会社 | Receiver circuit and signal receiving method thereof |
| CN106374907A (en) * | 2015-07-21 | 2017-02-01 | 炬芯（珠海）科技有限公司 | Circuit employing push-pull output |
| CN106411311A (en) * | 2015-07-31 | 2017-02-15 | 旺宏电子股份有限公司 | Output circuit |
| CN106505988A (en) * | 2016-11-10 | 2017-03-15 | 中国电子科技集团公司第四十七研究所 | Configurable I based on FPGA/O voltage holding circuits |
| CN106528459A (en) * | 2016-11-16 | 2017-03-22 | 苏州华芯微电子股份有限公司 | IO conversion method and system for FPGA-based MCU emulator |
| CN106817122A (en) * | 2016-12-27 | 2017-06-09 | 芯原微电子(上海)有限公司 | A kind of input/output interface circuit for I/O supply voltages scope wide |
| CN112764451A (en) * | 2019-10-21 | 2021-05-07 | 圣邦微电子（北京）股份有限公司 | Protection circuit for improving withstand voltage of logic input port |
| CN116131840A (en) * | 2023-04-14 | 2023-05-16 | 芯动微电子科技(珠海)有限公司 | Dual-mode voltage-resistant output IO circuit |
-
2009
- 2009-05-19 CN CNA2009100844485A patent/CN101552605A/en active Pending
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| CN103713678B (en) * | 2012-09-28 | 2016-04-27 | 株式会社索思未来 | protection circuit, interface circuit and communication system |
| US9520708B2 (en) | 2012-09-28 | 2016-12-13 | Socionext Inc. | Protection circuit, interface circuit, and communication system |
| CN103268133A (en) * | 2013-04-18 | 2013-08-28 | 北京大学 | Multi-working-voltage input-output pin unit circuit |
| CN104467799A (en) * | 2013-09-12 | 2015-03-25 | 珠海全志科技股份有限公司 | Input/output circuit device |
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| CN105515596B (en) * | 2014-10-10 | 2019-09-13 | 三星电子株式会社 | Acceptor circuit and its signal acceptance method |
| CN105515596A (en) * | 2014-10-10 | 2016-04-20 | 三星电子株式会社 | Receiver circuit and signal receiving method thereof |
| CN104660247A (en) * | 2015-03-10 | 2015-05-27 | 北京大恒图像视觉有限公司 | Two-way interface circuit |
| CN104660247B (en) * | 2015-03-10 | 2017-11-21 | 北京大恒图像视觉有限公司 | A kind of bidirectional interface circuit |
| CN106374907A (en) * | 2015-07-21 | 2017-02-01 | 炬芯（珠海）科技有限公司 | Circuit employing push-pull output |
| CN106374907B (en) * | 2015-07-21 | 2019-04-12 | 炬芯（珠海）科技有限公司 | A kind of circuit exported using push-pull type |
| CN106411311B (en) * | 2015-07-31 | 2019-10-01 | 旺宏电子股份有限公司 | Output circuit |
| CN106411311A (en) * | 2015-07-31 | 2017-02-15 | 旺宏电子股份有限公司 | Output circuit |
| CN106505988B (en) * | 2016-11-10 | 2019-06-04 | 中国电子科技集团公司第四十七研究所 | Configurable I based on FPGA/O voltage holding circuit |
| CN106505988A (en) * | 2016-11-10 | 2017-03-15 | 中国电子科技集团公司第四十七研究所 | Configurable I based on FPGA/O voltage holding circuits |
| CN106528459A (en) * | 2016-11-16 | 2017-03-22 | 苏州华芯微电子股份有限公司 | IO conversion method and system for FPGA-based MCU emulator |
| CN106817122A (en) * | 2016-12-27 | 2017-06-09 | 芯原微电子(上海)有限公司 | A kind of input/output interface circuit for I/O supply voltages scope wide |
| CN106817122B (en) * | 2016-12-27 | 2020-04-17 | 芯原微电子(上海)股份有限公司 | Input/output interface circuit for wide I/O power supply voltage range |
| CN112764451A (en) * | 2019-10-21 | 2021-05-07 | 圣邦微电子（北京）股份有限公司 | Protection circuit for improving withstand voltage of logic input port |
| CN116131840A (en) * | 2023-04-14 | 2023-05-16 | 芯动微电子科技(珠海)有限公司 | Dual-mode voltage-resistant output IO circuit |
| CN116131840B (en) * | 2023-04-14 | 2023-08-22 | 芯动微电子科技(珠海)有限公司 | Dual-mode voltage-resistant output IO circuit |
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Open date: 20091007 |