CN101533285A

CN101533285A - A reference voltage buffer circuit

Info

Publication number: CN101533285A
Application number: CN200910133602A
Authority: CN
Inventors: 黄洪伟
Original assignee: Actions Semiconductor Co Ltd
Current assignee: Ezchips Microeletronics Co ltd
Priority date: 2009-03-31
Filing date: 2009-03-31
Publication date: 2009-09-16
Anticipated expiration: 2029-03-31
Also published as: CN101533285B

Abstract

The present invention discloses a reference voltage buffer circuit, comprising a reference voltage generating circuit which generates and outputs a first primary voltage and a second primary voltage, and further comprising a driving buffer circuit and a deviation detecting circuit. The reference voltage buffer circuit provided by the embodiment of the present invention administers voltage adjustment to the given nodes of the driving buffer circuit through the deviation detecting circuit, realizing the adjustment and correction of the abnormal working state of a circuit, reliably solving the problem of reference voltage buffer circuit failing to work normally caused by production technique errors or other unpredictable factors, improving the production rate of standard quality of a circuit, providing reference voltage of great driving capacity, and achieving lower cost and circuit power dissipation.

Description

A kind of reference voltage buffer circuit

Technical field

The present invention relates to the reference voltage technology, relate in particular to a kind of reference voltage buffer circuit.

Background technology

Reference voltage buffer circuit is a kind of circuit that strengthens the reference voltage driving force, and it is widely used in the various electronic equipments.For example, at analog-digital converter (Analog-Digital Converter, ADC)/digital analog converter (Digital-Analog Converter, DAC) in, need the conduct of a high reference voltage (VR+) and a low reference voltage (VR-) with reference to benchmark, ADC/DAC utilizes these two reference datas could realize conversion of signals.

Fig. 1 is a kind of structural drawing of reference voltage buffer circuit of routine, comprising: reference voltage generating circuit 110, first drives buffer circuit 120 and second and drives buffer circuit 130.

Reference voltage generating circuit 110 further comprises: operational amplifier A 3, P-type mos (P-type Metal Oxide Semiconductor, PMOS) transistor M5, resistance R 1, resistance R 2 and current source CS5;

Wherein, the positive input terminal of operational amplifier A 3 connects an end of resistance R 1 and resistance R 2 respectively, and negative input end connects the fixed voltage Vcom of outside input, and output terminal connects grid (G) utmost point of PMOS pipe M5; Source (S) utmost point of PMOS pipe M5 is connected to power supply (VDD), and leakage (D) utmost point of PMOS pipe M5 is connected to the other end of resistance R 1, and the other end of resistance R 2 is then by current source CS5 ground connection;

By these circuit components in the reference voltage generating circuit 110, this reference voltage generating circuit can produce reference voltage first initial voltage (Vtop) at the common port (being the D utmost point of PMOS pipe) of PMOS pipe and resistance R 1, and produce reference voltage second initial voltage (Vbottom) at the common port of resistance R 2 and current source CS5, operating characteristic according to operational amplifier can be obtained: Vtop=Vcom+I5 * R1, Vbottom=Vcom-I5 * R2.Because this master reference voltage first initial voltage and the second initial voltage driving force that obtain this moment are very weak, and be not suitable for practical application, therefore need utilize first to drive buffer circuit 120 and second and drive the driving force that buffer circuit 130 strengthens described original reference voltage respectively.

First drives buffer circuit 120 comprises: first voltage buffer circuit 121 and first drives amplifying circuit 122;

Wherein, first voltage buffer circuit 121 further comprises: operational amplifier A 1, PMOS pipe M1 and current source CS1, and the positive input terminal of operational amplifier A 1 is connected to the D utmost point of PMOS pipe M5, the S utmost point that negative input end is connected to PMOS pipe M1 (is a node 2, if represent the voltage at port 2 places with V2, Hereinafter the same), output terminal then is connected to the G utmost point of PMOS pipe M1; Power supply is connected to the S utmost point of PMOS pipe M1 by current source CS1; The D utmost point of PMOS pipe M1 is connected to node A; Then obtain V2=Vtop easily.

First drives amplifying circuit 122 further comprises: current source CS2 and PMOS pipe M2; The S utmost point of PMOS pipe M2 is connected to power supply by current source CS2, and the G utmost point links to each other with the output terminal of operational amplifier A 1, and the D utmost point then is connected to Node B.Under perfect condition, (the wide ditch with gate circuit compares expression to the size of managing M2 as the electric current I 2 and the PMOS of current source CS2 generation, the size of M2 promptly is expressed as W2/L2), electric current I 1 that produces with respect to current source CS1 and the size (W1/L1) of PMOS pipe M1 are that equal proportion is when amplifying, (n is called enlargement factor when being I2/I1=(W2/L2)/(W1/L1)=n, usually n=10 in actual applications), at this moment, first drives the S utmost point output voltage V R+ of amplifying circuit 122 at PMOS pipe M2, can draw VR+=V2=Vtop, at this moment, the driving force of output voltage first initial voltage has obtained to strengthen widely.

It is corresponding that second circuit structure and first that drives buffer circuit 130 drives buffer circuit 120, comprises that second voltage buffer circuit 131 and second drives amplifying circuit 132;

Wherein, second voltage buffer circuit 131 further comprises: operational amplifier A 2, NMOS pipe M3 and current source CS3, and the positive input terminal of operational amplifier A 2 is connected to the input end of current source CS5, negative input end is connected to the S utmost point (being node 1) of NMOS pipe M3, and output terminal then is connected to the G utmost point of NMOS pipe M3; The D utmost point of NMOS pipe M3 is connected to node A, and its S utmost point is by current source CS3 ground connection; Obtain V1=Vbottom easily.

Second drives amplifying circuit 132 further comprises: current source CS4 and NMOS pipe M4; The D utmost point of NMOS pipe M4 is connected to Node B, and the G utmost point links to each other with the output terminal of operational amplifier A 2, and the S utmost point is then by current source CS4 ground connection.When the electric current I 4 of current source CS4 generation and the size of PMOS pipe M4, electric current I 3 that produces with respect to current source CS3 and the size of PMOS pipe M3 are that equal proportion is when amplifying, during I4/I3=(W4/L4)/(W3/L3)=n, second drives in the amplifying circuit 132, VR-=V1=Vbottom, thereby the driving force of output voltage second initial voltage has obtained to strengthen widely equally.

Further, as the PMOS of this circuit pipe M1, M2, and the equal operate as normal of NMOS pipe M3, M4 is when above-mentioned duty, can draw I1=I3 and I2=I4 by Fig. 1, because the first driving buffer circuit 120 and second drives buffer circuit 130 structural symmetry, know VA=VB=VDD/2 easily by inference simultaneously, simultaneously predefined input voltage Vcom=VDD/2, thereby can get VA=VB=Vcom.

As seen, when current source CS1 identical with the output current of CS3, current source CS2 is identical with the output current of CS4, and when the proportionate relationship on the proportionate relationship between I1 and the I2 and PMOS pipe M1 and M2/NMOS pipe M3 and the M4 size was identical, described circuit can be exported two reference voltage V R+ and VR-that driving force is very strong.

Yet in actual applications, because the integrated circuit production technology always exists certain deviation, PMOS pipe and NMOS pipe that actual production is come out can not be identical with design size, also be difficult between a plurality of current sources simultaneously guarantee that output current ratio identical or electric current meets the proportion requirement of setting fully, therefore, circuit shown in Figure 1 is difficult to guarantee I1=I3 and I2=I4 under most situations of practical application.

If I1〉I3 and I2〉I4, then VA and VB will constantly raise, and enter off state up to M1 and M2, cause VR+ ≠ V2 ≠ Vtop; If I1＜I3 and I2＜I4, VA and VB constantly descend, and enter off state up to M3 and M4, cause VR-≠ V1 ≠ Vbottom.As seen, reference voltage buffer circuit shown in Figure 1 in actual applications substantially can't operate as normal, and yields and practicality that circuit is produced are all very low.

Figure 2 shows that a kind of reference voltage buffer circuit that U.S. Pat 2007/00900860 proposes, it can solve the problem that conventional reference voltage buffer circuit shown in Figure 1 exists to a certain extent.This circuit form structure and reference voltage buffer circuit shown in Figure 1 basic identical, unique difference is that this patent has increased by two buffer circuit B1 and B2 on the basis of reference voltage buffer circuit shown in Figure 1, come the voltage at stable node A and B place by B1 and B2.If I1〉I3, I2〉during I4, B1 and B2 provide pull-down current Ib1=I1-I3 and Ib2=I2-I4 respectively, make node A, B place electric current conservation, thus VA, VB voltage are stable at VDD/2; If I1＜I3, I2＜and during I4, B1 and B2 then provide pull-up current Ib1=I3-I1 and Ib2=I4-I2 respectively, make node A, B place electric current conservation equally, thus VA, VB voltage are stable at VDD/2, the operate as normal of assurance entire circuit.

Though circuit shown in Figure 2 can improve the duty of conventional reference voltage buffer circuit to a certain extent, improve the stability of circuit, still there is following shortcoming in this circuit:

The first, this circuit needs two buffer circuit B1 and B2, and B1 and B2 need possess the ability of pull-down current and pull-up current simultaneously, and it is complicated that this just makes its circuit realize, not only power consumption is big but also cost is high;

The second, the production technology deviation of ifs circuit element is bigger, and the current deviation of I2 and I4 exceeds the compensation ability of B1 and B2, and the voltage at node A and B place just can't be stablized, thereby the circuit yields that still can cause producing reduces.

Summary of the invention

The embodiment of the invention provides a kind of reference voltage buffer circuit, and stably output reference voltage and power consumption and cost are lower.

For achieving the above object, technical scheme of the present invention specifically is achieved in that

A kind of reference voltage buffer circuit comprises the reference voltage generating circuit that produces and export first initial voltage and second initial voltage, and this circuit also further comprises: drive buffer circuit and deviation detection circuit;

Described driving buffer circuit, be used for that self circuit is set the voltages at nodes value and output to deviation detection circuit, when described magnitude of voltage leaves the rising of steady operation point, receive the Compensation Regulation signal that makes described magnitude of voltage reduce that deviation detection circuit returns, return to described steady operation point up to described magnitude of voltage; When described magnitude of voltage leaves the reduction of steady operation point, receive the Compensation Regulation signal that makes described magnitude of voltage raise that deviation detection circuit returns, return to described steady operation point up to described magnitude of voltage; Also the driving force of first initial voltage and second initial voltage being strengthened the back exports respectively as positive and negative reference voltage;

Described deviation detection circuit, be used for comparing with the outside reference voltage of presetting with driving buffer circuit setting voltages at nodes value, when described magnitude of voltage during, equate with outside reference voltage up to described magnitude of voltage to driving the Compensation Regulation signal that buffer circuit output makes described magnitude of voltage reduce greater than described outside reference voltage; When described magnitude of voltage during, equate with outside reference voltage up to described magnitude of voltage to driving the Compensation Regulation signal that buffer circuit output makes described magnitude of voltage raise less than described outside reference voltage.

As seen from the above technical solutions, the reference voltage buffer circuit that the embodiment of the invention provides, setting node place carries out voltage-regulation in the buffer circuit to driving by deviation detection circuit, can realize the adjusting of circuit abnormal operating state is proofreaied and correct, solved the problem that the reference voltage buffer circuit that causes owing to production technology deviation or other unpredictable reasons can't operate as normal reliably, improved the production yields of circuit, can provide driving force very big reference voltage, and realize that cost and circuit power consumption are lower.

Description of drawings

Fig. 1 is the circuit diagram of conventional reference voltage buffer circuit in the prior art.

Fig. 2 is the circuit diagram of the reference voltage buffer circuit after improving in the prior art.

The structured flowchart of the reference voltage buffer circuit that Fig. 3 provides for the embodiment of the invention.

The circuit diagram of the reference voltage buffer circuit that Fig. 4 provides for the embodiment of the invention one.

The circuit diagram of the reference voltage buffer circuit that Fig. 5 provides for the embodiment of the invention two.

The circuit diagram of the reference voltage buffer circuit that Fig. 6 provides for the embodiment of the invention three.

The circuit diagram of the reference voltage buffer circuit that Fig. 7 provides for the embodiment of the invention four.

The circuit diagram of the reference voltage buffer circuit that Fig. 8 provides for the embodiment of the invention five.

The circuit diagram of the reference voltage buffer circuit that Fig. 9 provides for the embodiment of the invention six.

Figure 10 is the electrical block diagram of first kind of Voltage-controlled Current Source in the embodiment of the invention.

Figure 11 is the electrical block diagram of second kind of Voltage-controlled Current Source in the embodiment of the invention.

Figure 12 is the composition structural representation of deviation detection circuit in the embodiment of the invention.

Embodiment

For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.

The embodiment of the invention provides a kind of reference voltage buffer circuit, structure as shown in Figure 3, comprising: reference voltage generating circuit 110, drive buffer circuit 320 and deviation detection circuit 330;

Described reference voltage generating circuit 110 is used for producing and exporting first initial voltage and second initial voltage, and it specifically forms in structure and the background technology identical, repeats no more.

Described driving buffer circuit 320, be used for that self circuit is set the voltages at nodes value and output to deviation detection circuit 330, when described magnitude of voltage leaves the rising of steady operation point, receive the Compensation Regulation signal that makes described magnitude of voltage reduce that deviation detection circuit 330 returns, return to described steady operation point up to described magnitude of voltage; When described magnitude of voltage leaves the reduction of steady operation point, receive the Compensation Regulation signal that makes described magnitude of voltage raise that deviation detection circuit 330 returns, return to described steady operation point up to described magnitude of voltage; Also the driving force of first initial voltage and second initial voltage being strengthened the back exports respectively as positive and negative reference voltage;

Described deviation detection circuit 330, be used for comparing with the outside reference voltage of presetting with driving buffer circuit 320 setting voltages at nodes values, when described magnitude of voltage during, equate with outside reference voltage up to described magnitude of voltage to driving the Compensation Regulation signal that buffer circuit 320 outputs make described magnitude of voltage reduce greater than described outside reference voltage; When described magnitude of voltage during, equate with outside reference voltage up to described magnitude of voltage to driving the Compensation Regulation signal that buffer circuit 320 outputs make described magnitude of voltage raise less than described outside reference voltage.

Embodiment one

The composition structure of a kind of reference voltage buffer circuit provided by the invention comprises as shown in Figure 4: reference voltage generating circuit 110, driving buffer circuit 320 and deviation detection circuit 330;

Wherein, described reference voltage generating circuit 110 is the reference voltage generating circuit 110 among Fig. 1; Described reference voltage generating circuit 110, common port (being the D utmost point of PMOS pipe) in PMOS pipe and resistance R 1 produces reference voltage first initial voltage, and producing reference voltage second initial voltage at the common port of resistance R 2 and current source CS3, described reference voltage first initial voltage and second initial voltage are further provided to driving buffer circuit 320.

Among 320 of described driving buffer circuits and Fig. 1 first drives buffer circuit 120 and second, and to drive the combination of buffer circuit 130 basic identical, and difference only is following 2 points:

1) in Fig. 4, the embodiment of the invention replaces with Voltage-controlled Current Source VCCS1 with current source CS3 among Fig. 1, current source CS4 among Fig. 1 is replaced with Voltage-controlled Current Source VCCS2, the control end of described Voltage-controlled Current Source VCCS1 and VCCS2 links to each other, and be connected to the output terminal of deviation detection circuit 330 jointly, that is, the output current of described VCCS1 and VCCS2 is by the output voltage control of deviation detection circuit 330;

2) in Fig. 4, the embodiment of the invention is connected the node A among Fig. 1 with B, and is connected to the positive input terminal of described deviation detection circuit 330 jointly---and the magnitude of voltage that is about to described node A and B place outputs to deviation detection circuit 330.

Described deviation detection circuit 330 is circuit units that the embodiment of the invention increases newly, comprises positive input terminal, negative input end and 3 ports of output terminal altogether; Wherein, positive input terminal links to each other with B with node A, and negative input end connects the reference voltage V b of outside input, and output terminal then links to each other with the control end of Voltage-controlled Current Source VCCS1 and VCCS2.When the positive input terminal voltage of deviation detection circuit 330 during greater than negative input end voltage, the voltage of output terminal rises; When the positive input terminal voltage of deviation detection circuit 330 during less than negative input end voltage, the voltage of output terminal descends; When the positive input terminal voltage of deviation detection circuit 330 equaled negative input end voltage, the voltage of output terminal remained unchanged.

For clear and definite foregoing circuit structure realizes reference voltage output and strengthens the principle of work of described reference voltage driving force, be elaborated below in conjunction with the actual working state of circuit:

One,

According to background technology description partly as can be known, when driving buffer circuit 320 operate as normal, the electric current I 4 that electric current I 3 that the electric current I 2 that the electric current I 1 that current source CS1 produces, current source CS2 produce, Voltage-controlled Current Source VCCS1 produce and Voltage-controlled Current Source VCCS2 produce satisfies I1+I2=I3+I4---promptly, the electric current that flows into node A equals to flow out the electric current of node A, the electric current conservation of node A, and node voltage VA=VDD/2 simultaneously, preestablishes input voltage Vb=Vcom=VDD/2.

As seen, when driving buffer circuit 320 operate as normal, the equal operate as normal of metal-oxide-semiconductor M1, M2, M3 and M4 is in the saturation region, and operational amplifier A 1, metal-oxide-semiconductor M1 and current source CS1 form negative-feedback circuit, at this moment, and V2=Vtop; Again since metal-oxide-semiconductor M2 and current source CS2 can the equal proportion amplifying circuit driving force, therefore, VR+=V2=Vtop, and the driving force of VR+ is strengthened greatly;

Similarly, operational amplifier A 2, metal-oxide-semiconductor M3 and Voltage-controlled Current Source VCCS1 form negative-feedback circuit, thus V1=Vbottom; Again since metal-oxide-semiconductor M4 and Voltage-controlled Current Source VCCS2 can the equal proportion amplifying circuit driving force, therefore, VR-=V1=Vbottom.

The input voltage of the positive and negative input end of deviation detection circuit 330 all equals Vb, therefore the output voltage V ct of output terminal is constant---and the control voltage that is Voltage-controlled Current Source VCCS1 and VCCS2 is constant, thereby electric current I 3 and I4 just can not change yet, and entire circuit maintains normal operating conditions.

Two,

If owing to production technology exists deviation or unpredictable reason, I1+I2 ≠ I3+I4 after circuit is started working then correspondingly exists two kinds of possibility: I1+I2〉I3+I4, or I1+I2＜I3+I4.

A) if I1+I2〉I3+I4

At this moment, the electric current that flows into node A is greater than the electric current that flows out node A, thereby node voltage VA will be drawn high and move closer in power supply voltage VDD.Deviation detection circuit 330 detects the voltage Vb of its positive input terminal voltage greater than negative input end, therefore the output end voltage Vct of deviation detection circuit 330 rises, correspondingly risen by the Voltage-controlled Current Source VCCS1 of Vct control and output current I3 and the I4 of VCCS2, thereby the electric current that flows out node A increases gradually, and the value of voltage VA reduces gradually;

When node voltage VA is reduced to when equaling Vb, voltage Vct no longer rises, thereby I3 and I4 also stop to increase, at this moment, the electric current that flows into node A equal to flow out node A electric current---be I1+I2=I3+I4, described driving buffer circuit 320 enters normal operating conditions.

B) if I1+I2＜I3+I4

At this moment, the electric current that flows into node A is less than the electric current that flows out node A, and node voltage VA descends and moves closer in ground connection.Deviation detection circuit 330 detects the voltage Vb of its positive input terminal voltage less than negative input end, therefore the output end voltage Vct of deviation detection circuit 330 descends, correspondingly descended by the Voltage-controlled Current Source VCCS1 of Vct control and output current I3 and the I4 of VCCS2, thereby the electric current that flows out node A reduces gradually, and the value of voltage VA raises gradually;

When node voltage VA is elevated to when equaling Vb, voltage Vct no longer descends, thereby I3 and I4 also stop to reduce, at this moment, the electric current that flows into node A equal to flow out node A electric current---be I1+I2=I3+I4, described driving buffer circuit 320 enters normal operating conditions.

Therefore, deviation detection circuit 330 is by the variation of the node voltage VA that detects current deviation and cause, can correspondingly change the output current of Voltage-controlled Current Source VCCS1 and VCCS2, make the electric current at node A place realize conservation by regulating described output current, guarantee that circuit can return to normal operating conditions.

Embodiment two

The present invention also provides the another kind of possible embodiment of described reference voltage buffer circuit, and its circuit structure comprises reference voltage generating circuit 110, drives buffer circuit 420 and deviation detection circuit 330 as shown in Figure 5;

Wherein, reference voltage generating circuit 110 and deviation detection circuit 330 are identical with first embodiment shown in Figure 4, no longer describe in detail;

Drive buffer circuit 420, its circuit is formed structure than embodiment shown in Figure 4, and difference only is:

1) in Fig. 5, present embodiment replaces with current source CS1 with the Voltage-controlled Current Source VCCS1 among Fig. 4, and the Voltage-controlled Current Source VCCS2 among Fig. 4 is replaced with current source CS2;

2) in Fig. 5, present embodiment replaces with Voltage-controlled Current Source VCCS1 with the current source CS1 among Fig. 4, and the current source CS2 among Fig. 4 is replaced with Voltage-controlled Current Source VCCS2; The control end of Voltage-controlled Current Source VCCS1 and VCCS2 links to each other, and is connected to the output terminal of deviation detection circuit 330 jointly, that is, the output current of described VCCS1 and VCCS2 (being I1 and I2) is by the output voltage control of deviation detection circuit 330.

At this moment, the magnitude of voltage that remains described node A and B place outputs to deviation detection circuit 330, circuit structure shown in the present embodiment is realized reference voltage output and strengthens the principle of work and first embodiment of described reference voltage driving force similar, so no longer elaborate, it is as follows only to make simple analysis:

If owing to production technology exists deviation or unpredictable reason, the circuit back I1+I2 ≠ I3+I4 that starts working after then there is deviation in the deviation detection circuit 330 voltage Vb that detects its positive input terminal voltage and negative input end, correspondingly changes its output voltage V ct; Its process is similarly: when described deviation detection circuit 330 detected its positive input terminal voltage greater than negative input end voltage Vb, output voltage V ct raise; When deviation detection circuit 330 detected its positive input terminal voltage less than negative input end voltage Vb, output voltage V ct descended; And when deviation detection circuit 330 detected its positive input terminal voltage and equates with negative input end voltage Vb, output voltage V ct remained unchanged.

The variation of Vct correspondingly changes the output current of Voltage-controlled Current Source VCCS1 and VCCS2, and but, different with first embodiment is:

A) if I1+I2〉I3+I4

At this moment, the electric current that flows into node A is greater than the electric current that flows out node A, thereby node voltage VA will be drawn high and move closer in power supply voltage VDD.Deviation detection circuit 330 detects the voltage Vb of its positive input terminal voltage greater than negative input end, therefore the output end voltage Vct of deviation detection circuit 330 rises, opposite with first embodiment, correspondingly reduced by the Voltage-controlled Current Source VCCS1 of Vct control and output current I1 and the I2 of VCCS2, thereby the electric current that flows into node A reduces gradually, and the value of voltage VA reduces gradually;

When node voltage VA is reduced to when equaling Vb, voltage Vct no longer rises, thereby I1 and I2 also stop to reduce, correspondingly, the electric current that flows into node A equals to flow out the electric current of node A---and be I1+I2=I3+I4, described driving buffer circuit 320 enters normal operating conditions, thereby guarantees that circuit returns to normal operating conditions, and generates correct reference voltage V R+ and VR-.

B) if I1+I2＜I3+I4

At this moment, the electric current that flows into node A is less than the electric current that flows out node A, and node voltage VA descends and moves closer in ground connection.Deviation detection circuit 330 detects the voltage Vb of its positive input terminal voltage less than negative input end, therefore the output end voltage Vct of deviation detection circuit 330 descends, opposite with first embodiment, correspondingly increased by the Voltage-controlled Current Source VCCS1 of Vct control and output current I1 and the I2 of VCCS2, thereby the electric current that flows into node A increases gradually, and the value of voltage VA raises gradually;

When node voltage VA is elevated to when equaling Vb, voltage Vct no longer descends, thereby I1 and I2 also stop to increase, correspondingly, the electric current that flows into node A equals to flow out the electric current of node A---and be I1+I2=I3+I4, described driving buffer circuit 320 enters normal operating conditions, thereby guarantees that circuit returns to normal operating conditions, and generates correct reference voltage V R+ and VR-.

It is pointed out that described first embodiment and second embodiment, still is giving an example of embodiment of the present invention, do not represent the qualification for embodiment of the present invention, in fact, the present invention can also be out of shape and adjust, can realize same effect equally, mainly comprise:

Embodiment three

Deviation detection circuit 330 in the foregoing description, can also realize jointly by two identical circuit of 26S Proteasome Structure and Function, as shown in Figure 6, comprise reference voltage generating circuit 110, driving buffer circuit 320, first deviation detection circuit 531 and second deviation detection circuit 532;

Wherein, reference voltage generating circuit 110 is identical with first embodiment shown in Figure 4 with driving buffer circuit 320, no longer describes in detail; First deviation detection circuit 531 and second deviation detection circuit 532, each is all identical with described deviation detection circuit 330 among first embodiment respectively, and its circuit is formed structure than embodiment shown in Figure 4, and difference only is:

In Fig. 6, present embodiment disconnects node A among Fig. 4 and B, and is connected respectively to first deviation detection circuit 531 and second deviation detection circuit 532; Described first deviation detection circuit 531, second deviation detection circuit 532 are all identical with described deviation detection circuit 330; At this moment, the magnitude of voltage at described node A place is outputed to first deviation detection circuit 531, and the magnitude of voltage at Node B place is outputed to second deviation detection circuit 532.

Node A is connected to the positive input terminal of first deviation detection circuit 531, the control end of Voltage-controlled Current Source VCCS1 is connected to the output terminal of described first deviation detection circuit 531, that is, the output current I3 of described VCCS1 is by the output voltage V ct1 control of first deviation detection circuit 531;

Similarly, Node B is connected to the positive input terminal of second deviation detection circuit 532, the control end of Voltage-controlled Current Source VCCS2 is connected to the output terminal of described second deviation detection circuit 532, that is, the output current I4 of described VCCS2 is by the output voltage V ct2 control of second deviation detection circuit 532.

At this moment, in the circuit setting of each parameter all identical with aforementioned each embodiment, reach hereinafter herein and all repeat no more.

Embodiment four

Similar with embodiment three, described deviation detection circuit 330 described in Fig. 5, can substitute with two identical with it circuit of 26S Proteasome Structure and Function equally, as shown in Figure 7, comprise reference voltage generating circuit 110, driving buffer circuit 420, first deviation detection circuit 631 and second deviation detection circuit 632;

Wherein, reference voltage generating circuit 110 is identical with second embodiment shown in Figure 5 with driving buffer circuit 420, no longer describes in detail; First deviation detection circuit 631 and second deviation detection circuit 632, each is all identical with described deviation detection circuit 330 among first embodiment respectively.The circuit of present embodiment is formed structure than embodiment shown in Figure 5, and difference only is:

In Fig. 7, present embodiment disconnects node A among Fig. 5 and B, and is connected respectively to first deviation detection circuit 631 and second deviation detection circuit 632; Described first, second deviation detection circuit is all identical with described deviation detection circuit 330; At this moment, the magnitude of voltage at described node A place is outputed to first deviation detection circuit 631, and the magnitude of voltage at Node B place is outputed to second deviation detection circuit 632.

Node A is connected to the positive input terminal of first deviation detection circuit 631, the control end of Voltage-controlled Current Source VCCS1 is connected to the output terminal of described first deviation detection circuit 631, that is, the output current I1 of described VCCS1 is by the output voltage V ct1 control of first deviation detection circuit 631;

Similarly, Node B is connected to the positive input terminal of second deviation detection circuit 632, the control end of Voltage-controlled Current Source VCCS2 is connected to the output terminal of described second deviation detection circuit 632, that is, the output current I2 of described VCCS2 is by the output voltage V ct2 control of second deviation detection circuit 632.

Embodiment five

Further, the present invention also provides a kind of possible embodiment of described reference voltage buffer circuit, as shown in Figure 8, comprises reference voltage generating circuit 110, drives buffer circuit 720, first deviation detection circuit 531 and second deviation detection circuit 532;

Wherein, reference voltage generating circuit 110, first deviation detection circuit 531 and second deviation detection circuit 532 are identical with the 3rd embodiment shown in Figure 6, no longer describe in detail.The circuit of present embodiment is formed structure than embodiment shown in Figure 6, and difference only is:

In Fig. 8, the embodiment of the invention replaces with current source CS2 with the Voltage-controlled Current Source VCCS2 among Fig. 6, current source CS2 among Fig. 6 is replaced with Voltage-controlled Current Source VCCS2, the control end of described Voltage-controlled Current Source VCCS2 is connected to the output terminal of second deviation detection circuit 532, that is, the output current I2 of described VCCS2 is by the output voltage V ct2 control of second deviation detection circuit 532.

At this moment, the magnitude of voltage at described node A place is outputed to first deviation detection circuit 531, and the magnitude of voltage at Node B place is outputed to second deviation detection circuit 532.

Embodiment six

Perhaps, similar with embodiment five, the present invention also provides the another kind of possible embodiment of described reference voltage buffer circuit, as shown in Figure 9, comprises reference voltage generating circuit 110, drives buffer circuit 820, first deviation detection circuit 531 and second deviation detection circuit 532;

In Fig. 9, the embodiment of the invention replaces with current source CS1 with the Voltage-controlled Current Source VCCS1 among Fig. 6, current source CS1 among Fig. 6 is replaced with Voltage-controlled Current Source VCCS1, the control end of described Voltage-controlled Current Source VCCS1 is connected to the output terminal of first deviation detection circuit 531, that is, the output current I1 of described VCCS1 is by the output voltage V ct1 control of first deviation detection circuit 531.

Those skilled in the art know described embodiment three to six by inference easily according to the analysis of the principle of work of previously described first and second embodiment, can realize the effect identical with first and second embodiment.

Described Voltage-controlled Current Source can have multiple implementation method, and Figure 10 and Figure 11 are wherein a kind of possible implementation.

Find easily, comprising two kinds of antipodal Voltage-controlled Current Source of the mode of action in the foregoing description: wherein, the same Voltage-controlled Current Source (Voltage-controlled Current Source of ground connection) that increases of output current can realize by NMOS pipe as shown in figure 10 along with the increase of control voltage; Voltage-controlled Current Source (Voltage-controlled Current Source that links to each other with power supply) that output current reduces gradually then can realize by PMOS pipe shown in Figure 11 along with the increase of control voltage, below detailed description respectively:

In Figure 10, described Voltage-controlled Current Source is made up of a NMOS pipe M6, wherein:

The D of NMOS pipe M6 is the input end of this Voltage-controlled Current Source very, and S is the output terminal of this Voltage-controlled Current Source very, and G is the control end of this Voltage-controlled Current Source very;

For example for first Voltage-controlled Current Source among first embodiment, corresponding, this moment, the G utmost point of NMOS pipe M6 linked to each other with the output terminal of deviation detection circuit, controlled by the output voltage V ct of described deviation detection circuit, and the D utmost point is connected to node 1 place, and S utmost point ground connection;

At this moment, the electric current that flows through NMOS pipe M6 satisfies I=K (Vct-Vt) ²Wherein K and Vt are the constant by the decision of NMOS pipe manufacturer technology, and (Vct-Vt) 0;

By following formula as seen, when voltage Vct rose, the electric current I that flows through NMOS pipe M6 became big, and when voltage Vct descended, the electric current I that flows through NMOS pipe M6 diminished.

Simultaneously, in order to distinguish the NMOS pipe of forming VCCS1 and VCCS2, correspondingly, one of them is called M6, another then is called M13.

In Figure 11, described Voltage-controlled Current Source is made up of a PMOS pipe M14, wherein:

The S of PMOS pipe M14 is the input end of this Voltage-controlled Current Source very, and D is the output terminal of this Voltage-controlled Current Source very, and G is the control end of this Voltage-controlled Current Source very;

For example for first Voltage-controlled Current Source among second embodiment, corresponding, this moment, the G utmost point of PMOS pipe M14 linked to each other with the output terminal of deviation detection circuit, controlled by the output voltage V ct of described deviation detection circuit, the D utmost point is connected to node 2 places, and the S utmost point is connected to power supply;

At this moment, the electric current that flows through PMOS pipe M14 satisfies I=K (VDD-Vct-Vt) ²Wherein K and Vt are the constant by the decision of PMOS pipe manufacturer technology, and (VDD-Vct-Vt) 0;

By following formula as seen, when voltage Vct rose, the electric current I that flows through PMOS pipe M14 diminished, and when voltage Vct descended, the electric current I that flows through PMOS pipe M14 became big.

Therefore, described PMOS pipe can be realized the function of described Voltage-controlled Current Source.

Similarly, in order to distinguish the PMOS pipe of forming VCCS1 and VCCS2, correspondingly, one of them is called M14, another then is called M15.

Need to prove, Figure 10 and Figure 11 are a kind of implementation of described Voltage-controlled Current Source, also comprise various other the implementations of Voltage-controlled Current Source in the prior art, the embodiment that these implementations and Figure 10, Figure 11 provide is enumerated in the middle of can being applied in the various embodiments of the present invention respectively as space is limited no longer one by one.

At last, described deviation detection circuit has multiple implementation method equally, for example can adopt operational amplifier or comparer to realize.As space is limited, only enumerate the implementation method of utilizing comparer herein, as shown in figure 12, comprising: current source CS4, PMOS pipe M7 and M8, NMOS manages M9;

Wherein, current source CS4 input termination power supply, output terminal connects the S utmost point of PMOS pipe M7 and M8; The G of PMOS pipe M7 is the positive input terminal of deviation detection circuit very, the D utmost point ground connection of described M7; The G of PMOS pipe M8 is the negative input end of deviation detection circuit very, be used to connect external input voltage Vb, the D utmost point of described M8 extremely links to each other with G with the D utmost point of NMOS pipe M9, the D utmost point of described M9 and the output terminal of drawing after G extremely links to each other as described deviation detection circuit, be used to produce the control voltage Vct of described Voltage-controlled Current Source, the S utmost point ground connection of described M9.

Circuit structure by above-mentioned deviation detection circuit is known by inference easily, and when its positive input terminal voltage during greater than negative input end voltage Vb, output voltage V ct rises; When positive input terminal voltage during less than negative input end voltage Vb, output voltage V ct descends.

Similarly, in order to distinguish the first and second deviation detecting units of forming among the embodiment, correspondingly, the current source of forming one of them is called CS4, each metal-oxide-semiconductor is called M7, M8 and M9; And the current source of forming another is called CS5, and each metal-oxide-semiconductor then is called M10, M11 and M12.Wherein M10 is corresponding to M7, and M11 is corresponding to M8, and M12 is corresponding to M9.

According to foregoing description, those skilled in the art can correspondingly obtain the annexation of each port of described Voltage-controlled Current Source and deviation detection circuit to realize the present invention, no longer the concrete connected mode of each embodiment are enumerated one by one at this.

By as seen above-mentioned, the reference voltage buffer circuit that the embodiment of the invention proposes, setting node place carries out voltage-regulation in the buffer circuit to driving by deviation detection circuit, can realize the circuit abnomal condition is regulated correction, thereby solved the problem that the reference voltage buffer circuit that causes owing to production technology deviation or other unpredictable reasons can't operate as normal reliably, improved the production yields of circuit, and very big reference voltage V R+ of driving force and VR-can be provided; Simultaneously, because described deviation detection circuit function is simple, therefore need to possess simultaneously the buffer circuit of pull-down current and pull-up current ability in the prior art, realization cost of the present invention and power consumption are all lower.

Claims

1, a kind of reference voltage buffer circuit comprises the reference voltage generating circuit that produces and export first initial voltage and second initial voltage, it is characterized in that this circuit also further comprises: drive buffer circuit and deviation detection circuit;

2, circuit according to claim 1 is characterized in that, described reference voltage generating circuit comprises: the 3rd operational amplifier (A3), the 5th PMOS manage (M5), first resistance (R1), second resistance (R2) and the 3rd current source (CS3); Export first initial voltage by the drain electrode of described the 5th PMOS pipe, export second initial voltage by the input end of described the 3rd current source;

The positive input terminal of described the 3rd operational amplifier connects the common port of first resistance and second resistance respectively, the negative input end of described the 3rd operational amplifier connects the fixed voltage of outside input, the output terminal of described the 3rd operational amplifier connects the grid of described the 5th PMOS pipe, the source electrode of described the 5th PMOS pipe is connected to power supply, the drain electrode of described the 5th PMOS pipe is connected to the other end of described first resistance, the other end of described second resistance is connected to the input end of described the 3rd current source, described the 3rd current source output head grounding.

3, circuit according to claim 2 is characterized in that, described driving buffer circuit comprises:

First operational amplifier (A1), second operational amplifier (A2), the one PMOS pipe (M1), the 2nd PMOS manage (M2), the 3rd NMOS pipe (M3), the 4th NMOS manage (M4), first current source (CS1), second current source (CS2) and first Voltage-controlled Current Source (VCCS1), second Voltage-controlled Current Source (VCCS2); Draw the positive output end of reference voltage buffer circuit by the output terminal of described second current source, draw the negative output terminal of reference voltage buffer circuit by the input end of described second Voltage-controlled Current Source;

The positive input terminal of described first operational amplifier connects first initial voltage of reference voltage generating circuit output, the negative input end of described first operational amplifier links to each other with the output terminal of described first current source, the output terminal of described first operational amplifier is managed with a PMOS, the grid of the 2nd PMOS pipe links to each other respectively, the input end of described first current source, second current source is connected to power supply respectively, the output terminal of described first current source links to each other with the source electrode of a described PMOS pipe, and the output terminal of described second current source is connected to the source electrode of described the 2nd PMOS pipe; Described PMOS pipe and the 3rd NMOS pipe common drain, the 2nd PMOS pipe and the 4th NMOS pipe common drain;

The positive input terminal of described second operational amplifier connects second initial voltage of reference voltage generating circuit output, the negative input end of described second operational amplifier links to each other with the source electrode of described the 3rd NMOS pipe, the output terminal of described second operational amplifier is managed with described the 3rd NMOS, the grid of the 4th NMOS pipe links to each other respectively, the input end of described first Voltage-controlled Current Source links to each other with the source electrode of described the 3rd NMOS pipe, and the described second Voltage-controlled Current Source input end links to each other with the source electrode of described the 4th NMOS pipe; Described first Voltage-controlled Current Source, the second Voltage-controlled Current Source output terminal be ground connection respectively;

Described deviation detection circuit, comprise positive and negative input end and an output terminal, PMOS pipe, the 2nd PMOS pipe, the 3rd NMOS pipe link to each other respectively with the drain electrode of the 4th NMOS pipe in the positive input terminal of described deviation detection circuit and the described driving buffer circuit, the negative input end of described deviation detection circuit connects the reference voltage of outside input, and the output terminal of described deviation detection circuit then links to each other respectively with the control end of described first Voltage-controlled Current Source, second Voltage-controlled Current Source; When the positive input terminal voltage of described deviation detection circuit during greater than negative input end voltage, the output end voltage of described deviation detection circuit rises; When the positive input terminal voltage of described deviation detection circuit during less than negative input end voltage, the output end voltage of described deviation detection circuit descends; When the positive input terminal voltage of described deviation detection circuit equaled negative input end voltage, the output end voltage of described deviation detection circuit remained unchanged.

4, circuit according to claim 3, it is characterized in that, described first Voltage-controlled Current Source comprises the 6th NMOS pipe (M6), the grid of described the 6th NMOS pipe is the control end of first Voltage-controlled Current Source, the drain electrode of described the 6th NMOS pipe is the input end of first Voltage-controlled Current Source, and the source electrode of described the 6th NMOS pipe is the output terminal of first Voltage-controlled Current Source;

Described second Voltage-controlled Current Source comprises the 13 NMOS pipe (M13), the grid of described the 13 NMOS pipe is the control end of second Voltage-controlled Current Source, the drain electrode of described the 13 NMOS pipe is the input end of second Voltage-controlled Current Source, and the source electrode of described the 13 NMOS pipe is the output terminal of second Voltage-controlled Current Source.

5, according to claim 3 or 4 described circuit, it is characterized in that described deviation detection circuit comprises: the 4th current source (CS4), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 9th NMOS pipe (M9);

The input end of described the 4th current source connects power supply, the output terminal of described the 4th current source and the 7th PMOS pipe, the source electrode of the 8th PMOS pipe links to each other respectively, the grounded drain of the 7th PMOS pipe, the grid of described the 7th PMOS pipe is the positive input terminal of described deviation detection circuit, the grid of the 8th PMOS pipe is the negative input end of described deviation detection circuit, the grid of described the 8th PMOS pipe is used to connect the reference voltage of default outside input, and the fixed voltage equal and opposite in direction imported of this voltage and the outside that negative input end was connected of the 3rd operational amplifier described in the reference voltage generating circuit; The drain electrode of the 8th PMOS pipe links to each other respectively with drain electrode, the grid of the 9th NMOS pipe, the source ground of described the 9th NMOS pipe, and the grid of described the 9th NMOS pipe is the output terminal of described deviation detection circuit.

6, circuit according to claim 2 is characterized in that, described driving buffer circuit comprises:

Described deviation detection circuit comprises the first deviation detecting unit and the second deviation detecting unit, and each unit all further comprises positive and negative input end and an output terminal; Wherein, the drain electrode of PMOS pipe, the 3rd NMOS pipe links to each other respectively in the positive input terminal of the described first deviation detecting unit and the described driving buffer circuit, and the output terminal of the described first deviation detecting unit links to each other with the control end of described first Voltage-controlled Current Source; The drain electrode of the 2nd PMOS pipe, the 4th NMOS pipe links to each other respectively in the positive input terminal of the described second deviation detecting unit and the described driving buffer circuit, and the output terminal of the described second deviation detecting unit links to each other with the control end of described second Voltage-controlled Current Source; The negative input end of described two unit connects the reference voltage of the identical outside input of size; To any described deviation detecting unit, when the positive input terminal voltage of described deviation detecting unit during greater than negative input end voltage, the output end voltage of described deviation detecting unit rises; When the positive input terminal voltage of described deviation detecting unit during less than negative input end voltage, the output end voltage of described deviation detecting unit descends; When the positive input terminal voltage of described deviation detecting unit equaled negative input end voltage, the output end voltage of described deviation detecting unit remained unchanged.

7, circuit according to claim 6, it is characterized in that, described first Voltage-controlled Current Source comprises the 6th NMOS pipe (M6), the grid of described the 6th NMOS pipe is the control end of first Voltage-controlled Current Source, the drain electrode of described the 6th NMOS pipe is the input end of first Voltage-controlled Current Source, and the source electrode of described the 6th NMOS pipe is the output terminal of first Voltage-controlled Current Source;

According to claim 6 or 7 described circuit, it is characterized in that 8, the described first deviation detecting unit comprises: the 4th current source (CS4), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 9th NMOS pipe (M9);

The input end of described the 4th current source connects power supply, the output terminal of described the 4th current source and the 7th PMOS pipe, the source electrode of the 8th PMOS pipe links to each other respectively, the grounded drain of the 7th PMOS pipe, the grid of described the 7th PMOS pipe is the positive input terminal of this deviation detecting unit, the grid of the 8th PMOS pipe is the negative input end of this deviation detecting unit, the grid of described the 8th PMOS pipe is used to connect the reference voltage of default outside input, and the fixed voltage equal and opposite in direction imported of this voltage and the outside that negative input end was connected of the 3rd operational amplifier described in the reference voltage generating circuit; The drain electrode of the 8th PMOS pipe links to each other respectively with drain electrode, the grid of the 9th NMOS pipe, the source ground of described the 9th NMOS pipe, and the grid of described the 9th NMOS pipe is the output terminal of this deviation detecting unit;

The described second deviation detecting unit comprises: the 5th current source (CS5), the tenth PMOS pipe (M10), the 11 PMOS pipe (M11) and the 12 NMOS pipe (M12);

The input end of described the 5th current source connects power supply, the output terminal of described the 5th current source and the tenth PMOS pipe, the source electrode of the 11 PMOS pipe links to each other respectively, the grounded drain of the tenth PMOS pipe, the grid of described the tenth PMOS pipe is the positive input terminal of this deviation detecting unit, the grid of the 8th PMOS pipe is the negative input end of this deviation detecting unit, the grid of described the 11 PMOS pipe is used to connect the reference voltage of default outside input, and the fixed voltage equal and opposite in direction imported of this voltage and the outside that negative input end was connected of the 3rd operational amplifier described in the reference voltage generating circuit; The drain electrode of the 11 PMOS pipe links to each other respectively with the drain electrode of the 12 NMOS pipe, grid, the source ground of described the 12 NMOS pipe, and the grid of described the 12 NMOS pipe is the output terminal of this deviation detecting unit.

9, circuit according to claim 2 is characterized in that, described driving buffer circuit comprises:

First operational amplifier (A1), second operational amplifier (A2), the one PMOS pipe (M1), the 2nd PMOS manage (M2), the 3rd NMOS pipe (M3), the 4th NMOS manage (M4), first Voltage-controlled Current Source (VCCS1), second Voltage-controlled Current Source (VCCS2) and first current source (CS1), second current source (CS2); Draw the positive output end of reference voltage buffer circuit by the described second Voltage-controlled Current Source output terminal, draw the negative output terminal of reference voltage buffer circuit by the described second current source input end;

The positive input terminal of described first operational amplifier connects first initial voltage of reference voltage generating circuit output, the negative input end of described first operational amplifier links to each other with the output terminal of described first Voltage-controlled Current Source, the output terminal of described first operational amplifier is then managed with a PMOS, the grid of the 2nd PMOS pipe links to each other respectively, described first Voltage-controlled Current Source, the input end of second Voltage-controlled Current Source is connected to power supply respectively, the output terminal of described first Voltage-controlled Current Source links to each other with the source electrode of a described PMOS pipe, and the output terminal of described second Voltage-controlled Current Source is connected to the source electrode of the 2nd PMOS pipe; Described PMOS pipe and the 3rd NMOS pipe common drain, the 2nd PMOS pipe and the 4th NMOS pipe common drain;

The positive input terminal of described second operational amplifier connects second initial voltage of reference voltage generating circuit output, the negative input end of described second operational amplifier links to each other with the source electrode of described the 3rd NMOS pipe, the output terminal of described second operational amplifier then links to each other respectively with the grid of described the 3rd NMOS pipe, the 4th NMOS pipe, the input end of described first current source links to each other with the source electrode of described the 3rd NMOS pipe, and the input end of described second current source links to each other with the source electrode of described the 4th NMOS pipe; Described first current source, the second current source output terminal be ground connection respectively;

Described deviation detection circuit, comprise positive and negative input end and an output terminal, the positive input terminal of described deviation detection circuit connects the drain electrode that drives PMOS pipe in the buffer circuit, the 2nd PMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe respectively, the negative input end of described deviation detection circuit connects the reference voltage of outside input, and the output terminal of described deviation detection circuit then links to each other respectively with the control end of described first Voltage-controlled Current Source, second Voltage-controlled Current Source; When the positive input terminal voltage of described deviation detection circuit during greater than negative input end voltage, the output end voltage of described deviation detection circuit rises; When the positive input terminal voltage of described deviation detection circuit during less than negative input end voltage, the output end voltage of described deviation detection circuit descends; When the positive input terminal voltage of described deviation detection circuit equaled negative input end voltage, the output end voltage of described deviation detection circuit remained unchanged.

10, circuit according to claim 9, it is characterized in that, described first Voltage-controlled Current Source comprises the 14 PMOS pipe (M14), the grid of described the 14 PMOS pipe is the control end of Voltage-controlled Current Source, the source electrode of described the 14 PMOS pipe is the input end of Voltage-controlled Current Source, and the drain electrode of described the 14 PMOS pipe is the output terminal of Voltage-controlled Current Source;

Described second Voltage-controlled Current Source comprises the 15 PMOS pipe (M15), the grid of described the 15 PMOS pipe is the control end of Voltage-controlled Current Source, the source electrode of described the 15 PMOS pipe is the input end of Voltage-controlled Current Source, and the drain electrode of described the 15 PMOS pipe is the output terminal of Voltage-controlled Current Source.

11, according to claim 9 or 10 described circuit, it is characterized in that described deviation detection circuit comprises: the 4th current source (CS4), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 9th NMOS pipe (M9);

The input end of described the 4th current source connects power supply, the output terminal of described the 4th current source is managed with the 7th PMOS, the source electrode of the 8th PMOS pipe links to each other respectively, the grounded drain of the 7th PMOS pipe, the grid of described the 7th PMOS pipe are the positive input terminal of described deviation detection circuit; The grid of the 8th PMOS pipe is the negative input end of described deviation detection circuit, the grid of described the 8th PMOS pipe is used to connect the reference voltage of default outside input, and the fixed voltage equal and opposite in direction imported of this voltage and the outside that negative input end was connected of the 3rd operational amplifier described in the reference voltage generating circuit; The drain electrode of the 8th PMOS pipe links to each other respectively with drain electrode, the grid of the 9th NMOS, the source ground of described the 9th NMOS, and the grid of described the 9th NMOS is the output terminal of described deviation detection circuit.

12, circuit according to claim 2 is characterized in that, described driving buffer circuit comprises:

The positive input terminal of described first operational amplifier connects first initial voltage of reference voltage generating circuit output, the negative input end of described first operational amplifier links to each other with the output terminal of described first Voltage-controlled Current Source, the output terminal of described first operational amplifier and PMOS pipe, the grid of the 2nd PMOS pipe links to each other respectively, described first Voltage-controlled Current Source, the input end of second Voltage-controlled Current Source is connected to power supply respectively, the output terminal of described first Voltage-controlled Current Source links to each other with the source electrode of a described PMOS pipe, and the output terminal of described second Voltage-controlled Current Source is connected to the source electrode of described the 2nd PMOS pipe; Described PMOS pipe and the 3rd NMOS pipe common drain, the 2nd PMOS pipe and the 4th NMOS pipe common drain;

The positive input terminal of described second operational amplifier connects second initial voltage of reference voltage generating circuit output, the negative input end of described second operational amplifier links to each other with the source electrode of described the 3rd NMOS pipe, the output terminal of described second operational amplifier is managed with described the 3rd NMOS, the grid of the 4th NMOS pipe links to each other respectively, the described first current source input end links to each other with the source electrode of described the 3rd NMOS pipe, and the described second current source input end links to each other with the source electrode of described the 4th NMOS pipe; The output terminal of described first current source, second current source is ground connection respectively;

Described deviation detection circuit comprises the first deviation detecting unit and the second deviation detecting unit, and each unit all further comprises positive and negative input end and an output terminal; Wherein the positive input terminal of the first deviation detecting unit connects the drain electrode that drives the pipe of a PMOS described in the buffer circuit, the 3rd NMOS pipe respectively, and the output terminal of the described first deviation detecting unit links to each other with the control end of described first Voltage-controlled Current Source; The positive input terminal of the second deviation detecting unit connects the drain electrode that drives the pipe of the 2nd PMOS described in the buffer circuit, the 4th NMOS pipe respectively, and the output terminal of the described second deviation detecting unit links to each other with the control end of described second Voltage-controlled Current Source; The negative input end of described two unit connects the reference voltage of the identical outside input of size; To any described deviation detecting unit, when the positive input terminal voltage of described deviation detecting unit during greater than negative input end voltage, the output end voltage of this deviation detecting unit rises; When the positive input terminal voltage of described deviation detecting unit during less than negative input end voltage, the output end voltage of this deviation detecting unit descends; When the positive input terminal voltage of described deviation detecting unit equaled negative input end voltage, the output end voltage of this deviation detecting unit remained unchanged.

13, circuit according to claim 12, it is characterized in that, described first Voltage-controlled Current Source comprises the 14 PMOS pipe (M14), the grid of described the 14 PMOS pipe is the control end of Voltage-controlled Current Source, the source electrode of described the 14 PMOS pipe is the input end of Voltage-controlled Current Source, and the drain electrode of described the 14 PMOS pipe is the output terminal of Voltage-controlled Current Source;

According to claim 12 or 13 described circuit, it is characterized in that 14, the described first deviation detecting unit comprises: the 4th current source (CS4), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 9th NMOS pipe (M9);

The input end of described the 4th current source connects power supply, the output terminal of described the 4th current source is managed with the 7th PMOS, the source electrode of the 8th PMOS pipe links to each other respectively, the grounded drain of the 7th PMOS pipe, the grid of described the 7th PMOS pipe are the positive input terminal of this deviation detecting unit; The grid of the 8th PMOS pipe is the negative input end of this deviation detecting unit, the grid of described the 8th PMOS pipe is used to connect the reference voltage of default outside input, and the fixed voltage equal and opposite in direction imported of this voltage and the outside that negative input end was connected of the 3rd operational amplifier described in the reference voltage generating circuit; The drain electrode of the 8th PMOS pipe links to each other respectively with drain electrode, the grid of the 9th NMOS pipe, the source ground of described the 9th NMOS pipe, and the grid of described the 9th NMOS pipe is the output terminal of this deviation detecting unit;

The input end of described the 5th current source connects power supply, the output terminal of described the 5th current source is managed with the tenth PMOS, the source electrode of the 11 PMOS pipe links to each other respectively, the grounded drain of the tenth PMOS pipe, the grid of described the tenth PMOS pipe are the positive input terminal of this deviation detecting unit; The grid of the 11 PMOS pipe is the negative input end of this deviation detecting unit, the grid of described the 11 PMOS pipe is used to connect the reference voltage of default outside input, and the fixed voltage equal and opposite in direction imported of this voltage and the outside that negative input end was connected of the 3rd operational amplifier described in the reference voltage generating circuit; The drain electrode of the 11 PMOS pipe links to each other respectively with the drain electrode of the 12 NMOS pipe, grid, the source ground of described the 12 NMOS pipe, and the grid of described the 12 NMOS pipe is the output terminal of this deviation detecting unit.

15, circuit according to claim 2 is characterized in that, described driving buffer circuit comprises:

The positive input terminal of described first operational amplifier connects first initial voltage of reference voltage generating circuit output, the negative input end of described first operational amplifier links to each other with output terminal with described first current source, the output terminal of described first operational amplifier is then managed with a PMOS, the grid of the 2nd PMOS pipe links to each other respectively, and described first current source, the input end of second Voltage-controlled Current Source is connected to power supply respectively, the output terminal of described first current source links to each other with the source electrode of a described PMOS pipe, and the output terminal of described second Voltage-controlled Current Source is connected to the source electrode of the 2nd PMOS pipe; Described PMOS pipe and the 3rd NMOS pipe common drain, the 2nd PMOS pipe and the 4th NMOS pipe common drain;

The positive input terminal of described second operational amplifier connects second initial voltage of reference voltage generating circuit output, the negative input end of described second operational amplifier links to each other with source electrode with described the 3rd NMOS pipe, the output terminal of described second operational amplifier then links to each other respectively with the grid of described the 3rd NMOS pipe, the 4th NMOS pipe, the input end of described first Voltage-controlled Current Source links to each other with the source electrode of the 3rd NMOS pipe, and the input end of described second current source links to each other with the source electrode of described the 4th NMOS pipe; Described first Voltage-controlled Current Source, the second current source output terminal be ground connection respectively;

Described deviation detection circuit comprises the first deviation detecting unit and the second deviation detecting unit, and each unit all further comprises positive and negative input end and an output terminal; Wherein the positive input terminal of the first deviation detecting unit connects the drain electrode that drives the pipe of a PMOS described in the buffer circuit, the 3rd NMOS pipe respectively, and the described first deviation detecting unit output terminal then links to each other with the control end of described first Voltage-controlled Current Source; The positive input terminal of the second deviation detecting unit connects the drain electrode that drives the pipe of the 2nd PMOS described in the buffer circuit, the 4th NMOS pipe respectively, and the output terminal of the described second deviation detecting unit links to each other with the control end of described second Voltage-controlled Current Source; The negative input end of described two unit connects the reference voltage of the identical outside input of size; To any described deviation detecting unit, when described deviation detecting unit when positive input terminal voltage during greater than negative input end voltage, the output end voltage of this deviation detecting unit rises; When the positive input terminal voltage of described deviation detecting unit during less than negative input end voltage, the output end voltage of this deviation detecting unit descends; When the positive input terminal voltage of described deviation detecting unit equaled negative input end voltage, the output end voltage of this deviation detecting unit remained unchanged.

16, circuit according to claim 15 is characterized in that, described first Voltage-controlled Current Source comprises the 6th NMOS pipe (M6):

The grid of described the 6th NMOS pipe is the control end of Voltage-controlled Current Source, and the drain electrode of described the 6th NMOS pipe is the input end of Voltage-controlled Current Source, and the source electrode of described the 6th NMOS pipe is the output terminal of Voltage-controlled Current Source.

17, circuit according to claim 16 is characterized in that, described second Voltage-controlled Current Source comprises the 14 PMOS pipe (M14):

The grid of described the 14 PMOS pipe is the control end of Voltage-controlled Current Source, and the source electrode of described the 14 PMOS pipe is the input end of Voltage-controlled Current Source, and the drain electrode of described the 14 PMOS pipe is the output terminal of Voltage-controlled Current Source.

According to claim 15,16 or 17 described circuit, it is characterized in that 18, the described first deviation detecting unit comprises: the 4th current source (CS4), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 9th NMOS pipe (M9);

The input end of described the 4th current source connects power supply, the output terminal of described the 4th current source is managed with the 7th PMOS, the source electrode of the 8th PMOS pipe links to each other respectively, the grounded drain of the 7th PMOS pipe, the grid of described the 7th PMOS pipe are the positive input terminal of this deviation detecting unit; The grid of the 8th PMOS pipe is the negative input end of this deviation detecting unit, the grid of described the 8th PMOS pipe is used to connect default external input voltage, and the fixed voltage equal and opposite in direction of the outside that negative input end was connected of this voltage and the 3rd operational amplifier described in reference voltage generating circuit input; The drain electrode of the 8th PMOS pipe links to each other respectively with drain electrode, the grid of the 9th NMOS pipe, the source ground of described the 9th NMOS pipe, and the grid of described the 9th NMOS pipe is the output terminal of this deviation detecting unit;

The input end of described the 5th current source connects power supply, the output terminal of described the 5th current source is managed with the tenth PMOSG, the source electrode of the 11 PMOSG pipe links to each other respectively, the grounded drain of the tenth PMOSG pipe, the grid of described the tenth PMOSG pipe are the positive input terminal of this deviation detecting unit; The grid of the 11 PMOSG pipe is the negative input end of this deviation detecting unit, the grid of described the 11 PMOSG pipe is used to connect default external input voltage, and the fixed voltage equal and opposite in direction of the outside that negative input end was connected of this voltage and the 3rd operational amplifier described in reference voltage generating circuit input; The drain electrode of the 11 PMOSG pipe links to each other respectively with the drain electrode of the 12 NMOSG pipe, grid, the source ground of described the 12 NMOSG pipe, and the grid of described the 12 NMOSG pipe is the output terminal of this deviation detecting unit.

19, circuit according to claim 2 is characterized in that, described driving buffer circuit comprises:

First operational amplifier (A1), second operational amplifier (A2), the one PMOS pipe (M1), the 2nd PMOS manage (M2), the 3rd NMOS pipe (M3), the 4th NMOS manage (M4), first Voltage-controlled Current Source (VCCS1), second Voltage-controlled Current Source (VCCS2) and first current source (CS1), second current source (CS2); Draw the positive output end of described reference voltage buffer circuit by the output terminal of described second current source, draw the negative output terminal of described reference voltage buffer circuit by the input end of described second Voltage-controlled Current Source;

The positive input terminal of described first operational amplifier connects first initial voltage of reference voltage generating circuit output, the negative input end of described first operational amplifier links to each other with the output terminal of described first Voltage-controlled Current Source, the output terminal of described first operational amplifier is then managed with a PMOS, the grid of the 2nd PMOS pipe links to each other respectively, described first Voltage-controlled Current Source, the input end of second current source is connected to power supply respectively, the output terminal of described first Voltage-controlled Current Source links to each other with the source electrode of a described PMOS pipe, and the output terminal of described second current source is connected to the source electrode of the 2nd PMOS pipe; Described PMOS pipe and the 3rd NMOS pipe common drain, the 2nd PMOS pipe and the 4th NMOS pipe common drain;

The positive input terminal of described second operational amplifier connects second initial voltage of reference voltage generating circuit output, the negative input end of described second operational amplifier links to each other with the source electrode of described the 3rd NMOS pipe, the output terminal of described second operational amplifier then links to each other respectively with the grid of described the 3rd NMOS pipe, the 4th NMOS pipe, the input end of described first current source links to each other with the source electrode of described the 3rd NMOS pipe, and the input end of described second Voltage-controlled Current Source links to each other with the source electrode of described the 4th NMOS pipe; Described first current source, the second Voltage-controlled Current Source output terminal be ground connection respectively;

Described deviation detection circuit comprises the first deviation detecting unit and the second deviation detecting unit, and each unit all further comprises positive and negative input end and an output terminal; Wherein the positive input terminal of the first deviation detecting unit connects the drain electrode that drives the pipe of a PMOS described in the buffer circuit, the 3rd NMOS pipe respectively, and the output terminal of the described first deviation detecting unit links to each other with the control end of described first Voltage-controlled Current Source; The positive input terminal of the second deviation detecting unit connects the drain electrode that drives the pipe of the 2nd PMOS described in the buffer circuit, the 4th NMOS pipe respectively, and the output terminal of the described second deviation detecting unit links to each other with the control end of second Voltage-controlled Current Source; The negative input end of described two unit connects the reference voltage of the identical outside input of size; To any described deviation detecting unit, when the positive input terminal voltage of described deviation detecting unit during greater than negative input end voltage, the output end voltage of this deviation detecting unit rises; When the positive input terminal voltage of described deviation detecting unit during less than negative input end voltage, the output end voltage of this deviation detecting unit descends; When the positive input terminal voltage of described deviation detecting unit equaled negative input end voltage, the output end voltage of this deviation detecting unit remained unchanged.

20, circuit according to claim 19 is characterized in that, described first Voltage-controlled Current Source comprises the 14 PMOS pipe (M14):

21, circuit according to claim 19 is characterized in that, described second Voltage-controlled Current Source comprises the 6th NMOS pipe (M6):

According to claim 19,20 or 21 described circuit, it is characterized in that 22, the described first deviation detecting unit comprises: the 4th current source (CS4), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 9th NMOS pipe (M9);