CN101523834B - Clock data recovery device - Google Patents
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- CN101523834B CN101523834B CN2007800381764A CN200780038176A CN101523834B CN 101523834 B CN101523834 B CN 101523834B CN 2007800381764 A CN2007800381764 A CN 2007800381764A CN 200780038176 A CN200780038176 A CN 200780038176A CN 101523834 B CN101523834 B CN 101523834B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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Abstract
A clock data recovery device (1) comprises a sampler section (10), a detection section (20), an offset determining section (30), a clock output section (40), and a DA converter (50). The phases of clock signals (CK, CKX) are adjusted so as to match the phase of an input digital signal. The given amount (+- Voff) of an offset in the sampler section (10) is adjusted so as to match the peak time of the data transition time distribution of a first signal when a value D (n-1) is at a high level and adjusted so as to match the peak time of the data transition time distribution of a second signal when the value D (n-1) is at a low level. Any one of the clock signals (CK, CKX) is outputted as the recovered clock signal. The time-series data of a digital value D (n) is outputted as the recovered data.
Description
Technical field
The present invention relates to the device that clock signal and data recovered according to the digital signal of input.
Background technology
Because the digital signal waveform generation during transmitting to receiver via transmission path from this transmitter from transmitter output is deteriorated, therefore need to recover clock signal and data at this receiver-side.This clock data recovery device for recovering for example is disclosed at patent documentation 1,2.
In the disclosed device of these documents, consider the moment change that data change in the deteriorated digital signal of waveform, detect each Bit data 3 timings.At this moment, in 3 timings when detecting each Bit data, the 1st timing setting is near the initial time during the data stabilization of this bit, and the 2nd timing setting is near the expired moment during the data stabilization of this bit, in addition, the middle moment of the 3rd timing setting between the 1st timing and the 2nd regularly.
And, in the disclosed device of patent documentation 1, by adjusting each regularly so that in full accord 3 detected data of timing for each bit, clock signal is recovered, in addition, recover data by regularly detecting each Bit data in the 3rd of centre this moment.
On the other hand, in the disclosed device of patent documentation 2, by adjusting each regularly so that the 1st regularly and the 2nd timing error rate separately (namely, the data that regularly detect these each are different from the ratio in the 3rd data that regularly detect of centre) be equal to each other and in the initial setting scope, clock signal is recovered, in addition, recover data by regularly detecting each Bit data in the 3rd of centre this moment.
Patent documentation 1: Japanese kokai publication hei 7-221800 communique
Patent documentation 2: Japanese Unexamined Patent Application Publication 2004-507963 communique
But, the change due to transmitter clock shake (transmitter clock jitter) of the data changing moment of supplied with digital signal, described transmitter clock shake produces because of the power supply voltage variation in the transmitter of sending digital signal and other noises; In addition, the data changing moment of supplied with digital signal is also due to intersymbol interference etc. and change, the irregular data pattern (data pattern) in described intersymbol interference factor word signal and the mixing of the decay in transmission path and produce.When larger, above-mentioned existing device can't recover clock signal and data sometimes when the shake of these transmitter clocks or intersymbol interference.
Summary of the invention
The present invention completes in order to address the above problem just, and its purpose is, even a kind of clock data recovery device that also can be more stably when larger clock signal and data be recovered in transmitter clock shake or intersymbol interference is provided.
Clock data recovery device of the present invention is the device that clock signal and data is recovered according to the digital signal of input, has sampling section, test section, skew determination portion and clock efferent.
The input of sampling section has clock signal C K and the clock signal C KX of same period T, and supplied with digital signal, (signal Voff) is made as the 1st signal will to have given skew to digital signal, (+signal after Voff) is made as the 2nd signal will to have given skew to digital signal, during each n in this cycle in T (n), to the moment t of clock signal C K indication
CThe digital value DA (n) of the 1st signal at place and the digital value DB (n) of the 2nd signal sample and keep and export, to the moment t of clock signal C KX indication
XThe digital value DXA (n) of the 1st signal at place and the digital value DXB (n) of the 2nd signal sample and keep and export.Wherein, " t
C＜t
X", n is integer.
test section is during each in T (n), input is from the value DA (n) of sampling section output, value DB (n), value DXA (n) and value DXB (n), D on duty (n-1) is when being high level, " if D (n)=DA (n) " and " DX (n-1)=DXA (n-1) ", D on duty (n-1) is when being low level, " if D (n)=DB (n) " and " DX (n-1)=DXB (n-1) ", the value of asking for D (n) and value DX (n-1), according to value D (n-1), value DX (n-1) and value D (n), detect the phase relation between clock signal C K and digital signal.
The skew determination portion is during each in T (n), the value D that input is obtained by test section (n) and value DX (n), determine in sampling section the skew amount of giving (± Voff), making is become the changing moment center of distribution of the 1st signal value by moment of clock signal C KX indication when being high level at value D (n-1), and become the changing moment center of distribution of the 2nd signal value in the moment that value D (n-1) is indicated by clock signal C KX when being low level.
The clock efferent comes adjustment cycle T or phase place according to the phase relation that is detected by test section, makes the phase difference between clock signal C K and digital signal diminish, and will satisfy " t
X-t
C=T/2 " the clock signal C K of relation and clock signal C KX output to sampling section.
The clock data recovery device of the present invention that consists of like this has the 1st loop of the sampling section of comprising, test section and clock efferent, and has the 2nd loop of the sampling section of comprising, test section and skew determination portion.By these two loop processed, clock signal C K is adjusted to consistent with the phase place of supplied with digital signal with clock signal C KX phase place separately.In addition, the skew amount of giving in sampling section (± Voff) to be adjusted to the peak value that distributes with the data changing moment that is worth the 1st signal of D (n-1) when the high level constantly consistent, and it is consistent to be adjusted to the peak value moment that the data changing moment of the 2nd signal when being worth D (n-1) for low level distributes.Then, any one of clock signal CK and clock signal C KX is as the clock signal after recovering.In addition, the time series data of output digital value D (n) is as the data after recovering.
Test section preferably has the phase relation testing circuit, this phase relation testing circuit output is the UP signal of effective value when " D (n-1) ≠ DX (n-1)=D (n) ", and be the DN signal of effective value when " D (n-1)=DX (n-1) ≠ D (n) ", as the signal of expression phase relation.
The clock efferent preferably, according to UP signal and DN signal adjustment cycle T or phase place, clock signal CK and clock signal C KX.
The skew determination portion is preferably determined the skew amount of giving in sampling section, so that the ratio (cntINSIDE/cntEDG) of the accumulated value cntEDG of the accumulated value cntINSIDE of " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " and " D (n) ^D (n-1) " and be worth difference between 0.5 below fiducial value.
the skew determination portion preferably, in T during each (n), only when exist in (T (n-9)～T (n)) during continuous 10 of the past that comprises during this period UP signal and DN signal be respectively effective value during the time, cumulative " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " asks for this accumulated value cntINSIDE, and cumulative " D (n) ^D (n-1) " asks for this accumulated value cntEDG, determine in sampling section the skew amount of giving so that the difference between ratio (cntINSIDE/cntEDG) and value 0.5 below fiducial value.
In addition, the skew determination portion is preferably come the correcting offset amount of giving according to value D (n-2) in T (n) during each.
According to the present invention, even also can stably recover clock signal and data when larger in transmitter clock shake or intersymbol interference.
Description of drawings
Fig. 1 is the figure of the eye pattern (eye pattern) of the digital signal that represents that schematically waveform is deteriorated.
Fig. 2 is explanation timing that the data of digital signal are sampled and the figure of the relation between skew.
Fig. 3 is the figure of an example that the eye pattern of the deteriorated digital signal of waveform is shown.
Fig. 4 is the figure that the timing of in the 1st execution mode, the data of digital signal being sampled is shown.
Fig. 5 is the figure of whole schematic configuration that the clock data recovery device 1 of the 1st execution mode is shown.
Fig. 6 is the circuit diagram of the test section 20 that comprises in the clock data recovery device 1 of the 1st execution mode.
Fig. 7 is the chart of truth table that the input and output value of the phase relation testing circuit 24 that comprises in test section 20 is shown.
Fig. 8 is the figure that the relation between the sampling instant shown in clock signal C KX and side-play amount Voff is shown.
Fig. 9 is the flow chart that the processing of the skew determination portion 30 that comprises in the clock data recovery device 1 of the 1st execution mode is described.
Figure 10 is the figure that the structure of the clock efferent 40 that comprises in the clock data recovery device 1 of the 1st execution mode is shown.
Figure 11 illustrates the figure of circuit structure that reference clock produces the 1st mode of circuit 41.
Figure 12 illustrates the figure of circuit structure that reference clock produces the 2nd mode of circuit 41.
Figure 13 illustrates the figure of circuit structure that reference clock produces the 3rd mode of circuit 41.
Figure 14 is the figure that the sampling timing of clock signal C K in the clock data recovery device 1 of the 1st execution mode and each self-indication of clock signal C KX is shown.
Figure 15 illustrates the figure of whole schematic configuration of the clock data recovery device 2 of the 2nd execution mode.
Figure 16 is the flow chart that the processing of the skew determination portion 30A that comprises in the clock data recovery device 2 of the 2nd execution mode is described.
Figure 17 is the figure that the processing of the skew determination portion 30A that comprises in the clock data recovery device 2 of the 2nd execution mode is described.
Figure 18 is the figure of whole schematic configuration that the clock data recovery device 3 of the 3rd execution mode is shown.
Figure 19 is the flow chart that the processing of the skew determination portion 30B that comprises in the clock data recovery device 3 of the 3rd execution mode is described.
Label declaration
1: clock data recovery device; 10: sampling section; 11～14: latch cicuit; 15～18: add circuit; 20: test section; 21: register circuit; 22,23: select circuit; 24: the phase relation testing circuit; 30,30A, 30B: skew determination portion; 40: the clock efferent; 41: reference clock produces circuit; 42: postpone to give circuit; The 50:DA converter section.
Embodiment
Below, describe in detail for implementing the preferred embodiment of the present invention with reference to accompanying drawing.In addition, the label identical to identical element annotation in the description of the drawings, the repetitive description thereof will be omitted.
The present invention completes consider the pattern effects (pattern effect) that produces in the deteriorated digital signal of waveform after.Therefore, at first pattern effects is described.Fig. 1 is the figure that the eye pattern of the deteriorated digital signal of waveform schematically is shown.At first, be conceived to the pattern effects that the time shaft to digital signal brings.As shown in the drawing, when the deteriorated digital signal of analysis waveform, the moment of data during from certain bit to next bit transition depended on the pattern of the data before this moment.That is, the data changing moment after identical data is continuous relatively lags behind (solid line in figure), and on the other hand, the data changing moment after data variation is leading (dotted line in figure) relatively.
Next, when pattern effects that the voltage axis (level) that is conceived to digital signal brings, the level of certain bit depends on the symbol of last bit.That is, even identical high level, if last bit is high level this bit is higher level, if last bit is low level this bit is lower level.For low level too.The level of this bit is depended in next transformation of certain bit.Compare when changing from lower low level to low level, the amplitude that changes when changing from higher high level to low level is larger, so changing moment lags behind.When changing from lower low level to high level too.When identical level higher high level or lower low level occur at the first two bit consecutive hours.Therefore, the changing moment of the bit that can say same level after continuously relatively lags behind.From another viewpoint, to compare when changing from lower low level to low level, when changing from higher high level to low level, waveform uprises.When changing from higher low level to high level too.Higher high level or higher low level appear when the bit when before is high level.Therefore, the skew of a rear transition waveforms is depended on the level of last bit and is changed.Such phenomenon is called pattern effects.The pattern of each Bit data is before this depended in the change of data changing moment, but depends on especially significantly the similarities and differences of each data of the first two bit.In addition, the data transition waveforms depends on the level of last bit and has skew.
In the present invention, on the basis of considering such pattern effects, at first the pattern effects of bringing for the time shaft of tackling to digital signal, the data changing moment when each data of the first two bit differ from one another at least and the data changing moment when each data of the first two bit are equal to each other at least are distinguished from each other and detect.In the present invention, utilize the timing adjustment of data and side-play amount to have the equivalence relation this point between giving, respectively for offset voltage value (Voff) be added on supplied with digital signal and the 1st signal, and with offset voltage value (+Voff) be added on supplied with digital signal and the 2nd signal, the timing of the peak value that is distributed by 1 clock signal C KX designation data changing moment, and adjust side-play amount Voff.
Fig. 2 is explanation timing that the data of above-mentioned digital signal are sampled and the figure of the equivalence relation between skew.In this Fig. 2 (a), the signal shown in dotted line is to have given signal after skew Voff to the supplied with digital signal shown in solid line.When considering to utilize same latch cicuit that the signal after having given skew Voff and original supplied with digital signal are sampled, compare with the sampling timing of original supplied with digital signal, the sampling timing of having given the signal after skew Voff is equivalent to and has shifted to an earlier date time τ off (=Voff/ slew rate (Slew Rate)).In addition, as shown in Fig. 2 (b), utilize latch cicuit to give to this effect that supplied with digital signal after skew Voff is sampled, also can (Voff) sample, namely give skew to sampling threshold and obtain the supplied with digital signal of not giving skew by utilize threshold value.
Next, describe for the above-mentioned pattern effects of bringing to the voltage axis (level) of digital signal.Fig. 3 is the figure of an example that the eye pattern of the deteriorated digital signal of waveform is shown.It is the situation of high level and the eye pattern when mixing for low level situation that Fig. 3 (a) illustrates data before 1 bit.Eye pattern when Fig. 3 (b) illustrates data before 1 bit and is high level.Eye pattern when Fig. 3 (c) illustrates data before 1 bit and is low level.That is, will become Fig. 3 (a) after Fig. 3 (b) and Fig. 3 (c) coincidence.
As shown in Fig. 3 (a), the data before 1 bit are the situation of high level and when mixing for low level situation, and the eyelet in eye pattern is narrower.Therefore, during the data level that the digital signal the when digital signal when the data before to 1 bit are high level according to 1 threshold voltage level Vth0 and the data before 1 bit are low level is carried out is judged, thereby the less error rate of voltage margin Vm0 may increase.In addition, on time shaft, the time width Tm0 that can carry out the level judgement is shorter, so the error rate also may increase.
But as shown in Fig. 3 (b), if observe data before the 1 bit eye pattern when being high level, the eyelet in this eye pattern is wider than Fig. 3's (a).Similarly, as shown in Fig. 3 (c), if observe data before the 1 bit eye pattern when being low level, the eyelet in this eye pattern is wider than Fig. 3's (a).But, the eyelet in the eye pattern the when eyelet in the eye pattern when being high level for the data before 1 bit and the data before 1 bit are low level, its level is different.
Therefore, when the data before 1 bit are high level (Fig. 3 (b)), carry out the level of data according to the threshold voltage level VthH higher than threshold voltage level Vth0 and judge, can access thus the voltage margin VmH larger than voltage margin Vm0, can reduce the error rate.In addition, on time shaft, the time width TmH that can carry out the level judgement is also long than time width Tm0, therefore can improve the patience to input jiffer.When similarly the data before 1 bit are low level (Fig. 3 (c)), carry out the level of data judges according to the threshold voltage level VthL lower than threshold voltage level Vth0, the voltage margin VmL larger than voltage margin Vm0 can be accessed thus, the error rate can be reduced.In addition, on time shaft, the time width TmL that can carry out the level judgement is also long than time width Tm0, therefore can improve the patience to input jiffer.In addition, research in further detail, according to the level of the data before 1 bit again, the level of the eyelet in eye pattern is also different.
In the present invention, utilize the adjustment of threshold voltage level Vth and side-play amount to have the equivalence relation this point between giving, with threshold voltage level be made as constant and according to 1 bit before data level difference adjust offset voltage value with the supplied with digital signal addition.
The present invention's eye pattern of the deteriorated digital signal of waveform as above according to probe opinion of obtaining just completes.In the 1st execution mode of the present invention of following explanation, the level differences of the eyelet between (Fig. 3 (c)) when (Fig. 3 (b)) and low level when being high level according to the data before 1 bit, (signal Voff) is made as the 1st signal will to have given skew to supplied with digital signal, (+signal after Voff) is made as the 2nd signal will to have given skew to supplied with digital signal, the processing of being scheduled to for these the 1st signals and the 2nd signal, definite skew amount of giving (± Voff), and recovered clock signal and data.And, in the 2nd execution mode of the present invention, proofread and correct the skew amount of giving of similarly determining with the 1st execution mode according to the level differences of the data before 1 bit again.
(the 1st execution mode)
Next, the 1st execution mode of clock data recovery device of the present invention is described.Fig. 4 is the figure that the timing of in the 1st execution mode, the data of digital signal being sampled is shown.This figure schematically shows the eye pattern of digital signal, in addition, utilizes CKX and CK that the timing of data sampling is shown.The clock data recovery device 1 of present embodiment is directed to has given skew (± the 1st signal and the 2nd signal after Voff) to digital signal, utilize clock signal C K to indicate the timing of sampling in during data stabilization, and, utilize clock signal C KX to indicate the timing of sampling when data change.
These two signals of clock signal C K and clock signal C KX have identical cycle T.The sampling instant t of clock signal C K indication
C, and the sampling instant t of clock signal C KX indication
XHas " t
X-t
C=T/2 " relation.In addition, in T (n), the sampling instant that these two signals of clock signal C K and clock signal C KX are indicated respectively sequentially is arranged in order according to this during each n of cycle T.N is integer arbitrarily.
(signal Voff) is made as the 1st signal, and (=supplied with digital signal-Voff), (+signal after Voff) is made as the 2nd signal (=supplied with digital signal+Voff) will to have given skew to supplied with digital signal will to have given skew to supplied with digital signal.In T during each (n), value representation at the 1st signal of the moment of clock signal C K indication sampling is DA (n), value representation at the 2nd signal of the moment of clock signal C K indication sampling is DB (n), value representation at the 1st signal of the moment of clock signal C KX indication sampling is DXA (n), and, be DXB (n) at the value representation of the 2nd signal of the moment of clock signal C KX indication sampling.Wherein, these cycle T and side-play amount Voff are adjusted by clock data recovery device 1.
In addition, these two signals of clock signal C K and clock signal C KX can be single-phase separately, can be also heterogeneous.For example, consider the situation that clock signal C K is made as 4 phases, using the cycle separately is 4 clock signal C K＜1 that 4T, phase place differ respectively pi/2 〉, CK＜2, CK＜3, CK＜4, and with these 4 clock signal C K＜1～CK＜4 in sampling section, 4 latch cicuits are set accordingly.Be made as when heterogeneous, although the circuit scale of sampling section becomes large, the rate request of each circuit module relaxed.
In addition, these two signals of clock signal C K and clock signal C KX can be different, can be also common.In the latter case, also common clock signal can be made as cycle T, pulse duration is T/2, represent clock signal C K with the rising edge of common clock signal, represent clock signal C KX with the trailing edge of common clock signal.
Fig. 5 is the figure of whole schematic configuration that the clock data recovery device 1 of the 1st execution mode is shown.As shown in the drawing, clock data recovery device 1 has sampling section 10, test section 20, skew determination portion 30, clock efferent 40 and DA converter section 50.
Sampling section 10 comprises 4 latch cicuits 11～14 and 4 add circuits 15～18, input is from the clock signal C K with same period T and the clock signal C KX of 40 outputs of clock efferent, the magnitude of voltage that input is exported from DA converter section 50 (± Voff), and input recovers the object digital signal.Add circuit 15,17 (Voff) with the digital signal addition of inputting, will output to latch cicuit 11,13 as the 1st signal of its addition result with offset voltage value.In addition, add circuit 16,18 with offset voltage value (+Voff) with the digital signal addition inputted, will output to latch cicuit 12,14 as the 2nd signal of its addition result.
In addition, can replace supplied with digital signal is given skew and adopted the structure of the sampling threshold skew make in each latch cicuit.At this moment, can omit add circuit 15～18.And, in this case, latch cicuit 11～14 input respectively from the magnitude of voltage of DA converter section 50 output (+Voff or-Voff).Then, latch cicuit 11～14 is respectively in the moment of clock signal C K or clock signal C KX indication, utilize skew+Voff or-threshold value after Voff samples to supplied with digital signal and keeps and output to test section 20.At this, suppose offset voltage in each latch cicuits 11～14 of DA converter section 50 output (+Voff or-Voff) itself, but so long as for each latch cicuit 11～14 make sampling threshold skew+Voff or-signal of Voff, can not be also offset voltage (+Voff or-Voff) itself.
Skew determination portion 30 in T (n), input is exported from test section 20 during each digital value D (n) and digital value DX (n).In addition, the skew amount of giving in the definite sampling of skew determination portion 30 section 10 (± Voff), the moment that the value of making D (n-1) is indicated by clock signal C KX when being high level becomes the changing moment center of distribution of the 1st signal value, and become the changing moment center of distribution of the 2nd signal value at value D (n-1) when being low level by moment of clock signal C KX indication, this skew amount of giving Voff that determines is notified to DA converter section 50.
Fig. 6 is the circuit diagram of the test section 20 that comprises in the clock data recovery device 1 of the 1st execution mode.Test section 20 comprises register circuit 21, selects circuit 22, selects circuit 23 and phase relation testing circuit 24.
Register circuit 21 during each in T (n) input from digital value DA (n), digital value DB (n), digital value DXA (n) and the digital value DXB (n) of 10 outputs of sampling section, and input is from selecting the digital value D (n) of circuit 22 outputs, keeps they and the timing output be scheduled in during certain.That is, register circuit 21 while output valve DA (n), value DB (n), value DXA (n-1), value DXB (n-1) and value D (n-1) during certain.
Select circuit 23 inputs from value DXA (n-1), value DXB (n-1) and the value D (n-1) of register circuit 21 outputs, value D (n-1) when being high level output valve DXA (n-1) as value DX (n-1), at value D (n-1) output valve DXB (n-1) conduct value DX (n-1) when being low level.
24 inputs of phase relation testing circuit are from the value D (n-1) of register circuit 21 outputs, input is from selecting the value D (n) of circuit 22 outputs, and input is from selecting the value DX (n-1) of circuit 23 outputs, carry out the logical operation according to truth table shown in Figure 7, output UP signal and DN signal.Namely, 24 outputs of phase relation testing circuit are the UP signal of effective value when " D (n-1) ≠ DX (n-1)=D (n) ", and be the DN signal of effective value when " D (n-1)=DX (n-1) ≠ D (n) ", as the signal of expression phase relation.
Fig. 8 is the figure that the relation between the sampling instant shown in clock signal C KX and side-play amount Voff is shown.As shown in Fig. 8 (a), in the situation that the changing moment center of distribution that value D (n-1) is later than the 1st signal value by the sampling instant of clock signal C KX indication when being high level constantly, value D (n-1) by the sampling instant of clock signal C KX indication early than the changing moment center of distribution of the 2nd signal value constantly, needs increase side-play amount Voff when being low level.
On the contrary, as shown in Fig. 8 (b), in the situation that value D (n-1) when being high level by the sampling instant of clock signal C KX indication early than the changing moment center of distribution of the 1st signal value constantly, value D (n-1) is later than the changing moment center of distribution moment of the 2nd signal value by the sampling instant of clock signal C KX indication when being low level, need to reduce side-play amount Voff.In addition, the figure shows the situation that digital signal value changes from low level to high level, but situation about changing from high level to low level too.
Skew determination portion 30 carries out adjusting side-play amount Voff in judgement illustrated in fig. 8.Fig. 9 is the flow chart that the processing of the skew determination portion 30 that comprises in the clock data recovery device 1 of the 1st execution mode is described.Skew determination portion 30 uses variable cntEDG, variable cntINSIDE, constant cntEDGTH, constant width, value D (n) and value DX (n) to carry out following processing.
In step S10, variable cntEDG and variable cntINSDE value separately are set as initial value 0.In following step S12, with the value of " D (n) ^D (n-1) " and the value addition of variable cntEDG, the value that obtains after this addition is made as the new value of variable cntEDG.In addition, in step S12, with the value of " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " and the value addition of variable cntINSIDE, the value that obtains after this addition is made as the new value of variable cntINSIDE.Herein, oeprator " ^ " expression XOR.In following step S13, whether the value of decision variable cntEDG equals constant cntEDGTH, if the value of variable cntEDG reaches constant cntEDGTH enters step S14, if reaching constant cntEDGTH, the value of variable cntEDG do not return to step S12.
Step S12 and step S13 processing are separately carried out 1 time in T (n) during each.That is, before the value that is judged to be variable cntEDG in step S13 has reached constant cntEDGTH, carry out the processing of 1 step S12 during each of cycle T.And the value that is judged to be variable cntEDG in step S13 has reached constant cntEDGTH and has entered moment of step S14, and the ratio of the value of variable cntINSDE and the value of variable cntEDG represents it is any one in Fig. 8 (a) and Fig. 8 (b).
In step S14 and step S15, for the certain limit centered by the value of 0.5 times of the value of variable cntEDG, take 2width as width, what kind of relation is the value of decision variable cntINSDE be in.In the situation that be judged to be the value of variable cntINSIDE less than 0.5 times of value (0.5*cntEDG-width) that deducts normal number width and obtain of the value of variable cntEDG, side-play amount Voff is increased, new side-play amount Voff is notified to DA converter section 50.In the situation that be judged to be the value of variable cntINSIDE greater than 0.5 times of value (0.5*cntEDG+width) that adds normal number width and obtain of the value of variable cntEDG, side-play amount Voff is reduced, new side-play amount Voff is notified to DA converter section 50.And, be present in above-mentioned certain limit in the situation that be judged to be the value of variable cntINSIDE, keep side-play amount Voff in step S18.
That is, in step S14～S18, be divided into 3 situations (a)～(c) as follows and carry out different processing.In addition, when any one processing of step S16～S18 finishes, return to step S10, the processing that repeats to have illustrated before this.
[formula 1]
(a) when " cntINSIDE＜0.5*cntEDG-width "
Increase Voff
(b) when " 0.5*cntEDG+width＜cntINSIDE "
Subtract Voff
When (c) value of cntINSIDE is in certain limit
Keep Voff
Thereby skew determination portion 30 carry out above such processing adjust the skew amount of giving (± Voff), make the value of variable cntINSIDE be present in certain limit (in 0.5*cntEDG-width～0.5*cntEDG+width).Thus, the sampling instant of clock signal C KX indication is adjusted to constantly consistent with the 1st signal value and the 2nd signal value changing moment center of distribution separately.
Reference clock produces circuit 41 and produces according to the reference clock signal of having adjusted from the UP signal of test section 20 outputs and DN signal after cycle T or phase place.Produce the circuit structure of circuit 41 as reference clock, can have various ways as shown in Figure 11～13.Postponing to give circuit 42 will be made as clock signal C K from the reference clock signal that reference clock produces circuit 41 outputs, and it is given the delay of T/2 and as clock signal C KX, exports these clock signal C K and clock signal C KX.
Figure 11 illustrates the figure of circuit structure that reference clock produces the 1st mode of circuit 41.Reference clock generation circuit 41A shown in this figure comprises CP, and (Charge Pump: charge pump) (Low Pass Filter: low pass filter) (Voltage-Controlled Oscillator: voltage controlled oscillator) circuit 413 for circuit 412 and VCO for circuit 411, LPF.Produce in circuit 41A at this reference clock, input is effective value from the CP circuit 411 of the UP signal of test section 20 outputs and DN signal according to which UP signal and DN signal, and the some current impulses in charging and discharging are outputed to LPF circuit 412.LPF circuit 412 input is from the current impulse of CP circuit 411 outputs, is which in charging and discharging according to the current impulse of this input, increases and decreases output voltage values.Then, VCO circuit 413 produce with from the output voltage values of LPF circuit 412 clock signal in corresponding cycle, this reference clock signal is outputed to delay gives circuit 42.Adjust the cycle that outputs to the clock signal that postpones to give circuit 42 from VCO circuit 413 according to UP signal and DN signal.
Figure 12 illustrates the figure of circuit structure that reference clock produces the 2nd mode of circuit 41.Reference clock shown in this figure produces circuit 41B and comprises CP circuit 411, LPF circuit 412, PLL (Phase Lock Loop: phase-locked loop) circuit 414 and variable delay circuit 415.Produce in circuit 41B at this reference clock, having inputted from the CP circuit 411 of the UP signal of test section 20 outputs and DN signal is effective value according to which UP signal and DN signal, and the some current impulses in charging and discharging are outputed to LPF circuit 412.LPF circuit 412 input is from the current impulse of CP circuit 411 outputs, is which in charging and discharging according to the current impulse of this input, increases and decreases output voltage values.PLL circuit 414 generates multi-phase clock according to input clock REFCLK, and this multi-phase clock is outputed to variable delay circuit 415.Then, variable delay circuit 415 input is from the multi-phase clock of PLL circuit 414 outputs, to multi-phase clock give with from delay corresponding to the magnitude of voltage of LPF circuit 412 outputs, given clock after postponing with this and outputed to and postpone to give circuit 42.Adjust the phase place that outputs to the clock signal that postpones to give circuit 42 from variable delay circuit 415 according to UP signal and DN signal.In addition, (Delay Lock Loop: delay lock loop) circuit replaces the PLL circuit also can to use DLL.
Figure 13 illustrates the figure of circuit structure that reference clock produces the 3rd mode of circuit 41.Reference clock shown in this figure produces circuit 41C and comprises PLL circuit 414, phase-control circuit 416 and phase-interpolation circuit 417.Produce in circuit 41C at this reference clock, having inputted from the phase-control circuit 416 of the UP signal of test section 20 output and DN signal is effective value according to which UP signal and DN signal, the control signal of the phase adjustment increase and decrease in output indication phase-interpolation circuit 417.PLL circuit 414 generates multi-phase clock according to input clock REFCLK, and this multi-phase clock is outputed to phase-interpolation circuit 417.And, 417 inputs of phase-interpolation circuit are from the multi-phase clock of PLL circuit 414 outputs, according to the control signal from phase-control circuit 416 outputs, by interpolation, the phase place of multi-phase clock is adjusted, the clock after this phase place adjustment is outputed to delay give circuit 42.Adjust the phase place that outputs to the clock signal that postpones to give circuit 42 from phase-interpolation circuit 417 according to UP signal and DN signal.In addition, also can replace the PLL circuit with the DLL circuit.
Above such clock data recovery device that consists of 1 has the 1st loop that comprises sampling section 10, test section 20 and clock efferent 40, and has the 2nd loop that comprises sampling section 10, test section 20, skew determination portion 30 and DA converter section 50.By these two loop processed, clock signal C K is adjusted to consistent with the phase place of supplied with digital signal with clock signal C KX phase place separately.The skew amount of giving in sampling section 10 (± Voff) to be adjusted to the peak value that distributes with the data changing moment that is worth the 1st signal of D (n-1) when the high level constantly consistent, and it is consistent to be adjusted to the peak value moment that the data changing moment of the 2nd signal when being worth D (n-1) for low level distributes.And any one of clock signal CK and clock signal CKX is as the clock signal of recovering.In addition, the time series data of output digital value D (n) is as the data of recovering.
Figure 14 is the figure that the sampling timing of clock signal C K in the clock data recovery device 1 of the 1st execution mode and each self-indication of clock signal C KX is shown.Figure 14 (a) illustrates the situation that time of the eye pattern of supplied with digital signal changes.And, the eye pattern in Figure 14 (b) illustrates between supplied with digital signal long-term.The change of the data changing moment of supplied with digital signal is because following factor produces: send intersymbol interference that transmitter clock shake that power supply voltage variation in the transmitter of this digital signal and other noises cause and the irregular data pattern in factor word signal and the mixing between the decay in transmission path cause etc.
In Figure 14 (a), because the transmitter clock shake, so the double dot dash line constantly of the center between stationary phase is curve according to the time series connection data.In addition, the data changing moment depends on the similarities and differences of the value D (n-2) of the first two bit and value D (n-1) and different phenomenons is because intersymbol interference.In the situation that the transmitter clock shake is larger, close as eyelet in the eye pattern between Figure 14 (b) supplied with digital signal that is shown in long-term, device as disclosed in patent documentation 2, in the time of near wanting the two ends that the sampling instant aligned data changing moment of digital signal is distributed, can't determine its sampling instant, therefore, also can't the center moment of specified data between stationary phase.
on the other hand, in the clock data recovery device 1 of the 1st execution mode, in sampling section 10, (signal Voff) is made as the 1st signal will to have given skew to digital signal, (+signal after Voff) is made as the 2nd signal will to have given skew to digital signal, during each n in T (n), to clock signal C K indication the moment place the digital value DA (n) of the 1st signal and the digital value DB (n) of the 2nd signal sample and keep and export, to clock signal C KX indication the moment place the digital value DXA (n) of the 1st signal and the digital value DXB (n) of the 2nd signal sample and keep and export.
Then, in the present embodiment, D on duty (n-1) is when being high level, " if D (n)=DA (n) " and " DX (n)=DXA (n) ", D on duty (n-1) is when being low level, " if D (n)=DB (n) " and " DX (n)=DXB (n) ", the value of asking for D (n) and value DX (n), according to the phase relation between these values detection clock signal C K and digital signal, adjust clock signal C K and clock signal C KX phase place separately.In addition, the skew amount of giving in adjustment sampling section 10 (± Voff), make D on duty (n-1) be become the changing moment center of distribution of the 1st signal value when being high level by moment of clock signal C KX indication, and D on duty (n-1) is become the changing moment center of distribution of the 2nd signal value by moment of clock signal C KX indication when being low level.
Thus, in the present embodiment, determine that timing that clock signal C K and clock signal C KX indicate respectively constantly in can be between short-term.That is, for the clock data recovery device 1 of the 1st execution mode, even when transmitter clock shake or intersymbol interference are larger, also stably recovered clock signal and data.
(the 2nd execution mode)
Next, the 2nd execution mode of clock data recovery device of the present invention is described.Figure 15 shows the whole schematic configuration of the clock data recovery device 2 of the 2nd execution mode.Compare with the structure of the clock data recovery device 1 of the 1st execution mode shown in Figure 5, the difference of the clock data recovery device 2 of the 2nd execution mode that this is shown in Figure 15 is: replace skew determination portion 30 and have skew determination portion 30A.
Skew determination portion 30A in T (n), input is exported from test section 20 during each digital value D (n) and digital value DX (n).Then, skew determination portion 30A determines the skew amount of giving in sampling section 10, the moment that makes D on duty (n-1) be indicated by clock signal C KX when being high level becomes the changing moment center of distribution of the 1st signal value, and D on duty (n-1) becomes the changing moment center of distribution of the 2nd signal value by the moment of clock signal C KX indication when being low level, and the skew amount of giving that will determine is notified to DA converter section 50.
The skew determination portion 30A of the 2nd execution mode and the skew determination portion of the 1st execution mode 30 are carried out roughly the same processing, but following aspect is different.Namely, skew determination portion 30A is during each in T (n), according to the UP signal in (T (n-9)～T (n)) during continuous 10 of the past that comprises during this period and each value of DN signal, determine whether accumulated value cntINSIDE and accumulated value cntEDG are carried out respectively accumulation process.
Figure 16 is the flow chart that the processing of the skew determination portion 30A that comprises in the clock data recovery device 2 of the 2nd execution mode is described.Compare with the processing of the skew determination portion 30 of the 1st execution mode shown in Figure 9, the difference of the processing of the skew determination portion 30A of the 2nd execution mode that this is shown in Figure 16 is: also have step S11 between step S10 and S12.
In step S11, in T during each (n), whether exist in (T (n-9)～T (n)) during 10 before judgement UP signal and DN signal be respectively effective value during, if exist enter step S12, if there is no do not enter step S12 and re-start the processing of step S11 during the next one.Figure 17 is the figure that the processing of the skew determination portion 30A that comprises in the clock data recovery device 2 of the 2nd execution mode is described.In the figure, be designated as " UP " during during the UP signal is effective value, be designated as " DN " during during the DN signal is effective value, in addition, during during blank column, UP signal and DN signal are invalid value.
Namely, skew determination portion 30A is during each in T (n), in the situation that exist in (T (n-9)～T (n)) during 10 the UP signal be effective value during and exist the DN signal be effective value during (Figure 17 (a)), in step S12, cumulative " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " asks for this accumulated value cntINSIDE, and cumulative " D (n) ^D (n-1) " asks for this accumulated value cntEDG.But, in the situation that during 10 (T (n-9)～T (n)) interior DN signal be always invalid value (Figure 17 (b)) or in the situation that during 10 (T (n-9)～T (n)) interior UP signal be always invalid value (Figure 17 (c)), skew determination portion 30A carries out accumulation process regardless of safety pin to accumulated value cntINSIDE and accumulated value cntEDG.
In addition, when skew determination portion 30A is judged as the accumulation process of the number of times that has carried out constant cntEDGTH in step S13, increase, reduce according to the relation of variable cntEDG and variable cntINSIDE value separately in step S14～S18 or keep the skew amount of giving, determine thus the skew amount of giving in sampling section 10, so that the difference of ratio (cntINSIDE/cntEDG) and value 0.5 is below fiducial value.
In addition, in step S11, judge whether in the scope during 10 based on following reason to exist UP signal and DN signal be respectively effective value during.That is, in the situation that exist data to change between a certain bit of supplied with digital signal and next bit, the valid value in UP signal and DN signal and the opposing party is invalid value.In the situation that do not exist data to change between a certain bit of supplied with digital signal and next bit, UP signal and DN signal both sides are invalid value.
If clock signal C K and clock signal C KX phase place separately are suitable, certain continuous a plurality of during in, as shown in Figure 17 (a), exist the UP signal be effective value during, also exist the DN signal be effective value during.But, if clock signal C K and clock signal C KX phase shifting separately, certain continuous a plurality of during in, the DN signal is always invalid value as shown in Figure 17 (b), perhaps the UP signal is always invalid value as shown in Figure 17 (c).
In the 8B10B code that uses in serial data communication, guarantee to change into more than 2 times in data between 10 bits.Therefore, if judge whether in the scope during 10 to exist UP signal and DN signal be respectively effective value during, if clock signal C K and clock signal C KX phase place separately are suitable, must exist in during these 10 the UP signal be effective value during, also must exist the DN signal be effective value during.
Otherwise, in the situation that in during 10, the DN signal is always invalid value, perhaps in the situation that during 10 in the UP signal be always invalid value, be judged to be clock signal C K and clock signal C KX phase shifting separately, therefore can not correctly detect the deviation between the skew amount of giving Voff and appropriate value.
Therefore, skew determination portion 30A in the 2nd execution mode is in step S11, by judgement whether exist in during before continuous 10 UP signal and DN signal be respectively effective value during, judge whether clock signal C K and clock signal C KX phase place separately be suitable, if phase place is fit to, carry out accumulation process in step S12.
Thus, even the clock data recovery device 2 of the 2nd execution mode when larger, is compared more stably recovered clock signal and data in transmitter clock shake or intersymbol interference with the situation of the 1st execution mode.
(the 3rd execution mode)
Next, the 3rd execution mode of clock data recovery device of the present invention is described.Figure 18 is the figure of whole schematic configuration that the clock data recovery device 3 of the 3rd execution mode is shown.Compare with the structure of the clock data recovery device 2 of the 2nd execution mode shown in Figure 15, the difference of the clock data recovery device 3 of the 3rd execution mode that this is shown in Figure 180 is: replace skew determination portion 30A and have skew determination portion 30B.
Skew determination portion 30B in T (n), input is exported from test section 20 during each digital value D (n) and digital value DX (n).In addition, skew determination portion 30B determines the skew amount of giving in sampling section 10, making D on duty (n-1) is the changing moment center of distribution of the 1st signal value by the moment of clock signal C KX indication when being high level, and D on duty (n-1) is the changing moment center of distribution of the 2nd signal value by the moment of clock signal C KX indication when being low level, and the skew amount of giving that will determine is notified to DA converter section 50.
The skew determination portion 30A of the skew determination portion 30B of the 3rd execution mode and the 2nd execution mode carries out roughly the same processing, but following aspect is different.That is, skew determination portion 30B in T (n), after similarly determining the skew amount of giving with the 2nd execution mode temporarily, proofreaies and correct and determine this skew amount of giving according to value D (n-2), and the skew amount of giving that will determine is notified to DA converter section 50 during each.
As use Fig. 3 illustrated, not only when changing, during stabilization side-play amount is also different, this side-play amount not only depends on the level of the previous bit of supplied with digital signal to the deteriorated digital signal of waveform, also depends on the level of the bit of front more.Therefore, so that the level of the previous bit of eyelet allowance basis becomes maximum, carry out being in the adjustment of threshold voltage level the adjustment of the skew amount of giving of equivalence relation for actual effect ground setting voltage threshold level.Namely, in the 1st execution mode and the 2nd execution mode, only consider the level of the previous bit of supplied with digital signal, but in the 3rd execution mode, except the level of considering previous bit is also considered the level of the bit of front more, determine thus the skew amount of giving in sampling section 10.
Figure 19 is the flow chart that the processing of the skew determination portion 30B that comprises in the clock data recovery device 3 of the 3rd execution mode is described.Skew determination portion 30B uses variable EDG, variable cntEDG, variable cntINSIDE[1], variable cntINSIDE[2], variable V off[1], variable c[2], constant cntEDGTH, constant width[1], constant width[2], value D (n) and value DX (n) carry out following processing.
In step S20, with variable cntEDG, variable cntINSIDE[1] and variable cntINSIDE[2] separately value is set as initial value 0.In following step S21, whether exist in (T (n-9)～T (n)) during 10 in T during each (n) before judgement UP signal and DN signal be respectively effective value during, if exist enter step S22, if there is no do not enter step S22 and re-start the processing of step S21 during the next one.
In step S22, the value of " D (n) ^D (n-1) " is made as the value of variable EDG, with the value addition of this value and variable cntEDG, the value that obtains after this addition is made as the new value of variable cntEDG.In step S22, value and variable cntINSIDE[1 that will " EDG*{D (n-2) ^DX (n-1) } "] the value addition, the value that obtains after this addition is made as variable cntINSIDE[1] new value.In addition, in step S22, value and variable cntINSIDE[2 that will " EDG*{D (n-3) ^DX (n-1) } "] the value addition, the value that obtains after this addition is made as variable cntINSIDE[2] new value.Herein, oeprator " ^ " illustrates XOR.In following step S23, whether the value of decision variable cntEDG equals constant cntEDGTH, if the value of variable cntEDG reaches constant cntEDGTH enters step S24, if reaching constant cntEDGTH, the value of variable cntEDG do not return to step S22.
Step S22 and step S23 processing are separately carried out 1 time in T (n) during each.That is, carry out the processing of 1 step S22 during each of cycle T, reach constant cntEDGTH until be judged to be the value of variable cntEDG in step S23.And the value that is judged to be variable cntEDG in step S23 has reached constant cntEDGTH and has entered moment of step S24, and the value of variable cntINSIDE and the ratio of the value of variable cntEDG show as any one of Fig. 8 (a) and Fig. 8 (b).
In step S24, for centered by the value of 0.5 times of the value of variable cntEDG, take 2width[1] be the certain limit of width, decision variable cntINSIDE[1] value be in what kind of relation, increase, reduce or keep variable V off[1 according to this result of determination].That is, in step S24, be divided into 3 situations (a)～(c) as follows and carry out different processing.This processes identical with the processing of step S14～S18 in the 1st execution mode and the 2nd execution mode.
[formula 2]
(a) " cntINSIDE[1]＜0.5*cntEDG-width[1] " time
Increase Voff[1]
(b) " 0.5*cntEDG+width[1]＜cntINSIDE[1] " time
Reduce Voff[1]
(c) cntINSIDE[1] value when being in certain limit
Keep Voff[1]
In following step S25, for centered by the value of 0.5 times of the value of variable cntEDG, take 2width[2] be the certain limit of width, decision variable cntINSIDE[2] value be in what kind of relation, increase, reduce or keep variable c[2 according to this result of determination].That is, in step S25, be divided into 3 situations (a)～(c) as follows and carry out different processing.The processing of this step S25 is except difference on as the variable of processing object and constant this point, and is identical with the processing of step S24.
[formula 3]
(a) " cntINSIDE[2]＜0.5*cntEDG-width[2] " time
Increase c[2]
(b) " 0.5*cntEDG+width[2]＜cntINSIDE[2] " time
Reduce c[2]
(c) cntINSIDE[2] value when being in certain limit
Keep c[2]
In following step S26, according to the variable V off[1 that determines in step S24], the variable c[1 that determines in step S25] and value D[n-2], carry out following computing, determine the skew amount of the giving Voff in sampling section 10, and the skew amount of the giving Voff that will determine notifies to DA converter section 50.Then, return to step S20, the processing that has illustrated before repeating.
[formula 4]
Voff＝Voff[1]+c[2]*d[n-2]
Wherein,
D[n-2]=1 o'clock d[n-2]=+ 1
D[n-2]=0 o'clock d[n-2]=-1
Carrying out as above processing by skew determination portion 30B adjusts and determines the skew amount of giving Voff[1 temporarily] so that variable cntINSIDE[1] value be present in certain limit (0.5*cntEDG-width[1]～0.5*cntEDG+width[1]).In addition, adjust correction coefficient c[2] so that variable cntINSIDE[2] value be present in certain limit (0.5*cntEDG-width[2]～0.5*cntEDG+width[2]).Then, according to correction coefficient c[2] proofread and correct the interim skew amount of the giving Voff[1 that determines], thus, determine the skew amount of the giving Voff in sampling section 10.
Like this, in the 3rd execution mode, except the level of the previous bit of considering supplied with digital signal is also considered the level of the bit of front more, determine thus the skew amount of the giving Voff in sampling section 10.Therefore, even the clock data recovery device 3 of the 3rd execution mode, is compared with the situation of the 2nd execution mode, more stably recovered clock signal and data when larger in transmitter clock shake or intersymbol interference.
In addition, skew determination portion 30B in T (n), can except also coming the correcting offset amount of giving according to value D (n-3) according to value D (n-2), also can further come the correcting offset amount of giving according to value D (n-4) during each.For example, in the situation that except also coming the correcting offset amount of giving according to value D (n-3) according to value D (n-2), the skew amount of giving Voff can obtain by following computing.Herein, correction coefficient c[3] acquiring method and above-mentioned correction coefficient c[2] roughly the same, the accumulated value that is adjusted to " EDG*{D (n-4) ^DX (n-1) } " is present in certain scope.
[formula 5]
Voff＝Voff[1]+c[2]*d[n-2]+c[3]*d[n-3]
Wherein,
D[n-2]=1 o'clock d[n-2]=+ 1
D[n-2]=0 o'clock d[n-2]=-1
D[n-3]=1 o'clock d[n-3]=+ 1
D[n-3]=0 o'clock d[n-3]=-1
Utilizability on industry
Even the invention provides a kind of clock data recovery device that also can be more stably when larger clock signal and data be recovered in transmitter clock shake or intersymbol interference.
Claims (5)
1. clock data recovery device, its digital signal according to input is recovered clock signal and data, it is characterized in that, and this clock data recovery device has:
Sampling section, its input has clock signal C K and the clock signal C KX of same period T, and input described digital signal, to be made as the 1st signal to the signal that described digital signal has been given after offset voltage value-Voff, to be made as the 2nd signal to the signal that described digital signal has been given after offset voltage value+Voff, during each n in this cycle in T (n), to the moment t of described clock signal C K indication
CThe digital value DA (n) of described the 1st signal at place and the digital value DB (n) of described the 2nd signal sample and keep and export, to the moment t of described clock signal C KX indication
XThe digital value DXA (n) of described the 1st signal at place and the digital value DXB (n) of described the 2nd signal sample and keep and export, wherein, and t
C＜t
X, n is integer;
test section, it is during each in T (n), input is from the value DA (n) of described sampling section output, value DB (n), value DXA (n) and value DXB (n), D on duty (n-1) is when being high level, " if D (n)=DA (n) " and " DX (n-1)=DXA (n-1) ", D on duty (n-1) is when being low level, " if D (n)=DB (n) " and " DX (n-1)=DXB (n-1) ", the value of asking for D (n) and value DX (n-1), according to value D (n-1), value DX (n-1) and value D (n), detect the phase relation between described clock signal C K and described digital signal, UP signal and the DN signal of expression phase relation are outputed to the clock efferent,
The skew determination portion, it is during each in T (n), the value D that input is obtained by described test section (n) and value DX (n), determine the skew amount of giving ± Voff in described sampling section, make the changing moment center of distribution that becomes the value of described the 1st signal in the moment that value D (n-1) is indicated by described clock signal C KX when being high level, and become the changing moment center of distribution of the value of described the 2nd signal at value D (n-1) when being low level by moment of described clock signal C KX indication, notify the converter section to DA with the determined skew amount of giving;
The clock efferent, its UP signal and DN signal according to the expression phase relation that is detected by described test section comes adjustment cycle T or phase place, makes the phase difference between described clock signal C K and described digital signal diminish, and will satisfy " t
X-t
C=T/2 " the described clock signal C K of relation and described clock signal C KX output to described sampling section; And
The DA converter section will output to sampling section as analog voltage from the skew amount of giving of skew determination portion notice,
described skew determination portion is determined the skew amount of giving by following processing, variable cntEDG and variable cntINSIDE value separately are set as initial value 0, with the value of " D (n) ^D (n-1) " and the value addition of variable cntEDG, the value that obtains after this addition is made as the new value of variable cntEDG, in addition, with the value of " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " and the value addition of variable cntINSIDE, the value that obtains after this addition is made as the new value of variable cntINSIDE, when " cntINSIDE＜0.5*cntEDG-width ", increase Voff, when " 0.5*cntEDG+width＜cntINSIDE ", reduce Voff, when the value of cntINSIDE is in certain limit, keep Voff, herein, and oeprator " ^ " expression XOR, width is normal number,
Described test section comprises the phase relation testing circuit, this phase relation testing circuit described UP signal of output and DN signal are as the signal of expression phase relation, this UP signal is effective value when " DX (n-1) ≠ D (n-1) and DX (n-1)=D (n) ", and this DN signal is effective value when " DX (n-1)=D (n-1) and DX (n-1) ≠ D (n) ".
2. clock data recovery device according to claim 1, is characterized in that, described clock efferent comes adjustment cycle T or phase place according to described UP signal and described DN signal, exports described clock signal C K and described clock signal C KX.
3. clock data recovery device according to claim 1, it is characterized in that, described skew determination portion is determined the skew amount of giving in described sampling section, so that the difference between the ratio cntINSIDE/cntEDG of the accumulated value cntEDG of the accumulated value cntINSIDE of " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " and " D (n) ^D (n-1) " and value 0.5 is below fiducial value.
4. clock data recovery device according to claim 1, is characterized in that, described skew determination portion,
In T during each (n), only when exist in (T (n-9)～T (n)) during continuous 10 of the past that comprises during this period described UP signal and described DN signal be respectively effective value during the time, cumulative " { D (n) ^D (n-1) } * { D (n-2) ^DX (n-1) } " asks for this accumulated value cntINSIDE, and cumulative " D (n) ^D (n-1) " asks for this accumulated value cntEDG
Determine the skew amount of giving in described sampling section, make difference between ratio cntINSIDE/cntEDG and value 0.5 below fiducial value.
5. according to claim 3 or 4 described clock data recovery devices, is characterized in that, described skew determination portion is proofreaied and correct the described skew amount of giving according to value D (n-2) in T (n) during each.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2006277925A JP4557947B2 (en) | 2006-10-11 | 2006-10-11 | Clock data recovery device |
| JP277925/2006 | 2006-10-11 | ||
| PCT/JP2007/067400 WO2008044407A1 (en) | 2006-10-11 | 2007-09-06 | Clock data recovery device |
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| CN101523834A CN101523834A (en) | 2009-09-02 |
| CN101523834B true CN101523834B (en) | 2013-05-22 |
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| US (1) | US8045664B2 (en) |
| EP (1) | EP2079210B1 (en) |
| JP (1) | JP4557947B2 (en) |
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| CN (1) | CN101523834B (en) |
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| Publication number | Publication date |
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| JP2008098930A (en) | 2008-04-24 |
| JP4557947B2 (en) | 2010-10-06 |
| WO2008044407A1 (en) | 2008-04-17 |
| US8045664B2 (en) | 2011-10-25 |
| KR101277432B1 (en) | 2013-06-20 |
| CN101523834A (en) | 2009-09-02 |
| KR20090061626A (en) | 2009-06-16 |
| EP2079210A4 (en) | 2011-06-29 |
| US20100026350A1 (en) | 2010-02-04 |
| ES2394282T3 (en) | 2013-01-30 |
| EP2079210A1 (en) | 2009-07-15 |
| EP2079210B1 (en) | 2012-08-01 |
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