CN101512740B - Method and apparatus for forming nickel silicide with low defect density in FET devices - Google Patents

Method and apparatus for forming nickel silicide with low defect density in FET devices Download PDF

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CN101512740B
CN101512740B CN2006800367029A CN200680036702A CN101512740B CN 101512740 B CN101512740 B CN 101512740B CN 2006800367029 A CN2006800367029 A CN 2006800367029A CN 200680036702 A CN200680036702 A CN 200680036702A CN 101512740 B CN101512740 B CN 101512740B
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nickel
substrate
silicide
deposited
thickness
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CN101512740A (en
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K·K·H·旺格
R·J·珀特尔
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International Business Machines Corp
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24—Vacuum evaporation
    • C23C14/32—Vacuum evaporation by explosion; by evaporation and subsequent ionisation of the vapours, e.g. ion-plating
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3435—Applying energy to the substrate during sputtering
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in asolely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Description

In the FET device, form the method and apparatus of the nickel silicide with fabricating low-defect-density
The cross reference of related application
The sequence number that the application requires to submit on October 3rd, 2005 is 11/163038, be entitled as the priority of the U.S. Patent application of " METHOD AND APPARATUS FOR FORMING NICKEL SILICIDEWITH LOW DEFECT DENSITY IN FET DECIVES ", here by with reference to its full content is introduced.
Technical field
The present invention relates to the manufacturing of advanced semiconductor device, and relate in particular to the manufacturing of improving high performance field effect transistors (FET) in the CMOS integrated device, wherein in this FET structure, contain nickel silicide.
Background technology
Metal silicide is used in the manufacturing of advanced FET device, so that the restriction film resistor increases along with the reduction of technique live width.Especially, the neutralization of the top of the grid structure of FET often is converted into silicide adjacent to the silicon in the silicon area in the source/drain region of grid.In common silicification technics, at first metal level is deposited on the FET structure, facilitate wherein metal and the contacted Silicide formation of silicon thereby afterwards this structure is annealed; Remove subsequently unreacted metal.Figure 1A shows FET structure 10, and it is formed on the substrate 1 and has a pair of FET grid structure (having grid material 11,12 on gate dielectric 13,14), has spacer 15,16 at the sidepiece of grid material.All thick (blanket) metal level 17 is deposited on this structure; Heat treatment will impel layer in 17 metal and the silication in the source/drain region 2 of grid material 11,12 and substrate close.Formed like this regions of suicide material 18, as shown in Figure 1B.
When with other metal silicides (for example, cobalt silicide) when comparing, nickel silicide provides along with live width reduces and less increases film resistor.For this reason, think that extensively nickel silicide is the selection of making the silicide material of FET structure, the grid line of this structure is wide to be 65nm or below the 65nm.Temperature in the silicidation heat treatment is controlled, so that form with respect to high resistance NiSi 2The NiSi of low thin-film electro resistance state.
Regrettably, traditional nickel Formation of silicide technique is subject to the impact of so-called defect of pipeline, that is, in undesirable substrate silicide to outgrowth, the lateral growth under the spacer especially.In Figure 1B, schematically show pipeline 19.Ducted material can be NiSi or NiSi 2
The density of the defect of pipeline in the known nickel silicide is subject to the impact of employed metal deposition process type.(collimation) or nondirectional (uncollimated) that depositing operation (and instrument of carrying out this technique) is normally directed.Each depositing operation causes as a result differently contoured (profile) of silicide.In Fig. 2 A and Fig. 2 B, illustrated the metal that deposits on a pair of grid profile ( spacer 15,16 experienced highly reduce etching or " drop-down " technique after).The metal deposition process of collimation, wherein metallic atom is basically mobile with the straight line path of substrate surface quadrature, impels upper surface in the grid structure to form metal 21 and (comprise the surface between the grid) on substrate surface 21b to form basic uniformly metal to cover; Among the regional 21a on the sidewall of grid structure, only deposited sheet metal (Fig. 2 A).By contrast, non-collimated metal deposition process impels metal 22 to be deposited on the top and sidepiece of grid structure, so that the metal thickness on the sidewall among the regional 22a is close to the metal thickness on the top of grid (Fig. 2 B).In non-collimated process, grid structure, spacer and be deposited on the metal on the grid structural top so that covered the substrate of close spacer, thus cover may be imperfect for the metal on surface (for example regional 22b).This impact is more remarkable along with the aspect ratio increase (for example along with the distance between the grid structure reduces) in zone.
Illustrated among Fig. 2 C and Fig. 2 D as the result of these techniques and the profiles of suicides that forms.When using collimated deposition process (referring to Fig. 2 C), have the thickness of minimizing among the regional 23a of nickel silicide 23 on the sidepiece of grid structure, and in adjacent to the source of spacer/drain region 23b, have uniform fold.By contrast, when using non-collimated deposition process (referring to Fig. 2 D), have larger thickness among the regional 22a of nickel silicide 24 on the sidepiece of grid, and in the regional 22b adjacent to spacer, have relatively poor covering.
Study verifiedly, the density of defect of pipeline is affected by the directionality degree of depositing operation.For example, the deposition of the Ni in non-directional (non-collimation) technique may cause the lower nickel silicide pipe defect density of deposition than the thickness of similar nickel in directed (collimation) technique.In addition, the numerous staff in this area have been noted that the gate polysilicon film resistor of the silicide low about 30% that forms after the silicide that forms has than collimated deposition process after non-collimated metal deposition.This is owing to the metal thickness on the sidepiece that is deposited on grid in non-collimated process is larger.On the other hand, in non-collimated metal deposition process, the relatively poor covering of the silicide in source/drain region causes the high contact resistance in this zone.
Therefore, expect very much the best features of combination collimation and non-collimation nickel deposition process.Especially, the top that is desirably in the grid structure has non-directional deposition and have orientated deposition in source/drain region.A kind of possible method will be to carry out the nickel deposition with following two steps: (1) uses traditional, non-collimated process to deposit the thickness of part expectation in processing chamber; (2) use collimated process in another chamber, (for example, coming from the senior low pressure source instrument of Applied Materials Inc) and deposit remaining thickness.To need to connect this two processing chambers, so that substrate is not exposed in the air.Aspect the substrate processing two of equipment and increase, this solution is expensive.
For the potential of the NiSi that realizes making for FET, need a kind of nickel deposition process and instrument of integrated directed and non-directional processing step, so that silicide has the film resistor of minimum and avoids defect of pipeline as a result.
Summary of the invention
The present invention wherein carries out two processing steps by providing a kind of method of making the FET device at substrate to solve above-mentioned needs in same chamber: first step, in non-directional technique on device plated metal; And second step, in directional process on device plated metal.In first step, in treatment chamber, form the first plasma, and in second step, form the second plasma.The second plasma is formed in the inside of the annular electrode (in the situation of nickel deposition, being preferably the Ni ring) that is connected to the RF generator.The first plasma is so that material is removed from target, and the second plasma increases the ion concentration of this material.Substrate holder is provided, and it can be electrical bias, so that ion is adsorbed to substrate in the direction with the substrate quadrature.
In the grid structure of FET device and/or in source/drain region, can comprise the silicide (for example NiSi) that forms from the metal of deposition.Had the lower effective film resistance of suicided gate that forms than the metal that from simple directional process, deposits by the formed suicided gate of method of the present invention.Silicided source/drains zone formed according to the present invention has the source lower than the silicided source/drains zone of the metal formation that deposits/drain contact resistance equally from simple non-directional technique.This metal is preferably Ni, but can be in Ni, Ti, W, Mo, Co, Pt, Nb or its alloy any one.
Depositing operation can utilize the degree of collimation of metal deposition and come characterization according to the density of the silicide pipe defects of this degree.
According to a further aspect in the invention, provide a kind of device be used to carrying out above-mentioned technique.This device comprises substrate holder, and the target of substrate holder positioned opposite, is arranged in annular electrode between substrate holder and the target, is connected to this electrode and the section within it of being used for forms a RF generator of the second plasma and is connected to substrate holder and is used for making the 2nd RF generator of this substrate electrical bias.Do not have the second plasma and substrate not by the condition of electrical bias under, material (for example Ni) from target is deposited on the substrate non-directional, and exist under the condition of the second plasma and substrate by the condition of electrical bias under, directionally be deposited on the substrate from the material (for example Ni) of target.The second plasma has increased the ion concentration of material, and the biasing of substrate is so that the ion that comes from the second plasma mobile with the direction of substrate quadrature, is facilitated the orientated deposition of material on substrate thus.
According to a further aspect in the invention, the structure that forms at substrate comprises first area and the second area of metal silicide.In the first area, metal silicide is arranged on the top of structure and on the adjacent wall; In second area, metal silicide is arranged on the substrate adjacent to sidewall, so that the surface of metal silicide contacts with sidewall.In the second area, the thickness of metal silicide is along with reducing with reducing of sidewall distance.The zone of metal silicide can be discontinuous.
In the first area, the thickness of the metal silicide on the sidewall can be substantially equal to the thickness on the top.The thickness of the metal silicide in second area can be less than the thickness of the metal silicide in the first area.
According to a further aspect in the invention, be formed on a part that FET grid structure on the substrate comprises the grid material with top and sidewall, adjacent to the spacer of sidewall, on the top of grid material metal silicide the first area and on substrate and with the second area of the contacted metal silicide of spacer.First area and second area are discontinuous, and the thickness of the metal silicide in the second area is along with reducing with reducing of spacer distance.
Description of drawings
Figure 1A is the graphical representation of exemplary of the viewgraph of cross-section of a pair of typical FET grid structure that deposits the Formation of silicide metal level thereon.
Figure 1B is the indicative icon of the nickel silicide that forms in the grid structure of Figure 1A, wherein has defect of pipeline.
Fig. 2 A shows and uses collimation (orientation) process deposits at the profile of the structural metal of a pair of grid.
Fig. 2 B shows and uses non-collimation (non-directional) process deposits at the profile of the structural metal of a pair of grid.
Fig. 2 C shows behind the metal deposition that uses collimation (orientation) technique, the profile of the silicide that forms in a pair of grid structure.
Fig. 2 D shows behind the metal deposition that uses non-collimation (non-directional) technique, the profile of the silicide that forms in a pair of grid structure.
Fig. 3 A shows the profile of the metal that deposits in a pair of grid structure, and wherein this depositing operation is carried out according to the embodiment of the present invention.
Fig. 3 B shows after the metal deposition shown in Fig. 3 A, the profile of the silicide that forms in a pair of grid structure.
Fig. 4 is the indicative icon according to the metal deposition apparatus of another embodiment of the present invention.
Embodiment
Nickel deposition process according to the present invention is integrated orientation and non-directional deposition processes.Fig. 3 A shows at the profile with nickel nickel of deposition after the surface of spacer removes.Non-directional deposition is used for utilizing with expectation thickness top and the upper portion side wall of nickel 31 covering gate structures; Orientated deposition is used for guaranteeing that the metal 32 of source/drain region has enough thickness (especially between two adjacent gate structures).Should be noted that the result as orientated deposition, the metal of covering source/drain region is run into the surface of spacer and with it continuously (comparison diagram 2B and Fig. 3 A).Because being deposited on the substrate between the grid than a little less than effect on the top of grid structure in the non-directional technique, so the thickness of metal 32 is usually less than the thickness of metal 31.
Fig. 3 B shows the heat treatment as a result silicide afterwards of the nickel of Fig. 3 A.Non-directional deposition is guaranteed thicker Silicide formation (the regional 33a on the side of grid; Regional 24a among the comparison diagram 2D).Orientated deposition causes the silicide of the substrate in source/drain region to cover (zone 34; Regional 23b among the comparison diagram 2C).Amount of directional deposition is controlled, so that reduce (the regional 32a among Fig. 3 A) adjacent to the nickel thickness of spacer.This causes reducing (regional 34a at the silicide thickness of the edge of grid; Comparison diagram 2C), it is then so that will to form the possibility of defect of pipeline less.
Therefore the silicide that forms from the metal that deposits according to the present invention has lower gate polysilicon film resistor and lower pipe defect density than the formed silicide of metal that deposits simple directional process.In addition, the silicide that forms from the metal that deposits according to the present invention has lower source/drain contact resistance than the silicide that the metal that deposits forms simple non-directional technique.
The deposition chambers 100 of executive basis technique of the present invention schematically is shown among Fig. 4 therein.(Fig. 4 is the viewgraph of cross-section by the center of substrate.) metallic target 40 is positioned on the substrate 1, this substrate 1 is positioned on the substrate holder 60; In present manufacturing, substrate normally the 300mm diameter silicon chip and remain in the chuck (wafer chuck).This target is connected to DC power supply 41.In this embodiment, target 40 is that planar nickel target and DC power supply are in scope 500W-5kW.(can also use difform target, such as dome, the cup-shaped etc. that falls.) plasma 42 (usually from Ar gas) is formed between target and the substrate; The plasma bombardment of target so that material remove and to move towards substrate.Non-directional deposition occurs on the substrate like this, as in the conventional deposition tool.
Annular electrode is such as nickel ring 50, between target and substrate.Electrode can also be the ring of being made by the stainless steel that is coated with Ni, or nickel wire net or Ni cylinder.Ring 50 is connected to RF generator 51; When generator 51 was being worked, the second plasma 52 was formed on the inside of ring.RF generator 51 usually has frequency 1MHz to 4MHz and scope is provided is the power of 200W-2000W.The second plasma 52 is for increasing the density of positive nickel ion, and this nickel ion can be adsorbed in substrate surface.Ring can also be used as the aperture, is used for making the Ni atom collimation that moves to substrate 1 from target 40.
Another RF generator 61 is connected to chuck 60; This generator is used for making wafer bias, so that nickel ion 70 is adsorbed in substrate in the direction with the substrate quadrature.It is the power of 0-800W that RF generator 61 provides scope.The operating frequency of RF generator 61 is 13.56MHz normally, but also can be several MHz (for example, about 2MHz).
In the first step of integrated nickel deposition process, turn off generator 51 and generator 61 both.Like this, tool work is in traditional mode and facilitate the structural non-directional deposition of grid (especially, the covering of the sidewall of grid structure).This initial metal deposition can also be used for so that damage in the more difficult charging of step wafer subsequently.
In the second step of depositing operation, open RF generator 51 and RF generator 61 both, facilitate the orientated deposition of metal on the substrate.Metal will appreciate that, in the low pressure deposition chambers, in straight line path, guide metal ion 70 into substrate, so that can be deposited on (for example in the bottom of groove, perhaps on the substrate surface between the adjacent gate) in the high-aspect-ratio structure.Orientated deposition causes metal enough on the substrate between the grid to cover and so enough silicide coverings.
Alternatively, can when technique begins, carry out short-period directed metal deposition, thereby guarantee that the metal of (for example regional 32a shown in Fig. 3 A) covers near the spacer before the non-directional metal deposition begins.
Can optimize this technique by one or more running parameter that changes instrument.These parameters comprise the overall process time; The time that the RF generator is opened (orientated deposition time); Ratio between orientated deposition time and total time; Gas pressure in non-directional or the orientated deposition step; And the power that is provided by one or more RF generator.Whole technique can be considered as having the directionality (the perhaps collimation of the variable pitch of metal deposition) of variable pitch, and it affects density of silicide pipe defects then.Pipe defect density also is subject to the mixture of alloy of underlayer temperature, deposition and the impact of post-depositional annealing conditions.
Above-mentioned depositing operation especially can be applicable in the structural deposition of FET grid.More generally, this technique can be advantageously used in wherein will have high aspect ratio (groove for example, the degree of depth of this groove surpass its width about 2 times or more) feature in the various situations of plated metal.When the pipe defect density in the silicide that forms is subsequently controlled, the bottom that the degree of collimation of change deposition guarantees to cover with metal this feature.
Thereby above-mentioned metal deposition process and instrument can be advantageously used in nickel deposited and form nickel silicide.Will appreciate that this technique and instrument go for other Formation of silicide metals, Ni alloy for example, Ti, W, Mo, Co, Pt, Nb with and alloy.
Although invention has been described according to particular implementation, according to foregoing description clearly, a plurality of possibilities, modification and distortion will be apparent for those skilled in the art.Therefore, the present invention is intended to comprise that all fall into this possibility, modification and the distortion of scope and spirit of the present invention and claims.

Claims (25)

1. the method for a nickel deposited on substrate may further comprise the steps:
In non-directional technique on described substrate nickel deposited;
In directional process on described substrate nickel deposited; And
Silicon below the nickel of described nickel and described deposition forms nickel silicide subsequently,
Wherein said deposition step is carried out in same deposition chambers, and carries out with random order.
2. method according to claim 1, wherein
Described in non-directional technique the step of nickel deposited further be included in the first plasma zone and form plasma; And
Described in directional process the step of nickel deposited further be included in the second plasma zone and form plasma.
3. method according to claim 2, wherein
Described in directional process the step of nickel deposited comprise further the annular electrode that is arranged between described substrate and the nickel target relative with described substrate be provided that described annular electrode is connected to a RF generator; And
Described the second plasma zone comprises the inside of described annular electrode.
4. according to claim 2 or 3 described methods, plasma in wherein said the first plasma zone is so that material removes from the nickel target with described substrate positioned opposite, and the plasma in described the second plasma zone causes the ionization of described material.
5. method according to claim 4, wherein said substrate arrangement is on substrate holder, and described in directional process the step of nickel deposited further comprise the 2nd RF generator that is connected to described bearing be provided, be used for making described substrate electrical bias, the ion from described the second plasma zone is adsorbed onto described substrate in the direction with described substrate quadrature thus.
6. method according to claim 1, wherein said nickel silicide are the parts of the suicided gate of the FET device that forms at described substrate.
7. method according to claim 6, wherein said suicided gate has lower effective film resistance than the suicided gate that the nickel that deposits forms from simple directional process.
8. the described method of any one claim according to claim 1 or in the claim 6 to 7, wherein said method characteristic is the degree of collimation of nickel deposition, and the device that comprises described nickel silicide has the pipe defect density according to described degree of collimation.
9. the described method of any one claim in 7 according to claim 6, wherein said FET device comprises nickel silicided source/drain region, and described nickel silicided source/drain region has lower source/drain contact resistance than nickel silicided source/drain region that the nickel that deposits forms from simple non-directional technique.
10. method according to claim 1, wherein
Described method characteristic is the thickness of the nickel that deposits;
Described nickel silicide is formed in the part of the FET device on the described substrate, and wherein said FET device comprises the grid structure; And
Described nickel silicide has larger thickness than the nickel silicide of the nickel formation of the same thickness that deposits at the sidepiece of described grid structure from simple directional process.
11. method according to claim 1, wherein
Described method characteristic is the thickness of the nickel that deposits;
Described nickel silicide is formed in the part of the FET device on the described substrate, and wherein said FET device comprises the grid structure; And
Described nickel silicide has larger volume than the nickel silicide of the nickel formation of the same thickness that deposits in the top of described grid structure from simple directional process.
12. a device that is used for nickel deposited on substrate comprises:
Substrate holder;
Nickel target, itself and described substrate holder arrange that relatively the nickel that will remove from described nickel target by the bombardment from the plasma in the first plasma zone thus is deposited on the described substrate;
Electrode, it is arranged between described substrate holder and the described nickel target;
The one RF generator, it is connected to described electrode, is used for forming plasma in the second plasma zone of described electrode interior; And
The 2nd RF generator, it is connected to described substrate holder, is used for making described substrate electrical bias, wherein
Not having plasma to be formed in described the second plasma zone and not having under the condition of the described substrate of electrical bias, be deposited on the described substrate described nickel non-directional,
Plasma be formed in described the second plasma zone and described substrate by the condition of electrical bias under, described nickel directionally is deposited on the described substrate, and
Silicon below the nickel of described nickel and described deposition forms nickel silicide subsequently.
13. device according to claim 12, the plasma in wherein said the second plasma zone increases the ion concentration of described nickel.
14. the described device of any one claim in 13 according to claim 12, the biasing of wherein said substrate so that from the ion in described the second plasma zone mobile with the direction of described substrate quadrature, thus so that described nickel orientated deposition on described substrate.
15. the described device of any one claim in 13 according to claim 12, wherein said electrode has annular shape.
16. device according to claim 15, wherein said annular electrode collimation material moves towards described substrate from described nickel target.
17. a structure that is formed on the substrate comprises the zone of nickel silicide, wherein
Nickel silicide described in the first area be deposited on the top of described structure by nickel in non-directional technique and directional process and on the adjacent wall and subsequently the silicon below the nickel of described nickel and described deposition form;
On the substrate that is deposited on by nickel in described non-directional technique and directional process adjacent to described sidewall at nickel silicide described in the second area, so that the surface of the nickel in the described second area contacts with the surface of described sidewall, and the silicon below the nickel of described nickel and described deposition forms subsequently; And
The thickness of the nickel silicide in the described second area is along with reducing with reducing of described sidewall distance.
18. structure according to claim 17, the zone of wherein said nickel silicide is discrete.
19. according to claim 17 or 18 described structures, wherein in described first area, the thickness of the nickel silicide on the described sidewall is substantially equal to the thickness of the nickel silicide on the described top.
20. the described structure of any one claim in 18 according to claim 17, the nickel silicide in the wherein said first area is characterised in that the first thickness, and the nickel silicide in the described second area is characterised in that second thickness less than described the first thickness.
21. a FET grid structure that is formed on the substrate comprises:
The part of grid material, it has top and sidewall;
Spacer, it is adjacent to described sidewall;
The first area of nickel silicide, its be in non-directional technique and directional process nickel be deposited on the top of described grid material and subsequently the silicon below the nickel of described nickel and described deposition form; And
The second area of nickel silicide, it is that nickel is deposited on the described substrate and with described spacer and contacts in described non-directional technique and directional process, and the silicon below the nickel of described nickel and described deposition forms subsequently, wherein
Described first area and described second area are discrete, and
The thickness of the nickel silicide in the described second area is along with reducing with reducing of described spacer distance.
22. FET grid structure according to claim 21, the nickel silicide in the wherein said first area is characterised in that the first thickness, and the nickel silicide in the described second area is characterised in that second thickness less than described the first thickness.
23. the described FET grid of any one claim structure in 22 according to claim 21, wherein said spacer is adjacent to the bottom of described sidewall, and the first area of described nickel silicide comprises the top of described sidewall.
24. the described FET grid of any one claim structure in 22 according to claim 21, wherein in described first area, the thickness of the nickel silicide on the described sidewall equals the thickness of the nickel silicide on the described top.
25. the described FET grid of any one claim structure in 22 according to claim 21, wherein said grid material has the lateral dimension that is not more than 65nm.
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US7456095B2 (en) 2008-11-25
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JP5106400B2 (en) 2012-12-26
EP1946361B1 (en) 2014-08-13
EP1946361A4 (en) 2011-03-09
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US8298385B2 (en) 2012-10-30
US20080164540A1 (en) 2008-07-10
EP1946361A2 (en) 2008-07-23
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KR101055944B1 (en) 2011-08-09
US7759741B2 (en) 2010-07-20

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