CN101510817B - Method and apparatus for receiving mixing automatic re-transmission request - Google Patents
Method and apparatus for receiving mixing automatic re-transmission request Download PDFInfo
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Abstract
The embodiment of the invention discloses an HARQ receiving method and a device thereof, which relate to the field of wireless communication and can solve the problem of slow processing speed of the existing HARQ realization function. The HARQ receiving device of the embodiment of the invention comprises a bit collection unit used for reading a bit sequence after deinterlacing, finishing address conversion and outputting the bit sequence; a second time rate matching unit used for conducting rate matching for the second time to the bit sequence output by the bit collection unit; a storage unit used for storing the bit sequence output by the second time rate matching unit, controlling and parallel outputting the system bit of a first time rate matching, the first parity bit of the first time rate matching and the second parity bit of the first time rate matching; and a first time rate matching unit used for conducting parallel first time rate matching to the bits output by the storage unit. The embodiment of the invention is suitable to HARQ technology.
Description
Technical field
The present invention relates to wireless communication field, relate in particular to a kind of method of reseptance and device that mixes automatic repeat requests.
Background technology
HSDPA (High Speed Downlink Packet Access; The high speed downlink packet access) is used to realize WCDMA (Wideband Code Division Multiple Access; WCDMA) network high-speed downlink data service can make descending data rate reach 8～10Mbps.To adopting MIMO (Multiple-Input Multiple-Out-put, multiple-input, multiple-output)) technological HSDPA system, data rate can reach 20Mbps.In the technical scheme of HSDPA, the key technology that relates to mainly comprises four kinds: adaptive coding and modulating, HARQ (Hybrid-ARQ mixes automatic repeat requests) technology, FCS (FrameCheck Sequence, honeycomb is selected fast), MIMO antenna processing.
The definition of HARQ mechanism itself is with FEC (Forward Error Correction; Forward error correction) and ARQ (Auto Repeat Request; Automatically a kind of error-control schemes that repeat requests) technology combines is meant that the recipient under the situation of decoding failure, preserves the data that receive; And requiring the transmit leg data retransmission, the recipient made up data that retransmit and the data that before received before decoding.Mix automatic retransmission technique and can improve systematic function, and can adjust effective code element speed flexibly, can also compensate because the error code that adopts link adaptation to bring.
HSDPA combines to obtain better link self adaptation effect with AMC (Adaptive Modulation and Coding, adaptive modulation and coding) with the HARQ technology.HSDPA provides rough data rate selection scheme through AMC earlier, and then uses the HARQ technology that accurate rate adaptation is provided, thereby improves precision and resource utilization that self adaptation is regulated.HARQ has soft merging (Soft Combing) and two kinds of operational modes of IR (Incremental Redundancy, incremental redundancy).The data of soft folding when retransmitting are identical during with first emission, and the IR technology when retransmitting data with last time launched differently, its performance is better than soft folding, but receiving terminal then need be bigger internal memory.
Be illustrated in figure 1 as the functional schematic of HS-PDSCH (High-Speed Physical Downlink Shared Channel, High-Speed Physical Downlink Shared Channel).The HARQ function comprises twice rate-matched and a virtual cache.Wherein, rate-matched module 101 matches virtual I R buffer memory 102 with the input bit number for the first time, and virtual cache is disposed by high level.If the input bit number is no more than the ability of virtual I R buffer memory 102, this step is transparent so.Bit number after the rate-matched module 103 general's rate-matched first time matches total bit number of whole HS-PDSCH physical channel set among this TTI for the second time.104 is the bit separation module, and 105 is the bit collection module.
At receiving terminal, need the relative set bit collection, go secondary rate coupling, HARQ to store and go these four modules of rate-matched.Wherein, go rate-matched to adopt software control usually, adopt the serial process mode.Present HARQ realizes that function treatment speed is slow, can not adapt to the express network transmission.
Summary of the invention
Embodiments of the invention provide method of reseptance and the device of a kind of HARQ, can improve the processing speed that existing HARQ realizes function.
Embodiments of the invention adopt following technical scheme:
The receiving system of a kind of HARQ comprises:
The bit collection unit is used to read the bit sequence after the deinterleaving, accomplishes the conversion of address and also exports said bit sequence;
Remove the secondary rate matching unit, be used for the bit sequence of said bit collection unit output is gone the secondary rate coupling;
Memory cell is used to store the said bit sequence that goes the output of secondary rate matching unit, and control and line output are gone to first time rate matching system position, go first time rate to mate first check digit, gone first time rate to mate the bit of second check digit;
Remove the first time rate matching unit, be used for the bit of said memory cell and line output is gone the first time rate coupling.
The method of reseptance of a kind of HARQ of another embodiment of the present invention comprises:
The bit sequence that reads after the deinterleaving carries out the conversion and the output of address;
Bit sequence to said output goes the secondary rate coupling;
Store the said bit sequence that goes after secondary rate is mated, control walks abreast and obtains and export first time rate matching system position, goes first time rate to mate first check digit, goes first time rate to mate the bit of second check digit;
Bit to said and line output goes the first time rate coupling.
The method of reseptance of the HARQ that the embodiment of the invention provides and device; Through parallel going to first time rate matching system position, go first time rate to mate first check digit, going first time rate to mate the bit of second check digit of needing when obtaining the first time rate coupling; Thereby the parallel processing that can go first time rate to mate; Solve the processing speed problem of high speed HSDPAHARQ, reduce the processing time-delay of row decoding under the HSDPA.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the dispensing device sketch map of HARQ;
Fig. 2 is the sketch map of the receiving system of embodiments of the invention HARQ;
Fig. 3 is the sketch map of the receiving system of another embodiment of the present invention HARQ;
Fig. 4 is the sketch map of the receiving system of an embodiment HARQ more of the present invention;
Fig. 5 is the storage inside sketch map of embodiments of the invention single port RAM;
Fig. 6 is the electrical block diagram of embodiments of the invention peek control module;
Fig. 7 is the method for reseptance flow chart of embodiments of the invention HARQ.
Embodiment
Below in conjunction with accompanying drawing the method and apparatus that embodiment of the invention HARQ receives is described in detail.
Should be clear and definite, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
As shown in Figure 2, the receiving system of a kind of HARQ of embodiments of the invention comprises:
Remove secondary rate matching unit 22, be used for the bit sequence of said bit collection unit output is gone the secondary rate coupling;
Remove first time rate matching unit 24, be used for the bit of said memory cell 23 and line output is gone the first time rate coupling.
As shown in Figure 3, in a preferred embodiment of the present invention, on the basis of the foregoing description, said memory cell 23 comprises: cache module 231 and peek control module 232.
Wherein cache module 231 is used for the said bit sequence of secondary rate matching unit 22 outputs that goes is stored.Peek control module 232 be used for from the bit sequence of said cache module 231 storages parallel read and export saidly remove first time rate matching system position S, go first time rate to mate the first check digit P1, go first time rate to mate the bit of the second check digit P2.
Present embodiment carries out buffer memory through removing the bit sequence after secondary rate is mated; And before going the first time rate coupling; Parallelly read and export first time rate matching system position, go first time rate to mate first check digit, go first time rate to mate the bit of second check digit through peek control module 232; Avoided when going the first time rate coupling, need reading three bit sequentially, reduced the time-delay that HARQ handles thereby improved the efficient of going the first time rate coupling.
As shown in Figure 4, in another preferred embodiment of the present invention, on the basis of the foregoing description, said memory cell 23 comprises: storage control module 233, cache module 231, queuing control module 234 and peek control module 232.
Wherein storage control module 233, be used for bit sequence in current reception and be new biography the time, store said bit sequence into said cache module; When the bit sequence of current reception is to retransmit, the bit sequence identical with bit sequence said re-transmission that store in the bit sequence of said re-transmission and the said cache module merged, and the bit sequence after will merging stores said cache module into.Particularly, said storage control module 221 comprises:
Judge module 2331, the bit sequence that is used to judge current reception be new biography or retransmit; If new biography, then the said bit sequence that goes secondary rate matching unit 22 to export is input to said cache module 231 and stores; If retransmit, then the bit sequence with current reception outputs to re-transmission merging module 2333 and notifies the 4th peek control module 2332;
The 4th peek control module 2332 is used for from the bit sequence of said cache module 231 storages, reading and output outputs to the identical bit sequence of bit sequence that said re-transmission merges module 2333 with said judging unit 2331;
Said re-transmission merges module 2333, is used for the bit sequence of said the 4th peek control module 2332 outputs and the bit sequence of said judge module 2331 outputs are merged, and exports the bit sequence after merging;
Write numerical control control module 2334, be used for bit sequence after the merging that bit ordered series of numbers or said re-transmission with 2331 outputs of said judge module merge module 2333 outputs and go here and there and change, and output to said cache module 231 and store.
Writing the bit sequence of numerical control control module 2334 after will going here and there and change outputs to before said cache module 231 stores; Need file a request to queuing control module 234, and bit ordered series of numbers or the bit sequence after the said merging of being controlled the new biography of said judge module 2331 outputs by queuing control module 234 store in the cache module 231.Write numerical control control module 2334 and can initiate once to write the number request to queuing control module 234, promptly require the bit sequence that receives is stored in the said cache module 231 when the data that receive reach some.
Peek control module 232, be used for from the bit sequence of said cache module 231 storages parallel read and export saidly remove first time rate matching system position S, go first time rate to mate the first check digit P1, go first time rate to mate the bit of the second check digit P2.Said peek control module 232 comprises: the first peek control module, the second peek control module and the 3rd peek control module.Wherein, the first peek control module is used for from the bit sequence of said cache module 231 storages, reading and export the said bit that removes first time rate matching system position S; The first peek control module is used for from the bit sequence that said cache module is stored, walking abreast and reads and export the said bit that goes first time rate to mate the first check digit P1; The 3rd peek control module is used for from the bit sequence of said cache module 231 storages, walking abreast and reads and export the said bit that goes first time rate to mate the second check digit P2.
When peek control module 232 reading of data; Also will file a request, thereby row is to control module 234 can will peek control module 232, the 4th peek control module 2332 and write the reading of numerical control control module 2334 or write number and ask to sort to queuing control module 2334.
Cache module described in the present embodiment 231 can be single port RAM.As shown in Figure 5, each process takies independently buffer zone in RAM, and in the inside of a process, the bit of system bits S, the first check digit P1 and the second check digit P2 is a separate storage.Wherein process_0～process_n representes 0～n process, and process_0_len～process_n_len representes each process shared length in RAM.In order to reduce the number of times of visit RAM, improve the throughput of RAM visit, be spliced into the bit wide of 48 bits to 8 soft values (6 bit bit wide) as RAM.When writing data, writing RAM after the data that are spliced into 1 48 bit bit wide after 8 data and the string commentaries on classics; When sense data, from RAM, read 8 data 1 time, doing and going here and there changes back output.
In the above-described embodiments; In order to improve processing speed; Reduce because data read and interrupt the processing time-delay that causes, each peek control module (comprise the first peek control module, the second peek control module and the 3rd peek control module in the peek control module 232, and the 4th peek control module 2332) adopts " prefectching " mechanism; First reading of data from RAM in advance before at every turn needing reading guarantees that data processing flowing water is not interrupted.As shown in Figure 6, the said first peek control module, the second peek control module, the 3rd peek control module and the 4th peek can comprise in the control module: the reading modules A with deposit module B;
The said module B that deposits is used to deposit and export the bit that said reading modules A reads;
Said reading modules A is used for reading corresponding bit and being input to the said module B that deposits to said cache module 231 in said bit output back of depositing module B.
As long as deposit the bit output among the module B, then said reading modules A then reads corresponding bit and is input to the said module B that deposits from said cache module 231.For example; If the bit of depositing among the module B in the first peek control module is exported; Then the reading modules A in the first peek control module reads first time rate matching system position S to said cache module 231 immediately, thereby has realized the prefectching function, has guaranteed that data processing is not interrupted.The implementation of other peek control module is similar.
As shown in Figure 6, the circuit of each control module of peeking mainly inputs or outputs signal through following 8 and realizes the prefectching function:
1, enable signal.As the switch of peek control module, peek control module work when enable signal is opened.
2, reading request signal.To the control signal of queuing control module initiation reading request, send a control wave in the time of new data need being read at every turn.
3, read response signal.It is corresponding to read corresponding signal and reading request signal, and the queuing control module is sent a response impulse when the reading request of peek control module meets with a response.
4, starting address signal.Initial address when this signal is initiated a collection of data and read for the peek control module.
5, read address signal.This signal is the current address that needs visit RAM of peek control module, obtains to read address signal behind the secondary response at every turn and adds 1 automatically.
6, reading data signal.The data of this signal for from RAM, reading.
7, outputting data signals.The data that this signal reads the data from RAM for the peek control module are carried out and are gone here and there and change the data that export the back.
8, reading enable signal.This signal is for carry out the enable signal of read operation at every turn.
Peek control module set inside 2 groups of registers: table tennis register and pang register, table tennis register are responsible for the data of buffer memory from the input of queuing control module, pang register be responsible for and the string conversion before the buffer memory of data.When the peek control module enables work, when in the table tennis register, not having data, will initiate the single reading request to the queuing control module.When the data of pang register are carried out and go here and there conversion and transmission end, will read new data from the table tennis register, and to the register zero clearing.Enable when effective at reading, output function is read in one of every completion, and mould 8 counters add 1, and selects from pang register, to select a data output according to the value of mould 8 counters.
Embodiments of the invention adopt single port RAM to realize the HARQ caching function, solve single port RAM access conflict problem.
Because service rate is high, need the data volume of processing big, the processing time-delay of HSDPA also is a difficult point during realize at the terminal.Embodiments of the invention are through the reasonable control to the HARQ buffer memory; Reduced because the processing time-delay that cache read is fetched data and caused; Guarantee to go secondary rate coupling and go first time rate coupling parallel processing and handle flowing water and do not interrupted, reduced the time-delay that HARQ handles.The following two kinds of methods of main in an embodiment of the present invention employing: 1, in going the first time rate matching treatment, adopt the realization mechanism of the bit parallel processing of system bits S, the first check digit P1, the second check digit P2; 2, adopt " prefectching " mechanism to going the secondary rate coupling and going to first time rate data matching source to read, guarantee to go the secondary rate coupling and go the flowing water of first time rate coupling not have Interrupt Process.
In addition; Embodiments of the invention adopt a kind of implementation structure to support two kinds of HARQ that stipulate in the 3GPP agreement to retransmit mode; Comprise Chase Combine (Chase merging) and Increment Combine (incremental redundancy merging) re-transmission mode, simplified the structure of HARQ receiving system, provide cost savings.
As shown in Figure 7, embodiments of the invention also provide the method for reseptance of a kind of HARQ, comprising:
S71, the bit sequence that reads after the deinterleaving carry out the conversion and the output of address;
S72, the bit sequence of said output is gone the secondary rate coupling;
S73, the said bit sequence that goes after secondary rate is mated of storage, control walks abreast and obtains and export first time rate matching system position, goes first time rate to mate first check digit, goes first time rate to mate the bit of second check digit;
S74, the bit of said and line output is gone the first time rate coupling.
Embodiments of the invention are through to going to first time rate matching system position, go first time rate to mate first check digit, go bit that first time rate is mated second check digit to walk abreast to read output, thereby can reduce the time-delay that HARQ handles.
On the basis of the foregoing description, step S73 specifically can for: the bit sequence of judging current reception be new biography or retransmit; If new biography, then go the bit sequence after secondary rate is mated to store with said; If retransmit, then obtain that stored the identical bit sequence and the bit sequence of current reception and merge, and the bit sequence after will merging is stored with bit sequence said current reception.
Wherein saidly go the bit sequence after the secondary rate coupling to store with said; Bit sequence after maybe will merging store specifically can for: go bit sequence or the bit sequence after the said merging after the secondary rate coupling to go here and there and change with said, and store.
In addition, the method for reseptance of embodiments of the invention HARQ further comprises: following each operation is sorted:
Obtain and saidly remove first time rate matching system position S, go first time rate to mate the first check digit P1, go first time rate to mate the bit of the second check digit P2;
Obtain that stored identical bit sequence with bit sequence said current reception;
The said bit sequence of secondary rate coupling back output that goes is stored, and the bit sequence after maybe will merging is stored.
In addition, go in the embodiments of the invention first time rate matching system position, go first time rate mate first check digit, go first time rate mate second check digit bit obtain the method that can adopt prefectching.To go the example that is retrieved as of first time rate matching system position,, then obtain the next one immediately and go to first time rate matching system position subsequent use if export the previous first time rate matching system position of going.Thereby can guarantee that data processing is not interrupted.Go first time rate to mate first check digit, go the obtaining of bit that first time rate is mated second check digit then to adopt similar method.
The method of reseptance of embodiments of the invention HARQ is in going the first time rate matching treatment; Adopt the realization mechanism of system bits S, the first check digit P1, the second check digit P2 parallel processing; And through adopting " prefectching " mechanism to going the secondary rate coupling and going to first time rate data matching source to read; Assurance is gone the secondary rate coupling and is gone the flowing water of first time rate coupling not have Interrupt Process, thereby can reduce the time-delay that HARQ handles.In addition; Embodiments of the invention can support two kinds of HARQ that stipulate in the 3GPP agreement to retransmit mode; Comprise Chase Combine (Chase merging) and Increment Combine (incremental redundancy merging) re-transmission mode; The method that adopts embodiments of the invention to provide can be simplified the structure of HARQ receiving system, saves cost.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (12)
1. a receiving system that mixes automatic repeat requests is characterized in that, comprising:
The bit collection unit is used to read the bit sequence after the deinterleaving, accomplishes the conversion of address and also exports said bit sequence;
Remove the secondary rate matching unit, be used for the bit sequence of said bit collection unit output is gone the secondary rate coupling;
Memory cell is used to store the said bit sequence that goes the output of secondary rate matching unit, and control and line output are gone to first time rate matching system position, go first time rate to mate first check digit, gone first time rate to mate the bit of second check digit;
Remove the first time rate matching unit, be used for the bit of said memory cell and line output is gone the first time rate coupling.
2. receiving system according to claim 1 is characterized in that, said memory cell comprises:
Cache module is used for the said bit sequence of secondary rate matching unit output that goes is stored;
The peek control module, be used for from the bit sequence that said cache module is stored parallel read and export saidly go to first time rate matching system position, go first time rate to mate first check digit, go first time rate to mate the bit of second check digit.
3. receiving system according to claim 2 is characterized in that, said peek control module comprises:
The first peek control module is used for from the bit sequence that said cache module is stored, reading and exporting the said bit that goes to first time rate matching system position;
The second peek control module is used for from the bit sequence that said cache module is stored, walking abreast and reads and export the said bit that goes first time rate to mate first check digit;
The 3rd peek control module is used for from the bit sequence that said cache module is stored, walking abreast and reads and export the said bit that goes first time rate to mate second check digit.
4. receiving system according to claim 3 is characterized in that, said memory cell also comprises:
Storage control module, be used for bit sequence in current reception and be new biography the time, the bit sequence of said new biography is stored; When the bit sequence of current reception is to retransmit, the bit sequence identical with bit sequence said re-transmission that store in the bit sequence of said re-transmission and the said cache module merged, and the bit sequence after will merging stores said cache module into.
5. receiving system according to claim 4 is characterized in that, said storage control module comprises:
Judge module, the bit sequence that is used to judge current reception be new biography or retransmit; If new biography, then the said bit sequence that goes the secondary rate matching unit to export is input to said cache module and stores; If retransmit, then the bit sequence with current reception outputs to re-transmission merging module and notifies the 4th peek control module;
The 4th peek control module is used for from the bit sequence that said cache module is stored, reading and output outputs to the identical bit sequence of bit sequence that said re-transmission merges module with said judge module;
Said re-transmission merges module, is used for the bit sequence that the bit sequence of said the 4th peek control module output and said judge module are exported is merged, and outputs to said cache module and store.
6. receiving system according to claim 5 is characterized in that, the said first peek control module, the second peek control module, the 3rd peek control module or the 4th peek control module comprise: the reading module with deposit module;
The said module of depositing is used to deposit and export the bit that said reading module reads;
Said reading module is used for reading corresponding bit and being input to the said module of depositing to said cache module in said bit output back of depositing module.
7. receiving system according to claim 5 is characterized in that, said memory cell also comprises:
The queuing control module is used for the reading request of the said first peek control module, the second peek control module, the 3rd peek control module and the 4th peek control module is sorted.
8. receiving system according to claim 7 is characterized in that,
Said storage control module also comprises: write the numerical control control module; Bit sequence after merging new biography or that retransmit merge cells output that is used for said judge module is exported is gone here and there and is changed, and the bit sequence after the request of queuing control module is with said string and conversion stores said cache module into;
Said queuing control module also is used for the reading request of the said request of writing the numerical control control module and the said first peek control module, the second peek control module, the 3rd peek control module and the 4th peek control module is sorted.
9. according to each described receiving system in the claim 2 to 8, it is characterized in that said cache module is single port RAM.
10. a method of reseptance that mixes automatic repeat requests is characterized in that, comprising:
The bit sequence that reads after the deinterleaving carries out the conversion and the output of address;
Bit sequence to said output goes the secondary rate coupling;
Store the said bit sequence that goes after secondary rate is mated, control walks abreast and obtains and export first time rate matching system position, goes first time rate to mate first check digit, goes first time rate to mate the bit of second check digit;
Bit to said and line output goes the first time rate coupling.
11. method of reseptance according to claim 10 is characterized in that, stores the said bit sequence that goes after secondary rate is mated, and comprising:
The bit sequence of judging current reception be new biography or retransmit; If new biography, then the said bit sequence of secondary rate coupling back output that goes is stored; If retransmit, then obtain that stored the identical bit sequence and the bit sequence of current reception and merge, and the bit sequence after will merging is stored with bit sequence said current reception.
12. method of reseptance according to claim 11 is characterized in that,
Said the said bit sequence of secondary rate coupling back output that goes is stored; Bit sequence after maybe will merging is stored and is comprised: the said bit sequence that goes secondary rate coupling back output or the bit sequence after the said merging are gone here and there and changed, and store.
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| CN102118219B (en) * | 2010-01-06 | 2014-09-10 | 中兴通讯股份有限公司 | Serial processing method and serial processing device for rate matching |
| CN102208966B (en) * | 2010-03-30 | 2014-04-09 | 中兴通讯股份有限公司 | Hybrid automatic repeat request (HARQ) combiner and HARQ data storage method |
| CN102694634A (en) * | 2011-03-23 | 2012-09-26 | 中兴通讯股份有限公司 | Method for processing hybrid automatic repeat request data combination, device thereof and system thereof |
| CN103248454B (en) * | 2012-02-10 | 2016-04-06 | 展讯通信（上海）有限公司 | Coding/decoding method in communication system and decoding device, communication terminal |
| CN106878012B (en) * | 2016-12-07 | 2019-07-16 | 中国电子科技集团公司第三十研究所 | A kind of wireless channel physical layer key agreement and inconsistent bit minimizing technology |
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