CN101106440B - A method and device for collection and interweaving of mixed automatic retransfer request - Google Patents

Abstract

The invention discloses a hybrid automatic repeat request bit collecting and interleaving method and a means. The means thereof comprise a bit collecting fore-FIFO buffer unit, which comprises a system bit FIFO, a check (1) bit FIFO and a check (2) bit FIFO; and a bit collecting control unit, a physical channel interleaving and output control unit, wherein the bit collecting fore-FIFO buffer unit is applied to match the difference between the forestage rate matching and the processing speed of bit collecting and interleaving; the bit collecting control unit is applied for controlling to read out the corresponding column data; the physical channel interleaving and output control unit is applied to obtain the address of each bit in the final physical channel flow by transforming channel flow addresses processed by bit collecting. The method and means in the invention utilize three FIFO buffer structures, which reduces the storage resources of circuit, and reduces the corresponding logical resources by using the combination simplifying the HARQ bit collection write-in order.

Description

The automatic repeat requests bit collection of a kind of mixing and interweaving method and device

Technical field

The present invention relates to a kind of 3-G (Generation Three mobile communication system) and method thereof, specifically, relate to the automatic repeat requests HARQ bit collection of mixing and the interweaving method and the device of the high speed downlink packet access of a kind of broadband CDMA system (WCDMA).

Background technology

Wideband CDMA (WCDMA) is one of main flow system of the third generation (3G) mobile communication system.Wherein the HSDPA of R5 version proposition (High Speed Downlink Packet Access, high speed downlink packet inserts) technology has become current research focus.The HSDPA technology is to realize improving the of paramount importance technology of WCDMA network high-speed downlink message transmission rate, be that 3GPP puts forward in order to satisfy the asymmetric demand of up-downgoing data service in the R5 agreement, it can be on the basis that does not change the WCDMA system network architecture of having built, improve user's downstream data traffic speed greatly, can reach more than the 10Mbps, this technology is to improve a kind of important technology of downlink capacity and data service rate in the WCDMA networking.

The HSDPA technology is by AMC (Adaptive Modulation and Coding, automatic modulation control, hereinafter to be referred as AMC) and H-ARQ (mix automatic repeat requests, hybrid automatic repeat request, hereinafter to be referred as HARQ) technology increases the throughput and the peak-data rates of transfer of data on the basis that reduce to postpone, for the multi-user provides the high-speed down data service.The principle of AMC technology is the pattern that changes modulation, coded system, code block size according to the variation of channel situation.HARQ is a kind of link adaptation techniques, and ARQ is an automatic repeat request, and HARQ is with forward error correction coding (FEC) and the automatic technology that combines of repeat requests (ARQ).

In order to realize the functional characteristic of HSDPA, three down physical channel: HS-DSCH, HS-SCCH, HS-DPCCH in the 3GPP physical layer specification, have been introduced.Wherein HS-DSCH (high speed descending sharing channel) is used for UMTS (Universal mobile terrestrial system) communication system carries downlink user data.

Provided the flow chart of HS-DSCH chnnel coding chain as shown in Figure 1, compare with the Release99 standard, the chnnel coding of HS-DSCH among the R5 is simplified, and the HS-DSCH transmission channel fixed number of activation is 1, therefore no longer needs the transmission channel Multiplexing module with same user; And interleave depth is 2ms, is not further divided into intra-frame interleaving and interframe interweaves; The type of chnnel coding is fixed as the Turbo coding.104 parts as shown in fig. 1 are the HARQ module, and it is the main distinction of Release 5 and Release99.

Provided the HARQ functional block diagram of prior art as shown in Figure 2.The function of HARQ is finished by two-stage rate-matched functional module, and wherein buffer 203 is positioned at two rate-matched interproceduals, can be used for adjusting the different redundant configuration that retransmit.Rate-matched is mated input bit number and virtual I R buffering for the first time, if the input bit number does not surpass the buffer memory ability of virtual I R buffering, rate-matched transparent transmission for the first time.For the second time rate-matched is that bit number after the first time rate-matched and the bit number capacity of a TTI of HS-DSCH channel set are mated.

The bit collection module 205 of HARQ as shown in Figure 2, the HARQ bit collection is a N _Row* N _ColThe matrix interleaver.N _RowBe the line number of interleaver matrix, N _ColColumns for interleaver matrix;

16QAM：N _row＝4，QPSK：N _row＝2；

N _col＝N _data/N _row；

N _DataThe total amount of the HS-DSCH bit number of a TTI of expression;

N _{T, sys}The figure place of representing the systematic bits that will send after the rate-matched second time;

Definition: intermediate variable Nr, Nc;

N _c＝N _t，sys-N _r·N _col.

If Nc=0 and Nr＞0, systematic bits writes the 1st ... Nr is capable;

Otherwise if Nr＞0, systematic bits writes 1 successively ... the preceding Nc row and 1 that Nr+1 is capable ... the Ncol-Nc row that Nr is capable.

Check bit writes the remaining space of matrix.Verification 1, verification 2 alternately write, and verification 2 writes earlier, from the minimum row of remaining space.

During the 16QAM modulation, bit stream is followed successively by the row 1,2,3,4 of first row by row output, the row 1,2,3,4 of secondary series,

During the QPSK modulation, bit stream is followed successively by the row 1,2 of first row by row output, the row 1,2 of secondary series,

Provided the schematic diagram of the HARQ bit collection bit write sequence of prior art as shown in Figure 3, it comprises QPSK modulation and 16QAM modulation.Wherein the QPSK modulation comprises that the systematic bits number is zero, shown in Fig. 3 a; Systematic bits number deficiency delegation is odd number, shown in Fig. 3 b; Systematic bits number deficiency delegation is even number, shown in Fig. 3 c; Systematic bits just is a delegation, shown in Fig. 3 d; Systematic bits is odd number more than delegation, shown in Fig. 3 e; The systematic bits number is even number more than delegation, shown in Fig. 3 f; The systematic bits number just in time is two row, shown in Fig. 3 g.

The 16QAM modulation comprises that the systematic bits number is zero, shown in Fig. 3 h; Systematic bits number deficiency delegation is odd number, shown in Fig. 3 i; Systematic bits number deficiency delegation is even number, shown in Fig. 3 j; Systematic bits just is a delegation, shown in Fig. 3 k; Systematic bits is less than two row more than delegation, is odd number, shown in Fig. 3 l; The systematic bits number is less than two row more than delegation, is even number, shown in Fig. 3 m; The systematic bits number just in time is two row, shown in Fig. 3 n; Systematic bits is less than triplex row more than two row, is odd number, shown in Fig. 3 o; The systematic bits number is less than triplex row more than two row, is even number, shown in Fig. 3 p; The systematic bits number just in time is a triplex row, shown in Fig. 3 q.Systematic bits is less than four lines more than triplex row, is odd number, shown in Fig. 3 r; The systematic bits number is less than four lines more than triplex row, is even number, shown in Fig. 3 s; The systematic bits number just in time is a four lines, shown in Fig. 3 t.

Provided the HS-DSCH physical channel interleave function structured flowchart of prior art as shown in Figure 4, data flow after the bit collection is continuous data flow, the principle of listing according to advancing according to the pattern that interweaves of 3GPP regulation, flows to the physical channel interleaver matrix and finishes and interweave.With 960 (QPSK) or the individual bit of 1920 (16QAM) is one group.

From above-mentioned flow process, there are following defective in the HARQ bit collection and the interweaving method of prior art as can be seen:

1) after the rate-matched second time, the sequencing of systematic bits, verification 1 bit and verification 2 bit process is inconsistent, and wherein systematic bits number maximum possible is 28800bits, and verification 1 bit and verification 2 bit number maximums are 14400bits.During bit collection, need to increase a bigger storage resources and make buffer memory.

2) it is more that bit collection writes the possibility of order of buffer memory, if carry out sort operation one by one according to the existing possibility that exists, can cause the waste logical resource, increases circuit area.

3) after bit collection was finished, bit stream came buffer memory by row output, imported next stage physics Bit Interleave again and handled operation, had increased the time that postpones.

Therefore, there is defective in prior art, and awaits improving and development.

Summary of the invention

The object of the present invention is to provide the automatic repeat requests bit collection of a kind of mixing and interweaving method and device, to reduce the delay process time.

Technical scheme of the present invention comprises:

A kind of device that mixes automatic repeat requests bit collection and interweave, wherein, it comprises the preceding FIFO buffer unit of bit collection, bit collection control unit, physical channel interweave and output control unit; Wherein, the FIFO buffer unit further comprises systematic bits FIFO, verification 1 bit FIFO and verification 2 bit FIFO before the described bit collection; Wherein,

The FIFO buffer unit is used to mate rate-matched speed and bit collection and the processing speed that interweaves afterwards for the second time before the described bit collection;

Described bit collection control unit is used for the line number Nrow according to the given interleaver matrix of system, the columns Ncol of interleaver matrix, and by intermediate variable Nc, Nr that line number and columns calculate, reads corresponding columns certificate by the control of bit collection method;

Described physical channel interweaves and output control unit, is used for obtaining the address of each bit in the final physical channel flow by conversion is carried out in the channel flow address after the bit collection and treatment; Wherein, described physical channel interweave and output control unit according to the address of current bit in data flow, calculate the line number of corresponding physics channel interleaving matrix column number and interleaver matrix, obtain the columns of new interleaver matrix behind the columns column permutation with the physical channel interleaver matrix, according to this columns and the line number that obtained originally, calculate interweave final address in the data flow of back of physical channel.

Described device, wherein, the FIFO that described systematic bits stream, verification 1 bit stream, verification 2 bit streams entered after the rate-matched separately in the second time carries out buffer memory, and respectively this FIFO is a synchronization fifo, and the stage Turbo encoded data stream write before FIFO forbade when full.

Described device, wherein, the width of described respectively this FIFO is 1, the degree of depth is decided by the maximum stream flow of system emulation.

Described device, wherein, described bit collection control unit is used for the line number Nrow according to the given interleaver matrix of system, the columns Ncol of interleaver matrix, and the intermediate variable Nc, the Nr that calculate by line number and columns, read corresponding columns certificate by the control of bit collection method, be specially:

Nrow represents the line number of the interleaver matrix that system is given, the columns that Ncol represents interleaver matrix, N _{T, sys}The figure place of representing the systematic bits that will send after the rate-matched second time, N _c=N _{T, sys}-N _rN _Col, Judge that whether the systematic bits number is zero, if be zero, then replaces reader check 1 bit and verification 2 bits as each columns certificate; If it is non-vanishing, judge then whether the systematic bits number is the integral multiple of interleaver matrix columns, if be integral multiple, then read Nr systematic bits successively as each row 1 ... the data that Nr is capable, check 1 bit and check 2 bits alternately to read the data that are listed as other row as each, if be not integral multiple, then read Nr+1 systematic bits successively as preceding Nc row 1 ... the data that Nr+1 is capable, read Nr systematic bits successively as Ncol-Nc row 1 ... the data that Nr is capable,, verification 1 bit and verification 2 bits are alternately read the data that are listed as other row as each.

Automatic repeat requests bit collection of a kind of mixing and interweaving method, it comprises the following steps:

A, after second time rate-matched, the FIFO that systematic bits stream, verification 1 bit stream, verification 2 bit streams enter separately carries out buffer memory;

B, according to the line number Nrow of the given interleaver matrix of system, the columns Ncol of interleaver matrix, and, control the output of current bit stream by the bit collection method by intermediate variable Nc, Nr that line number and columns calculate; Wherein, N _c=N _{T, Sys}-N _rN _Col,

N _{T, sys}The figure place of representing the systematic bits that will send after the rate-matched second time;

C, the rule that interweaves according to physical channel are carried out conversion to the channel flow address after the bit collection and treatment, promptly directly obtain the address of each bit in the final physical channel flow; Wherein, according to the address of current bit in data flow, calculate the line number of corresponding physics channel interleaving matrix column number and interleaver matrix, obtain the columns of new interleaver matrix behind the columns column permutation with the physical channel interleaver matrix, according to this columns and the line number that obtained originally, calculate interweave final address in the data flow of back of physical channel;

D, repetition above-mentioned steps A～C carry out the input of each bit.

Described method, wherein, described step B also comprises:

B1, judge that whether the systematic bits number is zero,, then be listed as and into list processing according to the situation that check bit stream is only arranged if be zero; If non-vanishing, then enter step B2 handling process;

If the B2 systematic bits is non-vanishing, judge then whether the systematic bits number is the integral multiple of interleaver matrix columns, judge promptly whether Nc is zero, and advance to list processing according to row.

Described method wherein, describedly judges that whether the systematic bits number is zero, if be zero, then be listed as according to the situation that check bit stream is only arranged and into list processing, is specially:

Judge that whether the systematic bits number is zero, if be zero, then replaces reader check 1 bit and verification 2 bits as each columns certificate.

Described method wherein, if systematic bits is non-vanishing, judges then whether the systematic bits number is the integral multiple of interleaver matrix columns, judges promptly whether Nc is zero, and advances to list processing according to row, is specially:

If it is non-vanishing, judge then whether the systematic bits number is the integral multiple of interleaver matrix columns, if be integral multiple, then read Nr systematic bits successively as each row 1 ... the data that Nr is capable, check 1 bit and check 2 bits alternately to read the data that are listed as other row as each, if be not integral multiple, then read Nr+1 systematic bits successively as preceding Nc row 1 ... the data that Nr+1 is capable, read Nr systematic bits successively as Ncol-Nc row 1 ... the data that Nr is capable, verification 1 bit and verification 2 bits are alternately read the data that are listed as other row as each.

Described method, wherein, described step C also comprises:

For each TB data, be divided into P physical channel, suppose that there is U TB a sub-district, each TB takies Pi physical channel, and when adopting the QPSK modulation, the final physical channel flow is defined as 0,1 ..., P1*960-1 ..., (P1+P2+ ... + PU) * 960-1; When adopting the 16QAM modulation, the final physical channel flow is defined as 0,1 ..., P1*1920-1 ..., (P1+P2+ ... + PU) * 1920-1.

Described method, wherein, described step C also comprises:

C1, according to the address of current bit in data flow, calculate the line number of corresponding physics channel interleaving matrix column number and interleaver matrix.

Described method, wherein, described step C also comprises:

Obtain the columns of new interleaver matrix behind C2, the columns column permutation,, calculate interweave final address in the data flow of back of physical channel according to this columns and the line number that obtained originally with the physical channel interleaver matrix.

The automatic repeat requests bit collection of a kind of mixing provided by the present invention and interweaving method and device, owing to utilized the structure of three FIFO buffer memorys, reduced the storage resources of circuit, and the combination of HARQ bit collection write sequence is simplified in utilization, reduce corresponding logical resource, reduced the area of circuit; By calculating the address in the data flow of physical channel after interweaving, direct output bit flow has reduced bit collection and physics time of delay between interweaving, the processing speed of having optimized HARQ bit collection in the HSDPA system and having interweaved.In another embodiment, defective at above-mentioned existence in the prior art, at systematic bits, verification 1 bit and verification 2 bits, the FIFO buffer memory increases corresponding FIFO for each bit stream before the bit collection, the degree of depth of FIFO decides according to the maximum stream flow of system emulation, to reduce storage resources; And adopt the bit collection control of optimizing, merge the combination of HARQ bit collection write sequence, to reduce logical resource consumption.

Description of drawings

Fig. 1 is high speed descending sharing channel (HS-DSCH) the symbol level cataloged procedure schematic diagram of the 3GPP regulation of prior art;

Fig. 2 is the HARQ functional block diagram of prior art;

Fig. 3 is the schematic diagram of the HARQ bit collection bit write sequence of prior art;

Fig. 4 is the HS-DSCH physical channel interleave function structured flowchart of prior art;

Fig. 5 is the functional block diagram of HARQ bit collection of the present invention and interlaced device;

Fig. 6 is HARQ bit collection of the present invention and deinterleaving method flow chart.

Embodiment

Below in conjunction with accompanying drawing, will carry out comparatively detailed explanation to the specific embodiment of method of the present invention and device.

The present invention mixes in automatic repeat requests bit collection and interweaving method and the device, the device that wherein is used for the HARQ bit collection of HSDPA system and interweaves is made up of following components, as shown in Figure 5, wherein this device comprises the preceding FIFO buffer unit 501 of bit collection, bit collection control unit 502, physical channel interweaves and output control unit 503, and FIFO buffer unit 501 comprises systematic bits FIFO, verification 1 bit FIFO and verification 2 bit FIFO before the described bit collection.

The present invention is used for the HARQ bit collection and the interweaving method of HSDPA system, and as shown in Figure 6, it comprises the following steps:

Step 601: flow process begins;

Step 602: after second time rate-matched, the FIFO that systematic bits stream, verification 1 bit stream, verification 2 bit streams enter separately carries out buffer memory.

Step 603: according to the line number Nrow of the given interleaver matrix of system, the columns Ncol of interleaver matrix, and the intermediate variable Nc, the Nr that calculate by line number and columns, control the output of current bit stream by the bit collection method, this method has been simplified the possibility of the sequencing that the input of bit collection data flow handles.

Judge whether the systematic bits number is zero,, then be listed as and into list processing, enter step 605 after finishing dealing with according to the situation that check bit stream is only arranged if be zero.If non-vanishing, then enter step 604 step handling process.

Step 604: if systematic bits is non-vanishing, judge then whether the systematic bits number is the integral multiple of interleaver matrix columns, judge promptly whether Nc is zero, if Nc is zero, represent that then systematic bits is the integral multiple of interleaver matrix columns, enter step 606 after advancing to list processing according to row.If Nc is non-vanishing, the aliquant interleaver matrix columns of systematic bits number then enters step 607 after advancing to list processing according to row.

Step 605,606,607: according to the rule that physical channel interweaves conversion is carried out in the channel flow address after the bit collection and treatment, both directly obtained the address of each bit in the final physical channel flow.For each TB data, be divided into P physical channel, suppose that there is U TB a sub-district, each TB takies Pi physical channel, and then the final physical channel flow is defined as 0,1,, P1*960 (or 1920)-1 ... (P1+P2+ ... + PU) * 960 (or 1920)-1 (QPSK is 960bit, and 16QAM is 1920bit).

Step 608:, calculate the line number of corresponding physics channel interleaving matrix column number and interleaver matrix according to the address of current bit in data flow; Obtain the columns of new interleaver matrix behind the columns column permutation with the physical channel interleaver matrix,, calculate interweave final address in the data flow of back of physical channel according to this columns and the line number that obtained originally.

Repeat above-mentioned steps then, control the input of next bit.

Be the functional block diagram of apparatus of the present invention as shown in Figure 5, wherein FIFO buffer unit 501 before the bit collection is used to mate the different of prime rate-matched and bit collection and the processing speed that interweaves.The FIFO that rate-matched second time systematic bits stream, verification 1 bit stream, verification 2 bit streams afterwards enter separately carries out buffer memory, and this FIFO is a synchronization fifo, and the stage Turbo encoded data stream write before FIFO forbade when full.The width of FIFO is 1, and the degree of depth is decided by the maximum stream flow of system emulation.

Bit collection control unit 502 among Fig. 5, by judging the SYSTEM_BIT_ZERO sign, if this is masked as 0 expression systematic bits number is 0, from verification 1, verification 2 bit FIFO buffer memorys, read each columns certificate then, first row are according to sequencing, read a check bit 2, a check bit 1 according to this, up to the Nrow that reads these a row bit; The rest may be inferred with whole Ncol columns according to till reading.

If the SYSTEM_BIT_ZERO sign is non-vanishing, according to the rule of bit collection sense data from systematic bits, verification 1, verification 2 bit FIFO successively, judge whether Nc is zero, if be zero, this reads Nr systematic bits from first leu, reads a check bit 2, a check bit 1 then, till these row are read Nrow bit, if last position is a check bit 2, then bidding will PARITY2_READ is 0, otherwise is set to 1.

Secondary series is read Nr systematic bits according to this, judge PARITY2_READ, if be 0, then read a check bit 1, a check bit bit 2 according to this, otherwise, then read verification 2 bits according to this, verification 1 bit is till these row are read Nrow bit, if last position is a check bit 2, then bidding will PARITY2_READ is 0, otherwise is set to 1.In like manner, the rest may be inferred with whole Ncol columns according to till reading.

If Nc is non-vanishing, then time read Nr+1 systematic bits from first leu, read a check bit 2, a check bit 1 then, till these row are read Nrow bit, if last position is a check bit 2, then bidding will PARITY2_READ is 0, otherwise is set to 1.Secondary series is read Nr systematic bits according to this, judge PARITY2_READ, if be 0, then read a check bit 1, a check bit bit 2 according to this, otherwise, then read verification 2 bits according to this, verification 1 bit is till these row are read Nrow bit, if last position is a check bit 2, then bidding will PARITY2_READ is 0, otherwise is set to 1.

The rest may be inferred with whole Nc columns according to till reading.

Then, this reads Nr systematic bits the Nc+1 leu, reads a check bit 2, a check bit 1 then, and till these row were read Nrow bit, if last position is a check bit 2, then bidding will PARITY2_READ was 0, otherwise is set to 1.Secondary series is read Nr systematic bits according to this, judge PARITY2_READ, if be 0, then read a check bit 1, a check bit bit 2 according to this, otherwise, then read verification 2 bits according to this, verification 1 bit is till these row are read Nrow bit, if last position is a check bit 2, then bidding will PARITY2_READ is 0, otherwise is set to 1.

The rest may be inferred with whole Ncol columns according to till reading.

The present invention's physical channel as shown in Figure 5 interweaves and controls 503, by conversion is carried out in the channel flow address after the bit collection and treatment, has obtained the address of each bit in the final physical channel flow.

This define certain bit physical channel interweave before address in data flow be N1, the address that is mapped in the data flow after physical channel interweaves is N2, is divided into two kinds of modulation systems of QPSK, 16QAM and is described as follows:

The QPSK modulation system:

Suppose: 960k＜N1＜960* (k+1);

Intermediate variable

Corresponding physics channel interleaving matrix column is counted N _Phc, line number N _Phr

After the column permutation be

$\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="H061A3232520060720E000011.png,H061A3232520060720E000021.png"\; state="\{\{state\}\}">N</figure-callout>}2=(N_{\mathrm{phc}}^{\&prime;}-1)\&times;32+N_{\mathrm{phr}}+960k;$

The 16QAM modulation system:

Suppose: 1920k＜N1＜1920* (k+1);

Intermediate variable

If

Then import the corresponding columns N of first interleaver matrix _{IX, phc}, line number N _{IX, phr}, X=1 represents first interleaver matrix here;

If Then import the corresponding columns N of first interleaver matrix _{IX, phc}, line number N _{IX, phr}, X=2 represents second interleaver matrix here;

After the column permutation be

Be intermediate variable;

Because the data flow after the bit collection is continuous bit stream, remove 30 operation in the aforementioned calculation process, can finish by linage-counter.

Such scheme can be applied to fully realize with the FPGA hardware mode in the HSDPA system, accomplish real-time processing.

The automatic repeat requests bit collection of the above-mentioned mixing that provides of the present invention and interweaving method and device, owing to utilized the structure of three FIFO buffer memorys, reduced the storage resources of circuit, and the combination of HARQ bit collection write sequence is simplified in utilization, reduce corresponding logical resource, reduced the area of circuit; By calculating the address in the data flow of physical channel after interweaving, direct output bit flow has reduced bit collection and physics time of delay between interweaving, the processing speed of having optimized HARQ bit collection in the HSDPA system and having interweaved.

But should be understood that above-mentioned description at specific embodiment is comparatively detailed, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.

Claims (4)

1. a device that mixes automatic repeat requests bit collection and interweave is characterized in that, it comprises the preceding FIFO buffer unit of bit collection, and bit collection control unit, physical channel interweave and output control unit; Wherein, the FIFO buffer unit further comprises systematic bits FIFO, verification 1 bit FIFO and verification 2 bit FIFO before the described bit collection; Wherein,

The FIFO buffer unit is used to mate rate-matched speed and bit collection and the processing speed that interweaves afterwards for the second time before the described bit collection;

Described bit collection control unit is used for the line number Nrow according to the given interleaver matrix of system, the columns Ncol of interleaver matrix, and the intermediate variable Nc, the Nr that calculate by line number and columns, read corresponding columns certificate by the control of bit collection method, be specially: N _{T, sys}The figure place of representing the systematic bits that will send after the rate-matched second time, N _c=N _{T, sys}-N _rN _Col,

Judge that whether the systematic bits number is zero, if be zero, then replaces reader check 1 bit and verification 2 bits as each columns certificate; If it is non-vanishing, judge then whether the systematic bits number is the integral multiple of interleaver matrix columns, if be integral multiple, then read Nr systematic bits successively as each row 1 ... the data that Nr is capable, check 1 bit and check 2 bits alternately to read the data that are listed as other row as each, if be not integral multiple, then read Nr+1 systematic bits successively as preceding Nc row 1 ... the data that Nr+1 is capable, read Nr systematic bits successively as Ncol-Nc row 1 ... the data that Nr is capable, verification 1 bit and verification 2 bits are alternately read the data that are listed as other row as each;

Described physical channel interweaves and output control unit, is used for obtaining the address of each bit in the final physical channel flow by conversion is carried out in the channel flow address after the bit collection and treatment; Wherein, described physical channel interweave and output control unit according to the address of current bit in data flow, calculate the line number of corresponding physics channel interleaving matrix column number and interleaver matrix, obtain the columns of new interleaver matrix behind the columns column permutation with the physical channel interleaver matrix, according to this columns and the line number that obtained originally, calculate interweave final address in the data flow of back of physical channel.

2. device according to claim 1, it is characterized in that, the FIFO that described systematic bits stream, verification 1 bit stream, verification 2 bit streams entered after the rate-matched separately in the second time carries out buffer memory, and respectively this FIFO is a synchronization fifo, and the stage Turbo encoded data stream write before FIFO forbade when full.

3. device according to claim 2 is characterized in that, the width of described respectively this FIFO is 1, and the degree of depth is decided by the maximum stream flow of system emulation.

4. one kind is mixed automatic repeat requests bit collection and interweaving method, and it comprises the following steps:

A, after second time rate-matched, the FIFO that systematic bits stream, verification 1 bit stream, verification 2 bit streams enter separately carries out buffer memory;

B, according to the line number Nrow of the given interleaver matrix of system, the columns Ncol of interleaver matrix, and the intermediate variable Nc, the Nr that calculate by line number and columns control the output of current bit stream by the bit collection method, are specially: N _{T, sys}The figure place of representing the systematic bits that will send after the rate-matched second time, N _c=N _{T, sys}-N _rN _Col, Judge that whether the systematic bits number is zero, if be zero, then replaces reader check 1 bit and verification 2 bits as each columns certificate; If it is non-vanishing, judge then whether the systematic bits number is the integral multiple of interleaver matrix columns, if be integral multiple, then read Nr systematic bits successively as each row 1 ... the data that Nr is capable, check 1 bit and check 2 bits alternately to read the data that are listed as other row as each, if be not integral multiple, then read Nr+1 systematic bits successively as preceding Nc row 1 ... the data that Nr+1 is capable, read Nr systematic bits successively as Ncol-Nc row 1 ... the data that Nr is capable, verification 1 bit and verification 2 bits are alternately read the data that are listed as other row as each;

C, the rule that interweaves according to physical channel are carried out conversion to the channel flow address after the bit collection and treatment, promptly directly obtain the address of each bit in the final physical channel flow; Wherein, according to the address of current bit in data flow, calculate the line number of corresponding physics channel interleaving matrix column number and interleaver matrix, obtain the columns of new interleaver matrix behind the columns column permutation with the physical channel interleaver matrix, according to this columns and the line number that obtained originally, calculate interweave final address in the data flow of back of physical channel;

D, repetition above-mentioned steps A～C carry out the input of each bit.

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