CN101488309B - Driving circuit board, driving system and driving method for flat display device - Google Patents
Driving circuit board, driving system and driving method for flat display device Download PDFInfo
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- CN101488309B CN101488309B CN2008100033300A CN200810003330A CN101488309B CN 101488309 B CN101488309 B CN 101488309B CN 2008100033300 A CN2008100033300 A CN 2008100033300A CN 200810003330 A CN200810003330 A CN 200810003330A CN 101488309 B CN101488309 B CN 101488309B
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- schedule controller
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Abstract
The invention discloses a driving circuit board of a flat panel display device, comprising a baseplate, a first time schedule controller, a second time schedule controller and at least a first metal wire. The circuit board is characterized in that the baseplate is equipped with a first surface and a second surface which is opposite to the first surface, the first time schedule controller with at least a first input end is positioned on the first surface of the baseplate, the second time schedule controller with at least a second input end is positioned on the second surface of the baseplate, wherein the second input end and the first input end of the first time schedule controller are arranged in the opposite directions; through the baseplate, the first metal wire is respectively connected with the first input end and the second input end electrically. The invention also discloses a drive system and a drive method of the flat panel display device.
Description
Technical field
The invention relates to a kind of drive circuit board, drive system and driving method of display device, especially in regard to a kind of drive circuit board, drive system and driving method of flat display apparatus.
Background technology
In recent years; Because the development of display technique; Traditional cathode ray display device is replaced by flat display apparatus gradually, and in general, mostly flat display apparatus is plasma display system (Plasma Display Panel; PDP) or liquid crystal indicator (Liquid Crystal Display, LCD).Wherein, Build is frivolous because of having for liquid crystal indicator, low power consumption and advantageous characteristic such as radiationless; Be applied to the electronic product of numerous species, for example notebook computer (NoteBook, NB), LCD TV (LCD TV) and LCD screen (LCD Monitor) or the like.
Please with reference to shown in Figure 1, a kind of existing liquid crystal indicator comprises a liquid crystal panel 1 and one drive circuit plate 2, and scan line drive circuit (scan line driving circuit) 11, multi-strip scanning line 12 are set
1-12
m, a data line drive circuit (data line driving circuit) 13, many data lines 14
1-14
nAnd a pixel array region 15, wherein scan line drive circuit 11 comprises a plurality of shift registers 111, and data line drive circuit 13 comprises a plurality of shift registers 131 and a plurality of sampling/retainer 132.Drive circuit board 2 comprises time schedule controller (timing controller) 21 and one image processor 22.
A plurality of pixel data signal DATA0 are to time schedule controller 21 in image processor 22 outputs, and time schedule controller 21 is to produce a gate clock pulse CLK
GAnd one source pole time clock CLK
S, and export gate clock pulse CLK respectively
G, source electrode time clock CLK
SAnd these pixel data signals DATA0 is to shift register 111, shift register 131 and sampling/retainer 132.
Yet,, open every sweep trace 12 along with the lifting of liquid crystal indicator resolution and frame updating frequency
1-12
mThe required time is also just short more; Relatively; The usefulness of time schedule controller 21 also must and then promote; For example at present resolution is that the liquid crystal indicator of WXGA is to use single time schedule controller to drive liquid crystal panel (as shown in Figure 1), and to resolution be Full HDTV liquid crystal indicator be to use two same sizes time schedule controller with the driven in common liquid crystal panel.And in Fig. 2, specify.
Please with reference to shown in Figure 2, another kind of existing liquid crystal indicator is to comprise a liquid crystal panel 1 and one drive circuit plate 3, is that one scan line drive circuit 11, multi-strip scanning line 12 are set on liquid crystal panel 1
1-12
m, a data line drive circuit 13
1-13
n, many data lines 14
1-14
nAnd a pixel array region 15, wherein scan line drive circuit 11 comprises a plurality of shift registers 111, data line drive circuit 13
1-13
nComprise a plurality of shift register a
1--a
nAnd a plurality of samplings/retainer b
1--b
nDrive circuit board 3 comprises one first time schedule controller 31 and one second time schedule controller 32 and an image processor 33.Pel array 15 is divided into left half-court 151 and right half-court 152.
Wherein, liquid crystal panel 1 has specified in Fig. 1, does not give unnecessary details in this appearance.
In other words, the dealer must be that the liquid crystal indicator of WXGA specification and Full HDTV specification is developed two groups of drive circuit boards 2 (comprising time schedule controller 21) and drive circuit board 3 (comprising first time schedule controller 31 and second time schedule controller 32) to resolution.When drive circuit board collocation resolution was the liquid crystal indicator of WXGA specification, drive circuit board 2 was to see through time schedule controller 21 to drive liquid crystal panel 1.In addition; When drive circuit board collocation resolution is the liquid crystal indicator of Full HDTV specification; Drive circuit board 3 is to drive liquid crystal panel 1 through first time schedule controller 31 and second time schedule controller 32, therefore causes increasing the cost of exploitation time schedule controller.
In addition, explain that to drive circuit board 3 among Fig. 2 please with reference to shown in Figure 3, drive circuit board 3 also comprises a substrate 34 and four strip metal lead 351～～354 again.First time schedule controller 31 has four first input end A1～A4, and second time schedule controller 32 has four second input end A1～A4.Wherein, first time schedule controller 31, second time schedule controller 32, plain conductor 351～354 and image processor 33 are to be formed at same surperficial 341 of substrate 34.First input end A1～A4 sees through plain conductor 351～354 respectively and electrically connects with second input end A1～A4, and image processor 33 is to electrically connect with output pixel data signal (figure shows) and another part pixel data signal (figure shows) respectively to first time schedule controller 31 and second time schedule controller 32 with first time schedule controller 31 and second time schedule controller 32 respectively.
Yet; Because first time schedule controller 31 is identical with the specification of second time schedule controller 32; And be formed at the same surperficial 341 of substrate, therefore, first input end A1～A4 is positioned at (as shown in Figure 3) on the diagonal line with second input end A1～A4 respectively; Not only need use long plain conductor 351～354 to link first input end A1～A4 and second input end A1～A4 respectively, and increase the complexity of plain conductor layout.
Therefore; Drive circuit board, drive system and driving method that how a kind of flat display apparatus is provided are to be applicable to the liquid crystal indicator of different size; And can reduce length and the complexity of lead layout, one of the current important topic of genus in fact that links lead between first time schedule controller and second time schedule controller.
Summary of the invention
Because above-mentioned problem; The object of the invention is drive circuit board, drive system and the driving method that a kind of flat display apparatus is provided; The liquid crystal indicator of different size can be applicable to, and the length of binding lead between first time schedule controller and second time schedule controller and the complexity of lead layout can be reduced.
For achieving the above object, the drive circuit board of foundation a kind of flat display apparatus of the present invention comprises a substrate, one first time schedule controller, one second time schedule controller and at least one first plain conductor.Substrate has a first surface and a second surface relative with first surface; First time schedule controller is arranged at the first surface of substrate, and has at least one first input end; Second time schedule controller is arranged at the second surface of substrate, and has at least one second input end, and wherein the first input end of second input end and first time schedule controller is established in opposite directions; First plain conductor sees through substrate and electrically connects with the first input end and second input end respectively.
For achieving the above object, the drive system of foundation a kind of flat display apparatus of the present invention comprises one first time schedule controller and one second time schedule controller.First time schedule controller receives a plurality of pixel data signals, and exports a first of these pixel data signals; Second time schedule controller system receives these pixel data signals, and exports a second portion of these pixel data signals.
For achieving the above object; Driving method according to a kind of flat display apparatus of the present invention is to use with drive system collocation; Drive system comprises one first time schedule controller and one second time schedule controller; Driving method comprises following steps: receive a plurality of pixel data signals by first time schedule controller, and export a first of these pixel data signals; And receive these pixel data signals, and export a second portion of these pixel data signals by this second time schedule controller.
Hold the above; According to drive circuit board, drive system and the driving method of a kind of flat display apparatus of the present invention is to make first time schedule controller and second time schedule controller be arranged at the first surface and the second surface of substrate respectively, and first input end and second input end are established in opposite directions.Compare with prior art; Distance between the first input end of the present invention and second input end is shorter; Thereby make the existing plain conductor of first plain conductor short; And the short loss of signal that plain conductor caused is less, thus can promote the usefulness of first time schedule controller and second time schedule controller, and can reduce the complexity of lead layout.In addition; First time schedule controller of the present invention and second time schedule controller system receive complete pixel data signal respectively; When the liquid crystal indicator that for example is applied to Full HDTV specification; First to the flat display apparatus of the first time schedule controller output pixel data signal is with the first of driving flat display apparatus (first subregion of pel array) display pixel data-signal, and second portion to the flat display apparatus of the second time schedule controller output pixel data signal (second subregion of pel array) is to drive the second portion of flat display apparatus display pixel data-signal.In addition; When the liquid crystal indicator that for example is applied to the WXGA specification; Can set according to the firmware of internal memory; And only make the whole pixel data signal of first time schedule controller or second time schedule controller output, so the present invention can be applicable to the flat display apparatus of different size, and then save the cost of the different time schedule controllers of exploitation.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Fig. 1 is a kind of synoptic diagram of existing liquid crystal indicator;
Fig. 2 is the synoptic diagram of another kind of existing liquid crystal indicator;
Fig. 3 is the synoptic diagram of drive circuit board among Fig. 2;
Fig. 4 A is the synoptic diagram according to the drive circuit board of a kind of flat display apparatus of preferred embodiment of the present invention;
Fig. 4 B is the diagrammatic cross-section of drive circuit board among Fig. 4 A;
Fig. 4 C is another diagrammatic cross-section of drive circuit board among Fig. 4 A;
Fig. 5 is the synoptic diagram that drive circuit board and display panel link;
Fig. 6 is the synoptic diagram according to the drive system of a kind of flat display apparatus of preferred embodiment of the present invention;
Fig. 7 is another synoptic diagram according to the drive system of the flat display apparatus of preferred embodiment of the present invention; And
Fig. 8 is the process flow diagram according to the driving method of a kind of flat display apparatus of preferred embodiment of the present invention.
The component symbol explanation:
1 liquid crystal panel
11 scan line drive circuits
111 shift registers
12
1-12
mSweep trace
13
1-13
nData line drive circuit
131 shift registers
132 sampling/retainers
14
1-14
nData line
15 pixel array regions
150 pixels
151 left half-court
152 right half-court
2 drive circuit boards
21 time schedule controllers
22 image processors
3 drive circuit boards
31 first time schedule controllers
32 second time schedule controllers
33 image processors
34 substrates
341 surfaces
351～354 plain conductors
4 drive circuit boards
41 substrates
411 first surfaces
412 second surfaces
413 first conductive through holes
42 first time schedule controllers
43 second time schedule controllers
44,441～444 first plain conductors
45 image processors
451 image output terminals
46 second plain conductors
47 the 3rd plain conductors
48 connectors
5 display panels
61 first time schedule controllers
62 second time schedule controllers
63 image processors
64 driving circuits
641
1-641
nData line drive circuit
642 scan line drive circuits
The 642a shift register
65 selector switchs
7 display panels
71 pixel array regions
711 first subregions
712 first subregions
A1～A4 first input end
A1～A4 second input end
a
1-a
nShift register
c
1-c
nShift register
b
1-b
nSampling/retainer
d
1-d
nSampling/retainer
B1～B4 first input end
C1～C4 second input end
CLK
G, CLK
G2The gate clock pulse
CLK
S, CLK
S1, CLK
S2The source electrode time clock
CTL selects signal
D1 first output terminal
DATA
0Pixel data signal
The DATA0 pixel data signal
DATA
1The first of pixel data signal
DATA
1The left-half of pixel data signal
DATA
2The second portion of pixel data signal
The right half part of DATA2 pixel data signal
E1 second output terminal
The process step of the driving method of S1, S2 flat display apparatus
Embodiment
Below will drive circuit board, drive system and driving method according to a kind of flat display apparatus of preferred embodiment of the present invention be described with reference to relevant drawings, wherein components identical will be explained with identical reference marks.
Please with reference to shown in Fig. 4 A and Fig. 4 B, comprise a substrate 41, one first time schedule controller 42, one second time schedule controller 43 and at least one first plain conductor 44 according to the drive circuit board 4 of a kind of flat display apparatus of preferred embodiment of the present invention.In the present embodiment, flat display apparatus is to be a liquid crystal indicator.
First plain conductor 44 sees through substrate 41 and electrically connects with the first input end B1 and the second input end C1 respectively.
In the present embodiment; Substrate 41 also comprises at least one first conductive through hole 413; It was first conductive through hole 413 of substrate 41 and electrically connecting with the first input end B1 and the second input end C1 respectively that first conductive through hole 413 is communicated with first surfaces 411 and second surface 412, the first plain conductors 44.
In the present embodiment, shown in Fig. 4 C, the first input end B1 of first time schedule controller 42 is adjacent to the projected position of the second input end C1 of second time schedule controller 43.Therefore, can reduce the distance between the first input end B1 and the second input end C1, and make the length of first plain conductor 44 shorter, and then, the usefulness of first time schedule controller 42 and second time schedule controller 43 can be promoted.
In addition, clearer in order to make the present invention, next lift the drive circuit board 4 of an instance with the illustrated planar display device.
Please with reference to shown in Figure 5, in the present embodiment, the drive circuit board 4 of flat display apparatus has four first plain conductors 441～444.In addition, first time schedule controller 42 has four first input end B1～B4, and second time schedule controller 43 has four second input end C1～C4.Wherein, First input end B1～B4 sees through first plain conductor 441～444 and electrically connects with second input end C1～C4; At this moment; First plain conductor 441～444 slightly is parallel (as shown in Figure 5), and with the comparison that is crisscross arranged of existing plain conductor 351～354, the present invention can reduce the complexity of wiring.Certainly; Being positioned on the diagonal line (as shown in Figure 3) with second input end A1～A4 respectively with existing first input end A1～A4 again compares; Distance between first input end B1～B4 of the present invention and the second input end C1～C4 is less; Thereby make first plain conductor, 441～444 existing plain conductor 351～354 weak points, and the short loss of signal that plain conductor caused is less, therefore can promote the usefulness of first time schedule controller 42 and second time schedule controller 43.
In addition; The drive circuit board 4 of flat display apparatus also comprises an image processor 45; Wherein image processor 45 has at least one image output terminal 451; Wherein, image output terminal 451 is to electrically connect with the first input end B1～B4 of first time schedule controller 42 and second input end C1 of second time schedule controller 43～C4 respectively.
The drive circuit board 4 of flat display apparatus also comprises at least one second plain conductor 46 and at least one the 3rd plain conductor 47, and first time schedule controller 42 has at least one first output terminal D1, and second time schedule controller 43 has at least one second output terminal E1.Wherein, second plain conductor 46 electrically connects with the first output terminal D1 and a display panel 5 respectively.The 3rd plain conductor 47 electrically connects with the second output terminal E1 and display panel 5 respectively.In the present embodiment, second plain conductor 46 and the 3rd plain conductor 47 are connected to a connector 48 respectively, and connector 48 electrically connects with display panel 5.
Please with reference to shown in Figure 6, comprise one first time schedule controller 61, one second time schedule controller 62 and an image processor 63 according to the drive system of a kind of flat display apparatus of preferred embodiment of the present invention.Wherein, image processor 63 is exported a plurality of pixel data signal DATA respectively
0To first time schedule controller 61 and second time schedule controller 62.And first time schedule controller 61 is to receive these pixel data signals DATA
0, and export a DATA of first of these pixel data signals
1In addition, second time schedule controller 62 receives these pixel data signals DATA
0, and export a second portion DATA of these pixel data signals
2In the present embodiment, these pixel data signals DATA of being exported of image processor 63
0Be for a kind of low-voltage differential signal (Low Voltage Differential Signal, LVDS), and the DATA of first of these pixel data signals that first time schedule controller 61 and second time schedule controller 62 are exported
1And the second portion DATA of these pixel data signals
2Be for a kind of low-swing differential signal (Reduced Swing Differential Signal, RSDS).
In addition, the drive system of flat display apparatus also comprises at least one driving circuit 64, and it is that a pixel array region 71 with a display panel 7 electrically connects, and receives the DATA of first of these pixel data signals of being exported by first time schedule controller 61
1, and the second portion DATA of these pixel data signals of being exported by second time schedule controller 62
2, show the DATA of first of these pixel data signals with second subregion 712 of first subregion 711 of driving pixels array area 71 respectively and pixel array region
1And second portion DATA
2Driving circuit 64 can be arranged at display panel 7.In the present embodiment, first subregion 711 is that the left one side of something with pixel array region 71 is an example, and second subregion 712 is that the right one side of something with pixel array region 71 is an example, and certainly, the configuration of first subregion 711 and second subregion 712 also can have other combination.In addition, the big I of first subregion 711 and second subregion 712 is identical also can be different.
In the present embodiment, driving circuit 64 comprises a plurality of data line drive circuits 641
1-641
nAnd scan line drive circuit 642.Data line drive circuit 641
1-641
nComprise a plurality of shift register c
1-c
nAnd a plurality of samplings/retainer d
1-d
nAnd scan line drive circuit 642 comprises a plurality of shift register 642a.
Wherein, first time schedule controller 61 produces one source pole time clock CLK
S1, and output source electrode time clock CLK
S1And the DATA of first of these pixel data signals
1Respectively to shift register c
1-c
iAnd sampling/retainer d
1-d
iThe DATA of first that shows these pixel data signals with first subregion 711 of driving pixels array 71
1In addition, second time schedule controller 62 is to produce a gate clock pulse CLK
G2And one source pole time clock CLK
S2, and output gate clock pulse CLK
G2To shift register 642a, and output source electrode time clock CLK
S2And the second portion DATA of these pixel data signals
2, shift register c
I+1-c
nAnd sampling/retainer d
I+1-d
nThe second portion DATA that shows these pixel data signals with second subregion 712 of driving pixels array 71
2
At this moment, first time schedule controller 61 of the present invention and second time schedule controller 62 receive complete pixel data signal DATA respectively
0, and when the present invention for example is applied to the liquid crystal indicator for Full HDTV specification, the DATA of first of first time schedule controller, 61 output pixel data signals
1To the first DATA of display panel 7 with first subregion, the 711 display pixel data-signals of driving pixels array 71
1, and second time schedule controller 62 is the second portion DATA of output pixel data signal
2To the second portion DATA of display panel 7 with second subregion, the 712 display pixel data-signals of driving pixels array 71
2In addition; When the present invention for example is applied to the liquid crystal indicator for the WXGA specification; First time schedule controller 61 and second time schedule controller 62 can be set according to the firmware of internal memory, and make first time schedule controller 61 or the whole pixel data signal DATA of second time schedule controller, 62 outputs
0To display panel 7 with driving pixels array 71 display pixel data-signal DATA
0, changing speech, the dealer can see through firmware and set to control first time schedule controller 61 and second time schedule controller, 62 handled pixel data signal DATA according to actual situation
0Quantity, and the zone of controlling first time schedule controller 61 and second time schedule controller, 62 output datas to pel array 71.For example; Above-mentioned first time schedule controller 61 and second time schedule controller 62; It can be integrated circuit with same design; When the dealer was used to above-mentioned time schedule controller to use the display device of single time schedule controller, this time schedule controller this moment (time schedule controller 61 or time schedule controller 62) must be responsible for handling all pixel data signal DATA that transmitted by external circuit
0, the dealer just makes this time schedule controller handle all through the firmware setting and receives pixel data signal DATA
0And export.When the dealer was used to above-mentioned time schedule controller to use the display device of Dual Clocking controller, two time schedule controllers (time schedule controller 61 and time schedule controller 62) were responsible for handling the pixel data signal DATA that is transmitted by external circuit jointly again
0, the dealer just can make one of them time schedule controller handle all through the firmware setting and receive the DATA of first of pixel data signal
1And export, make another time schedule controller handle all and receive pixel data signal DATA
2Second portion and export.
Therefore, the present invention goes for the flat display apparatus of different size, and then saves the cost of the different time schedule controllers of exploitation.
Certainly; Except the firmware of above-mentioned internal memory is set; Also can control through selector switch; Please with reference to shown in Figure 7, the drive system of flat display apparatus also comprises a selector switch 65, and it produces selects signal CTL to control first time schedule controller 61 and second time schedule controller, 62 one of them these pixel data signals of output DATA
0Perhaps first time schedule controller 61 and second time schedule controller 62 are exported the DATA of first of these pixel data signals respectively
1And the second portion DATA of these pixel data signals
2, in other words, selector switch 65 is controlled first time schedule controller 61 and second time schedule controller, 62 handled pixel data signal DATA
0Quantity, and the zone of controlling first time schedule controller 61 and second time schedule controller, 62 output datas to pel array 71.
Again; What deserves to be mentioned is at this; The quantity of time schedule controller can increase according to the demand of reality; For example; The drive system of flat display apparatus can also comprise one the 3rd time schedule controller; Wherein, first time schedule controller, second time schedule controller or the 3rd time schedule controller can be exported the Zone Full of whole pixel data signals to driving pixels array with the driving pixels array according to actual state, and first time schedule controller, second time schedule controller and the 3rd time schedule controller first, second portion and the third part that can distinguish the output pixel data signal to first subregion, second subregion and the 3rd district of driving pixels array with first subregion, second subregion and the 3rd district of driving pixels array.
Please with reference to shown in Figure 8; According to the driving method of a kind of flat display apparatus of preferred embodiment of the present invention be and drive system collocation is used; Wherein drive system comprises one first time schedule controller and one second time schedule controller, and the driving method of flat display apparatus comprises step S1 to step S2.
Step S1 receives a plurality of pixel data signals by first time schedule controller, and exports a first of these pixel data signals; Step S2 receives these pixel data signals by second time schedule controller, and exports a second portion of these pixel data signals.
The driving method of the flat display apparatus of present embodiment can be applicable to the drive system of aforesaid flat display apparatus, and the drive system of aforesaid flat display apparatus details in the embodiment of Fig. 6 and Fig. 7, so repeat no more in this.
In sum; According to drive circuit board, drive system and the driving method of a kind of flat display apparatus of the present invention is to make first time schedule controller and second time schedule controller be arranged at the first surface and the second surface of substrate respectively, and first input end and second input end are established in opposite directions.Compare with prior art; Distance between the first input end of the present invention and second input end is less; Thereby make the existing plain conductor of first plain conductor short; And the short loss of signal that plain conductor caused is less, thus can promote the usefulness of first time schedule controller and second time schedule controller, and can reduce the complexity of lead layout.In addition; First time schedule controller of the present invention and second time schedule controller system receive complete pixel data signal respectively; When the liquid crystal indicator that for example is applied to Full HDTV specification; First to the flat display apparatus of the first time schedule controller output pixel data signal is with the first of driving flat display apparatus (first subregion of pel array) display pixel data-signal, and second portion to the flat display apparatus of the second time schedule controller output pixel data signal (second subregion of pel array) is to drive second subregion of flat display apparatus display pixel data-signal.In addition; When the liquid crystal indicator that for example is applied to the WXGA specification; Can set according to the firmware of internal memory; And only make the whole pixel data signal of first time schedule controller or second time schedule controller output, so the present invention can be applicable to the flat display apparatus of different size, and then save the cost of the different time schedule controllers of exploitation.
The above is merely illustrative, but not is restricted.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the appending claims its equivalent modifications of carrying out or change.
Claims (19)
1. LCD drive circuits plate comprises:
One substrate has a first surface and a second surface relative with this first surface;
One first time schedule controller is arranged at this first surface of this substrate, and has at least one first input end;
One second time schedule controller is arranged at this second surface of this substrate, and has at least one second input end, and this first input end of this second input end and this first time schedule controller is established in opposite directions; And
At least one first plain conductor electrically connects with this first input end and this second input end respectively through this substrate.
2. drive circuit board as claimed in claim 1; It is characterized in that; This substrate also comprises at least one first conductive through hole; This first conductive through hole is communicated with this first surface and this second surface, and this first plain conductor sees through this first conductive through hole of this substrate and electrically connects with this first input end and this second input end respectively.
3. drive circuit board as claimed in claim 1 is characterized in that, this first time schedule controller has at least one first output terminal, and this second time schedule controller has at least one second output terminal.
4. drive circuit board as claimed in claim 3 is characterized in that, also comprises at least one second plain conductor, and it electrically connects with this first output terminal and a display panel respectively.
5. drive circuit board as claimed in claim 3 is characterized in that, also comprises at least one the 3rd plain conductor, and it electrically connects with this second output terminal and a display panel respectively.
6. drive circuit board as claimed in claim 1 is characterized in that, this first input end of this first time schedule controller is adjacent to a projected position of this second input end of this second time schedule controller.
7. drive circuit board as claimed in claim 1; It is characterized in that; Also comprise an image processor; Wherein this image processor has at least one image output terminal, and this image output terminal electrically connects with this first input end of this first time schedule controller and this second input end of this second time schedule controller respectively.
8. the drive system of a liquid crystal indicator comprises:
One first time schedule controller receives a plurality of pixel data signals, and exports a first of those pixel data signals; And
One second time schedule controller receives those pixel data signals, and exports a second portion of those pixel data signals.
9. drive system as claimed in claim 8 is characterized in that, also comprises an image processor, and it exports those pixel data signals.
10. drive system as claimed in claim 8; It is characterized in that; Also comprise at least one first driving circuit and at least one second driving circuit; It electrically connects with a pixel array region of a display panel respectively; This first driving circuit receives this first of those pixel data signals of being exported by this first time schedule controller and this second portion that this second driving circuit receives those pixel data signals of being exported by this second time schedule controller, with one second subregion of one first subregion that drives this pixel array region respectively and this pixel array region to show those pixel data signals.
11. drive system as claimed in claim 10 is characterized in that, this first driving circuit and this second driving circuit are data line drive circuit.
12. drive system as claimed in claim 10 is characterized in that, this first driving circuit and this second driving circuit are to be arranged at this display panel.
13. drive system as claimed in claim 8 is characterized in that, also comprises:
One selector switch produces one and selects signal, and this first time schedule controller and this second time schedule controller are according to these those pixel data signals of selection signal output.
14. drive system as claimed in claim 8 is characterized in that, also comprises one the 3rd time schedule controller, receives those pixel data signals, and exports a third part of those pixel data signals.
15. the driving method of a liquid crystal indicator is to use with drive system collocation, this drive system comprises one first time schedule controller and one second time schedule controller, and this driving method comprises following steps:
Receive a plurality of pixel data signals by this first time schedule controller, and export a first of those pixel data signals; And
Receive those pixel data signals by this second time schedule controller, and export a second portion of those pixel data signals.
16. driving method as claimed in claim 15 is characterized in that, this drive system also comprises an image processor, and this driving method also comprises:
By this image processor output those pixel data signals to this first time schedule controller and this second time schedule controller.
17. driving method as claimed in claim 15 is characterized in that, this drive system also comprises at least one first driving circuit and at least one second driving circuit, and this driving method also comprises:
Receive this first of those pixel data signals of exporting by this first time schedule controller and receive this second portions of those pixel data signals that this second time schedule controller exports by this first driving circuit by this second driving circuit, with one second subregion of one first subregion that drives this pixel array region respectively and this pixel array region to show those data pixels signals.
18. driving method as claimed in claim 15 is characterized in that, this drive system also comprises a selector switch, and this driving method also comprises:
Produce one by this selector switch and select signal, this first time schedule controller and this second time schedule controller are according to these those pixel data signals of selection signal output.
19. driving method as claimed in claim 18 is characterized in that, this first time schedule controller and this second time schedule controller are first or the second portions that determines to export those pixel data signals according to this selection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100033300A CN101488309B (en) | 2008-01-17 | 2008-01-17 | Driving circuit board, driving system and driving method for flat display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100033300A CN101488309B (en) | 2008-01-17 | 2008-01-17 | Driving circuit board, driving system and driving method for flat display device |
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| Publication Number | Publication Date |
|---|---|
| CN101488309A CN101488309A (en) | 2009-07-22 |
| CN101488309B true CN101488309B (en) | 2012-11-28 |
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| CN2008100033300A Expired - Fee Related CN101488309B (en) | 2008-01-17 | 2008-01-17 | Driving circuit board, driving system and driving method for flat display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP6099311B2 (en) * | 2012-02-10 | 2017-03-22 | 株式会社ジャパンディスプレイ | Display device |
| CN102930845B (en) * | 2012-11-15 | 2015-06-03 | 深圳市华星光电技术有限公司 | Liquid crystal display timing driver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2287741Y (en) * | 1996-09-13 | 1998-08-12 | 中国航天工业供销总公司 | Streamer type picture and text displayer |
| US6756951B1 (en) * | 1999-08-03 | 2004-06-29 | Pioneer Corporation | Display apparatus and driving circuit of display panel |
| CN1841483A (en) * | 2005-03-30 | 2006-10-04 | 奇景光电股份有限公司 | Control signal transmission method for liquid crystal display |
-
2008
- 2008-01-17 CN CN2008100033300A patent/CN101488309B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2287741Y (en) * | 1996-09-13 | 1998-08-12 | 中国航天工业供销总公司 | Streamer type picture and text displayer |
| US6756951B1 (en) * | 1999-08-03 | 2004-06-29 | Pioneer Corporation | Display apparatus and driving circuit of display panel |
| CN1841483A (en) * | 2005-03-30 | 2006-10-04 | 奇景光电股份有限公司 | Control signal transmission method for liquid crystal display |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101488309A (en) | 2009-07-22 |
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Address after: 000000 science Road, 350 Hsinchu Science Industrial Park, Miaoli, Taiwan Province, China, No. 160 Applicant after: Chimei Optoelectronics Co., Ltd. Address before: 000000 No. 1, Qi Gong Road, Tainan Science Industrial Park, 74144 Tainan County, Taiwan Province, China Applicant before: Chimei Optoelectronics Co., Ltd. |
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