CN101483429A - Multi-mode programmable frequency divider with 0.5 frequency division step - Google Patents
Multi-mode programmable frequency divider with 0.5 frequency division step Download PDFInfo
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- CN101483429A CN101483429A CNA2009100284619A CN200910028461A CN101483429A CN 101483429 A CN101483429 A CN 101483429A CN A2009100284619 A CNA2009100284619 A CN A2009100284619A CN 200910028461 A CN200910028461 A CN 200910028461A CN 101483429 A CN101483429 A CN 101483429A
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Abstract
The present invention discloses a multi- module programmable frequency demultiplier as 0.5 frequency demultiplication step length which comprises 2/3 frequency demultiplier unit, multiplex selector and a controller that cascade mutually; a half-adder of n-1 bit used to adjust frequency dividing ratio timely is also included; enable signal C<SUB>0</SUB> of phase switch control module and 2/3 unit number setting signal constitute binary system frequency dividing ratio control bit together; output signal can be lead out from any 2/3 unit mode control signal output terminal. The fractional step length frequency demultiplier circuit structure of the invention is simple with no bur, increased power consumption is few and flexibility is strong.
Description
Technical field
The present invention relates to a kind of multi-mode programmable frequency divider of 0.5 frequency division step-length, particularly the technical field of the multi-mode programmable frequency divider of high-speed wide-region fraction division design.
Background technology
In recent years, along with the extensive use of delta sigma decimal fraction frequency synthesizer in radio-frequency technique, the frequency divider with fraction division step-length has obtained deep research.A large amount of frequency division step-lengths that studies show that frequency divider whenever reduce half, can reduce the quantizing noise 6dB of modulator, and the bandwidth of frequency synthesizer just can obtain expanding like this, thereby have accelerated the lock speed of system.In April, 2002, be published in (JSSC) " A1.5-V900-MHzmonolithic CMOS fast-switching frequency synthesizer for wireless applications " literary composition of the 459th page to the 470th page of IEEE " solid-state circuit magazine ", related to a kind of design of multi-mode programmable frequency divider of 0.5 frequency division step-length.This circuit structure has utilized phase place handoff technique low in power consumption, is that order is switched owing to what adopt still, has brought burr inevitably, spends the elimination that a large amount of energy is used for burr like this with regard to having to.Successively there are many pieces of articles to disclose the method for various elimination burr, but generally speaking are nothing but to have increased a lot of control circuits extraly, this is not only complicated circuit structure, what have has also consumed bigger power consumption.
In November, 2006, IEEE " solid-state circuit magazine " (JSSC) " A quantizationnoise suppression technique for delta sigma fractional-N frequency synthesizers " literary composition of the 2500th page to the 2511st page discloses a kind of 0.5 step-length multi-mode programmable frequency divider based on 1/1.5 frequency unit.This structure has modular characteristics, has made things convenient for layout design, but 1/1.5 frequency unit that is increased need consume 1.5 times of power consumptions to high speed 2/3 frequency unit.Thereby the increase of this unit, it is about 75% to make that the power consumption of frequency divider has increased before comparing, and this is not suitable for the trend of low power dissipation design nowadays.
Summary of the invention
The technical problem to be solved in the present invention is the multi-mode programmable frequency divider that proposes a kind of 0.5 frequency division step-length at the defective that prior art exists.
The multi-mode programmable frequency divider of a kind of 0.5 frequency division step-length of the present invention, it is characterized in that comprising that n-1 level 2/3 frequency unit is the first order 2/3 frequency unit to the n-1 level 2/3 frequency unit, MUX, control module and half adder, wherein connect the pulse input end of the second level 2/3 frequency unit after the output of the first order 2/3 frequency unit serial connection MUX, the mode control signal output of the mode control signal input termination second level 2/3 frequency unit of the first order 2/3 frequency unit, the pulse input end of the output termination third level 2/3 frequency unit of the second level 2/3 frequency unit, the mode control signal output of the mode control signal input termination third level 2/3 frequency unit of the second level 2/3 frequency unit, by that analogy to n-1 level 2/3 frequency unit, the input signal termination high level of n-1 level 2/3 frequency unit, be connected in series control module between the output of n-1 level 2/3 frequency unit and the input of MUX, the output of half adder connects the number of putting of the first order 2/3 frequency unit to the n-1 level 2/3 frequency unit respectively and holds, and wherein n is a natural number.
The present invention has adopted the phase place handoff technique with low-power consumption characteristic, generation for fear of burr, the working method of using backward to switch, but the influence that this kind working method is brought is reducing of frequency dividing ratio rather than increases, because when backward is switched, part input pulse has been left in the basket, and makes the output pulse period shorten.Solve the method for this influence, insert the number of putting of each frequency unit after exactly frequency dividing ratio being adjusted accordingly through a half adder earlier again and hold.The frequency divider of 0.5 frequency division step-length of the present invention, power consumption is less, does not have burr, and circuit structure is succinct, and has two kinds of mode of operations: the mark step-length; Integer step.
Description of drawings
Fig. 1 is the sequential chart that order and backward phase place are switched;
Fig. 2 is a frequency divider general structure of the present invention;
Fig. 3 is the circuit structure of 2/3 frequency unit;
Fig. 4 is the control logic that backward of the present invention is switched;
Fig. 5 is the output timing diagram of phase place switch control logic module correspondence;
Input and output waveform when Fig. 6 is a frequency divider mark step-length of the present invention;
Output waveform when Fig. 7 is a frequency divider integer step of the present invention.
Embodiment
At present the high-speed wide-region programmable frequency divider of integer step adopts is that the mode of traditional 2/3 frequency unit cascade realizes, pattern control output signal Mo only needs feedforward step by step, thereby have stronger speed advantage, and has binary system frequency dividing ratio control bit very easily.In order to utilize these characteristics of this structure, can realize the function of decimal 0.5 frequency division step-length again, we insert MUX between first and second grade of 2/3 unit, realize the requirement of fraction division step-length by the signal link that switches out of phase.The frequency divider of existing 0.5 frequency division step-length is realized the main technology of switching based on the structure and the order phase place of 1/1.5 frequency unit that adopts.The former power consumption is very big, and the latter needs complicated circuit to eliminate burr.
As shown in Figure 1.In the order phase place is switched,, then produced burr inevitably if the opportunity of switching is improper; And backward phase place handoff technique can jaggedly not produce in essence, therefore becomes the choice of technology of the present invention.
As shown in Figure 2.A kind of multi-mode programmable frequency divider of 0.5 frequency division step-length, it is characterized in that comprising that n-1 level 2/3 frequency unit is the first order 2/3 frequency unit to the n-1 level 2/3 frequency unit, MUX 21, control module 22 and half adder 23, wherein connect the pulse input end of the second level 2/3 frequency unit after the output of the first order 2/3 frequency unit serial connection MUX 21, the mode control signal input Mi of the first order 2/3 frequency unit meets the mode control signal output Mo of the second level 2/3 frequency unit, the pulse input end of the output termination third level 2/3 frequency unit of the second level 2/3 frequency unit, the mode control signal input Mi of the second level 2/3 frequency unit meets the mode control signal output Mo of the third level 2/3 frequency unit, by that analogy to n-1 level 2/3 frequency unit, the input signal termination high level of n-1 level 2/3 frequency unit, be connected in series control module 22 between the output of n-1 level 2/3 frequency unit and the input of MUX 21, the output of half adder 23 connects the number of putting of the first order 2/3 frequency unit to the n-1 level 2/3 frequency unit respectively and holds, and wherein n is a natural number.f
FracBe the output signal of frequency divider, f
InInput signal for the source pulse.The n-1 position summing signal output Sum of half adder among the figure
1To Sum
N-1The number of putting that connects 2/3 corresponding frequency unit is respectively held.
In order to realize the function of 0.5 frequency division step-length, between first and second grade of 2/3 unit, be connected in series the MUX of 4-1.Four road signals are produced by the first order 2/3 frequency unit, are respectively I, Q, I is non-, Q is non-, and phase place postpones 90 degree successively, and they are directly as the input of 4-1MUX.Owing to these signals are to remove 2 frequency units through one to generate, so if order is switched, the phase place of a current demand signal of every switching just is delayed 90 degree, just output signal has gulped down input pulse half more, realize that frequency dividing ratio adds 0.5, and when the phase place switching is not worked, by the number end of putting of the first order 2/3 frequency unit is put height, can realize that frequency dividing ratio adds 1, so just make things convenient for and realized that with 0.5 be the function of the continuous frequency dividing ratio variation of step-length.Otherwise, to switch for backward, phase place of then every switching is shifted to an earlier date 90 degree, and output signal has just been lacked the input pulse cycle half, and frequency dividing ratio has been reduced 0.5, so just is difficult to realize the requirement of frequency dividing ratio continually varying.For one or four mould frequency dividers, attainable frequency dividing ratio is when supposing to switch in proper order: n/n+0.5/n+1/n+1.5, if utilization backward handoff technique, the frequency dividing ratio that its reality realized is: n/n-0.5/n+1/n+0.5.Therefore, we say that the backward handoff technique makes the variation of frequency dividing ratio produce reforming phenomena, and this problem needs to be resolved hurrily.
We are not difficult to find that this phenomenon is regular governed by above-mentioned example, when phase place is switched backward work, the relative target frequency dividing ratio of frequency dividing ratio reduces 1, thereby we can be when the switching of backward phase place enables, add 1 for the target frequency dividing ratio, after handover operation is finished, just realize our needed frequency dividing ratio size like this.Based on such thought, put the half adder that the number end increases by a n-1 position in the frequency dividing ratio of frequency divider, realize adjusting the function of frequency dividing ratio in good time.The addend of half adder is the enable signal C of phase place switching controls module
0, because here we design C
0When high, phase place is switched and is enabled C
0When low, phase place is switched and is not worked.Therefore, during the backward switch operating, just add upward 1 to frequency dividing ratio, backward is switched when not working, and added value is 0, does not influence the size of frequency dividing ratio.If designed enable signal state exchange is opposite with this example, then increases by a not gate and get final product.
Fig. 3 is 2/3 a frequency unit structural representation of the present invention.It is a common structure, and it comprises: import and door, level Four D-latch, a triggering signal input F for three two
In, a mode control signal input Mi, puts number end P, triggering signal output Fo, an and mode control signal output Mo.Be all when high when putting several signal P and pattern control input signals Mi, this frequency unit is operated in 3 frequency division patterns; All be operated in 2 frequency division patterns under other situations.In frequency divider as shown in Figure 2, a complete frequency division is in the cycle, and high level only appears one time in mode control signal, and pulse duration is equivalent to the one-period of input signal, so in the cycle, each 2/3 frequency unit only carries out once removing 3 divide operation at the most at a complete frequency division.Consider the variation of the frequency dividing ratio that the phase place switching is brought when enabling, the output pulse period that can get whole frequency divider is: (2
N-1+ 2
N-2C
N-1+ ... + 2
0C
1+ 2
-1C
0) T
In, T
InBe input signal cycle, so attainable frequency dividing ratio is: 2
N-1+ 2
N-2C
N-1+ ... + 2
0C
1+ 2
-1C
0, be not difficult to find out that by expression formula the frequency division step-length that is realized is 0.5.
The control module 22 that Fig. 4 switches for the phase place among the present invention, comprise first remove 2 frequency units 41, second remove 2 frequency units 42 and five and door promptly first with Men Zhidi five and door, wherein first remove the output termination first of 2 frequency units 41 and an input of door, first with the outside Enable Pin C of another input termination of door
0First removes the input of 2 frequency units 42 with the output termination second of door, second first output that removes 2 frequency units 42 connect respectively second with input of door and the 5th with an input of door, second second output that removes 2 frequency units 42 connect respectively second with another input of door and the 3rd with an input of door, second the 3rd output that removes 2 frequency units 42 connect respectively the 3rd with another input of door and the 4th with an input of door, second the 4th output that removes 2 frequency units 42 connect respectively the 4th with another input of door and the 5th with another input of door.f
IntBe first the output signal except that 2 frequency units 41, the output signal when it can be used as integer step.
Its operation principle is when the phase place switching enables, C
0=1, with output signal four frequency divisions, produce the identical duty ratio of frequency then and be 25% four tunnel control signals, be used to control 4-1MUX work.Be understood that the duty ratio that is obtained is 25% signal, its high level just equals an output pulse period effective time, so just can be implemented in interior phase place of each output pulse period and automaticallyes switch once.It is that the order of their connection control signal is opposite that backward is switched the difference of switching with order, and what the present invention adopted is the backward handoff technique, thus the order of phase place switching be non-from Q, I is non-, Q is to I.When enable signal when low, C
0=0, phase place is switched and not to be worked, this mainly be because the output that the first order is removed 2 frequency units and enable signal with after send into the second level and remove 2 frequency units, and this signal constant is low at this moment, so MUX is only understood a certain road signal in gating four road signals, and remains unchanged.First the output signal f in control module 22 except that 2 frequency units 41
IntDuring as the output of whole frequency divider, can realize the division function of integer step, and the output signal duty ratio is 50%.
As shown in Figure 5.Four road signal dutyfactors of control module output are 25%, control 4-1 selector four road input signals respectively, determine that wherein one road signal is as the output of selector.During whole frequency divider operation, because the circulation of four tunnel control signals is for high, so can realize the backward handoff functionality of phase place automatically.
Input and output waveform when Fig. 6 is a frequency divider operation of the present invention.The figure illustrates the working condition of frequency divider of the present invention under four kinds of continuous different frequency dividing ratios.As shown in the figure, when putting frequency dividing ratio increased, its variation was followed in the output pulse automatically, the every increase by 0.5 of frequency dividing ratio, and it just gulps down input pulse half more, has well realized the function of 0.5 frequency division step-length.
Fig. 7 is the work wave of frequency divider of the present invention when the integral frequency divisioil step-length.This signal is the output that removes 2 frequency units through, so its duty ratio is 50%, and the frequency dividing ratio size that is realized this moment two times during for the mark step-length.Therefore structure of the present invention is when the frequency divider as the fraction division step-length uses, and its attainable frequency dividing ratio scope is half when doing the use of integral frequency divisioil step-length.Above-mentioned two figure are emulation gained under the situation of 3GHz at frequency input signal all, thereby as can be known, frequency divider of the present invention can well be applied to the design of high frequency telecommunication circuits such as radio-frequency transmitter, can realize the designing requirement of expecting.
In sum, the present invention has following technical characterictic: (1) no burr: the employing of backward phase place handoff technique has determined this characteristics; (2) circuit structure is succinct: the half adder that has only additionally increased by a n-1 position is regulated the influence that frequency dividing ratio is brought because of the backward switching; (3) able to programme: as only to need that the target frequency dividing ratio is turned to binary number and insert the input of corresponding half adder and get final product.
The above only is a preferred embodiment of the present invention, and all equalizations that claim is done according to the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (2)
1. the multi-mode programmable frequency divider of a frequency division step-length, it is characterized in that comprising that n-1 level 2/3 frequency unit is the first order 2/3 frequency unit to the n-1 level 2/3 frequency unit, MUX (21), control module (22) and half adder (23), wherein connect the pulse input end of the second level 2/3 frequency unit after the output of the first order 2/3 frequency unit serial connection MUX (21), the mode control signal input (Mi) of the first order 2/3 frequency unit connects the mode control signal output (Mo) of the second level 2/3 frequency unit, the pulse input end of the output termination third level 2/3 frequency unit of the second level 2/3 frequency unit, the mode control signal input (Mi) of the second level 2/3 frequency unit connects the mode control signal output (Mo) of the third level 2/3 frequency unit, by that analogy to n-1 level 2/3 frequency unit, the mode control signal input termination high level of n-1 level 2/3 frequency unit, be connected in series control module (22) between the output of n-1 level 2/3 frequency unit and the input of MUX (21), the output of half adder (23) connects the number of putting of the first order 2/3 frequency unit to the n-1 level 2/3 frequency unit respectively and holds, and wherein n is a natural number.
2. the multi-mode programmable frequency divider of a kind of 0.5 frequency division step-length according to claim 1, it is characterized in that described control module (22) comprise first remove 2 frequency units (41), second remove 2 frequency units (42) and five and door promptly first with Men Zhidi five with, wherein first remove the output termination first of 2 frequency units (41) and an input of door, first with the outside Enable Pin (C of another input termination of door
0), first removes the input of 2 frequency units (42) with the output termination second of door, second first output that removes 2 frequency units (42) connect respectively second with input of door and the 5th with an input of door, second second output that removes 2 frequency units (42) connect respectively second with another input of door and the 3rd with an input of door, second the 3rd output that removes 2 frequency units (42) connect respectively the 3rd with another input of door and the 4th with an input of door, second the 4th output that removes 2 frequency units (42) connect respectively the 4th with another input of door and the 5th with another input of door.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103098377A (en) * | 2010-07-29 | 2013-05-08 | 马维尔国际贸易有限公司 | Modular frequency divider and mixer configuration |
| US9325541B2 (en) | 2010-07-29 | 2016-04-26 | Marvell World Trade Ltd. | Modular frequency divider with switch configuration to reduce parasitic capacitance |
| CN108777575A (en) * | 2018-04-23 | 2018-11-09 | 深圳华大北斗科技有限公司 | frequency divider |
| CN116545438A (en) * | 2023-07-03 | 2023-08-04 | 麦斯塔微电子(深圳)有限公司 | Frequency divider and multi-modulus frequency divider |
-
2009
- 2009-01-20 CN CNA2009100284619A patent/CN101483429A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103098377A (en) * | 2010-07-29 | 2013-05-08 | 马维尔国际贸易有限公司 | Modular frequency divider and mixer configuration |
| US8965310B2 (en) | 2010-07-29 | 2015-02-24 | Marvell World Trade Ltd. | Modular frequency divider and mixer configuration |
| CN103098377B (en) * | 2010-07-29 | 2015-08-26 | 马维尔国际贸易有限公司 | Module frequency divider and mixer configuration |
| US9325541B2 (en) | 2010-07-29 | 2016-04-26 | Marvell World Trade Ltd. | Modular frequency divider with switch configuration to reduce parasitic capacitance |
| CN108777575A (en) * | 2018-04-23 | 2018-11-09 | 深圳华大北斗科技有限公司 | frequency divider |
| CN108777575B (en) * | 2018-04-23 | 2022-05-03 | 深圳华大北斗科技股份有限公司 | Frequency divider |
| CN116545438A (en) * | 2023-07-03 | 2023-08-04 | 麦斯塔微电子(深圳)有限公司 | Frequency divider and multi-modulus frequency divider |
| CN116545438B (en) * | 2023-07-03 | 2023-11-03 | 麦斯塔微电子(深圳)有限公司 | Frequency divider and multi-modulus frequency divider |
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