CN101471671A - Method and device for calculating checkout bit of LDPC encode - Google Patents

Abstract

The invention discloses a method for calculating check bits in low density parity check codes (LDPC), which comprises the following steps: calculating the value of any check bit group in the check bit groups; and calculating the value of the check bits in other check bit groups according to the value of the any check bit group. The calculation method can calculate the value of any one check bit other than the initial check bit in other check bit groups, thereby reducing the time delay of code calculation and increasing the efficiency.

Description

The computational methods and the device of check bit in the LDPC coding

Technical field

The present invention relates to the encoding and decoding technique field, the computational methods and the device of check bit in particularly a kind of LDPC sign indicating number coding.

Background technology

Low density parity check code (Low Density Parity Check Codes) is a kind of linear block codes that proposed in 1962.The LDPC sign indicating number has good Hamming distance characteristic.Utilize iterative decoding algorithm, the LDPC sign indicating number can lower complexity approach the shannon capacity limit.But because the restriction of computing capability at that time, the LDPC sign indicating number is considered to not be practical codes, is not subject to people's attention in a very long time.Up to 1993, after having found the Turbo code of the nearly shannon limit of performance, utilize the Tanner figure of random configuration to study the performance of LDPC sign indicating number, find to adopt and have the decoding performance similar with Turbo code with the canonical LDPC sign indicating number of long-pending decoding algorithm, when long code even surpassed Turbo code, this result has caused the upsurge of coding circle research LDPC sign indicating number.

The LDPC sign indicating number is a kind of linear block codes, and its name derives from the sparse property of its check matrix, and promptly the number of every row (every row) nonzero element is very rare in the check matrix, and the position is issue at random, and most elements all is " 0 ".For code length is that n, information bit number are the LDPC sign indicating number of k, can be described by its check matrix H (n-k) * n, and all code words satisfy xH ^T=0, wherein x represents arbitrary code word.Verification constraint of each line display of check matrix, wherein the code element variable xj of all nonzero element correspondences constitutes a checksum set, represents promptly above-mentioned formula xH with a check equations ^T=0; The verification constraint that a code element variable participates in is shown in each tabulation of check matrix, when column element is non-vanishing, represents that this code element variable has participated in the verification constraint of this row.

In the 802.16e of prior art related protocol, in order to reduce the encoder complexity of LDPC sign indicating number, the LDPC sign indicating number is constructed as follows:

The LDPC sign indicating number is based on one or more basic LDPC sign indicating number collection.Each basic code is a system linear block code.It is long with different bags that basic code can generate different code checks.

Each LDPC sign indicating number that the LDPC sign indicating number is concentrated is defined as the matrix H of m*n, and wherein n is a code length, and m is the number of parity check bit in the sign indicating number, the number k=n-m of system bits.Matrix H is defined as follows:

P wherein _{I, j}Be the permutation matrix of a z*z or complete 0 matrix of a z*z.Matrix H is by a m _b* n _b(subscript b represents corresponding with basic battle array, the basic matrix H of binary system base) _bExpansion comes, n=z*n _b, m=z*m _b, z is an integer.The concrete grammar of expansion is, fundamental matrix H _bIn each 1 permutation matrix that changes a z*z into, each 0 complete 0 matrix that changes a z*z into.The n of fundamental matrix _b=24.

The substitute mode that permutation matrix uses is a ring shift right, and the permutation matrix collection comprises the unit matrix of z*z and the ring shift right matrix that is produced by unit matrix.Because each permutation matrix represented by a ring shift right, so the information of the basic matrix of binary system with and the information of displacement just can make up compact prototype matrix H bm of generation.Prototype matrix H bm is identical with the basic matrix H b ranks of binary system number average.By 0 usefulness blank among the Hb or negative (as: 1) being replaced representing complete 0 matrix of a z*z, (i j) 〉=0 replaces the 1 usefulness cyclic shift size p among the Hb, and the prototype matrix can directly expand to H.

H _bSeparated into two parts, wherein H _B1Be systematic bits, H _B2Be Parity Check Bits, so,

Each LDPC sign indicating number that the LDPC sign indicating number is concentrated is defined as the matrix H of m*n, and wherein n is a code length, and m is the number of parity check bit in the sign indicating number, the number k=n-m of system bits.

H _B2Can further include h _bAnd H ' _B2Two parts, wherein vector h _bBe weighting, H ' _B2Be dual diagonal matrix.H ' _B2In the matrix, i represents line number, and j represents columns, and when i=j and i=j+1, matrix element is 1; Be 0 under other situation.

H in the fundamental matrix _b(0)=1, h _b(m _b-1)=1, the three are worth h _b(j)=1,0＜j＜(m _b-1)

Non-0 submatrix comes ring shift right by a specific ring shift right value.H ' _B2In each 1 be assigned with shift size 0.H _bWhen expanding to H, H ' _B2In each 1 replace by unit matrix of a z*z.The position of hb vector top and bottom is assigned with identical shift size, and the 3rd 1 in the middle of the hb vector is azygous shift size.For the maximum code length (n=2304) of variant code check has defined basic prototype matrix.Displacement collection in the basic prototype matrix { p (i, j) } is used for determining the shift size of other different code lengths of same code rate.Each prototype matrix has the nb=24 row, and for code length n, spreading factor zf=n/24, f are the code length sequence numbers to constant bit rate, f=0, and 1,2 ..., 18.For code length n=2304, spreading factor is z0=96.

If code check is 1/2, the 3/4A sign indicating number, the 3/4B sign indicating number, 2/3B sign indicating number and 5/6 then changes by following formula { p (i, j) }:

If code check is 2/3A, then { p (i, j) } changed by following formula.

$p(f,i,j)=\left\{\begin{array}{c}p(i,j),p(i,j)\≤0\\ \mathrm{mod}(p(i,j),z_f),p(i,j)>0\end{array}\right.$

For example during 1/2 code check, as follows

-1?94?73?-1?-1?-1?-1?-1?55?83?-1?-1?7 0 -1?-1?-1?-1?-1?-1?-1?-1?-1?-1

-1?27?-1?-1?-1?22?79?9 -1?-1?-1?12?-1?0 0 -1?-1?-1?-1?-1?-1?-1?-1?-1

-1?-1?-1?24?22?81?-1?33?-1?-1?-1?0 -1?-1?0 0 -1?-1?-1?-1?-1?-1?-1?-1

61?-1?47?-1?-1?-1?-1?-1?65?25?-1?-1?-1?-1?-1?0 0 -1?-1?-1?-1?-1?-1?-1

-1?-1?39?-1?-1?-1?84?-1?-1?41?72?-1?-1?-1?-1?-1?0 0 -1?-1?-1?-1?-1?-1

-1?-1?-1?-1?46?40?-1?82?-1?-1?-1?79?0 -1?-1?-1?-1?0 0 -1?-1?-1?-1?-1

-1?-1?95?53?-1?-1?-1?-1?-1?14?18?-1?-1?-1?-1?-1?-1?-1?0 0 -1?-1?-1?-1

-1?11?73?-1?-1?-1?2 -1?-1?47?-1?-1?-1?-1?-1?-1?-1?-1?-1?0 0 -1?-1?-1

12?-1?-1?-1?83?24?-1?43?-1?-1?-1?51?-1?-1?-1?-1?-1?-1?-1?-1?0 0 -1?-1

-1?-1?-1?-1?-1?94?-1?59?-1?-1?70?72?-1?-1?-1?-1?-1?-1?-1?-1?-1?0 0 -1

-1?-1?7 65?-1?-1?-1?-1?-1?39?49?-1?-1?-1?-1?-1?-1?-1?-1?-1?-1?-1?0 0

43?-1?-1?-1?-1?65?-1?41?-1?-1?-1?26?7 -1?-1?-1?-1?-1?-1?-1?-1?-1?-1?0

According to the structure of above-mentioned check matrix H, coding method is as follows:

Given information bit sequence s=[s (0), s (2) ..., s (K-1)], the LDPC coding is exactly to determine M check bit p=[p (0), p (1) ..., p (M-1)], the LDPC code word that obtains is c=[sp].Information bit sequence s is divided into groups:

s＝[u(0)，u(1)，…，u(k _b-1)]，u(i)＝[s _iz，s _iz+1，…，s _(i+1)z-1]

Similarly, check bit p is divided into groups:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _iz，p _iz+1，…，p _(i+1)z-1]

In the prior art, the computational process of check bit comprised for two steps, (1) initialization v (0) in the LDPC sign indicating number coding; (2) recurrence is calculated v (i+1), 0≤i≤m according to v (i) _b-2

Specific as follows:

(1), can get according to Hbm

$P_{p(x,k_b)}v\left(0\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\underset{i=0}{\overset{m_b-1}{\mathrm{\Σ}}}{p}_{i,j}u\left(j\right)$

1≤x≤m wherein _b-2, Pi represents that the unit matrix of z * z obtains through right cyclic shift i.Following formula multiply by

Then can obtain v (0), wherein $P_{p(x,k_b)}^{-1}=P_{z-p(x,k_b)}$

(2) carry out recurrence

$v\left(1\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}{P}_{p(i,j)}u\left(j\right)+P_{p(i,k_b)}v\left(0\right),i=0$

$v(i+1)=v\left(i\right)+\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}{P}_{p(i,j)}u\left(j\right)+P_{p(i,k_b)}v\left(0\right),i=1,...,m_b-2$

In research and practice process to prior art, the inventor finds to exist in the prior art following problem:

The calculating of check bit is a kind of serial computing method in the existing LDPC sign indicating number coding, promptly the calculating of check bit is the block-by-block serial computing in computational process, only after calculating v (i), just can calculate v (i+1), and the serial computing method can cause bigger time delay.

Summary of the invention

The purpose of the embodiment of the invention provides the computational methods and the device of check bit in a kind of LDPC sign indicating number coding, to overcome in the prior art because what adopt is the bigger problem of time delay that the serial computing method causes.

For solving the problems of the technologies described above, the embodiment of the invention provides the calculating of check bit in a kind of LDPC sign indicating number coding to be achieved in that

The computational methods of check bit in a kind of low density parity check code coding comprise:

The value of the arbitrary check bit grouping in the computation of parity bits grouping;

The value of check bit during other check bit of value parallel computation that utilizes described arbitrary check bit to divide into groups divides into groups.

The computational methods of check bit in a kind of low density parity check code coding comprise:

Calculate the value of arbitrary check bit;

Utilize the value of other check bit of value parallel computation of described arbitrary check bit.

The calculation element of check bit comprises initial check bit computing unit in a kind of low density parity check code coding, check bit parallel computation unit wherein,

Initial check bit computing unit is used for the value of arbitrary check bit grouping of computation of parity bits grouping;

Check bit parallel computation unit is used for utilizing the value of other check bit grouping check bit of value parallel computation of described arbitrary check bit grouping.

The calculation element of check bit comprises initial check bit computing unit in a kind of low density parity check code coding, check bit parallel computation unit wherein,

Initial check bit computing unit is used to calculate the value of arbitrary check bit;

Check bit parallel computation unit is used to utilize the value of other check bit of value parallel computation of described arbitrary check bit.

The technical scheme that is provided by the above embodiment of the invention as seen, by above embodiment as seen, after calculating the value of the arbitrary check bit grouping in the check bit grouping, the value of check bit during other check bit of value parallel computation that utilizes described arbitrary check bit to divide into groups divides into groups, like this, the value that calculates check bit in the grouping of other check bit that can walk abreast, thus the time delay of calculating can be reduced, raise the efficiency.

Description of drawings

Fig. 1 is the flow chart of the computational methods embodiment of check bit in the low density parity check code coding of the present invention;

Fig. 2 is the block diagram of the calculation element embodiment of check bit in the low density parity check code coding of the present invention.

Embodiment

The embodiment of the invention provides the computational methods and the device of check bit in a kind of low density parity check code coding.

In order to make those skilled in the art person understand the present invention program better, the embodiment of the invention is described in further detail below in conjunction with drawings and embodiments.

The front is mentioned, for given information bit sequence s=[s (0), and s (1) ..., s (K-1)], the LDPC coding is to determine M check bit p=[p (0), p (1) ..., p (M-1)], the LDPC code word that obtains is c=[sp].Information bit sequence s is divided into groups:

s＝[u(0)，u(1)，…，u(k _b-1)]，u(i)＝[s _iz，s _iz+1，…，s _(i+1)z-1]

Subscript z in u (i) grouping is more than or equal to 1, and is special, and the situation that subscript z equals 1 is equivalent to not grouping.

Similarly, check bit p is divided into groups:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _iz，p _iz+1，…，p _(i+1)z-1]

Employed H matrix is as follows:

Hb separated into two parts, wherein H _B1Be systematic bits, H _B2Be Parity Check Bits, so

H _B2Can also be further divided into two parts, wherein vector h _bBe weighting, H ' _B2Be dual diagonal matrix.H ' _B2In the matrix, i represents line number, and j represents columns, and when i=j and i=j+1, matrix element is 1; Be 0 under other situation.

H in the fundamental matrix _b(0)=1, h _b(m _b-1)=1, the three are worth h _b(j)=1,0＜j＜(m _b-1), as follows:

Based on this, the inventive method first embodiment can comprise flow process as shown in Figure 1:

Step 101: the value of the arbitrary check bit grouping in the computation of parity bits grouping.

As previously mentioned, according to Hbm, can get

$P_{p(x,k_b)}v\left(0\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\underset{i=0}{\overset{m_b-1}{\mathrm{\Σ}}}{p}_{i,j}u\left(j\right)$

1≤x≤m wherein _b-2, Pi represents that the unit matrix of z * z obtains through right cyclic shift i.

Following formula multiply by

Then can obtain v (0), wherein $P_{p(x,k_b)}^{-1}=P_{z-p(x,k_b)}.$

V (0) is the value of the arbitrary check bit grouping in the check bit grouping, like this, can calculate the value of arbitrary check bit grouping v (0).

Step 102: the value of check bit during other check bit of value parallel computation that utilizes described arbitrary check bit to divide into groups divides into groups.

Concrete, can be according to the value of described arbitrary check bit grouping, and utilize the value of check bit in information bit sequence and other check bit grouping of check matrix parallel computation.

Preceding step has calculated arbitrary check bit v (0), in the step 102, and according to y (0), parallel computation v (1)～v (m _b-1).

Can calculate according to following formula:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

In the following formula

And u (j) can be as calculating in the prior art.

According to following formula, can calculate other each check bit grouping v (i), i=1,2 ..., m _b-1, and the calculating of each v (i) can only calculate according to v (0), and unlike needing to depend on v (i-1) in the prior art.

In addition, the check matrix H matrix constructs in advance, therefore, and check matrix

Can precompute and come and storage, thereby, in cataloged procedure, can directly read storage

Can further reduce the time delay of coding like this, promptly improve the efficient of coding.

This method embodiment can also comprise step 103: utilize the code word after information bit and check bit obtain encoding.

Information bit sequence s=[s (0), s (1) ..., s (K-1)] be given, so, calculate each v (i) after, just can be as the formula c=[sp of front] code word after obtaining encoding.

Below introduce the present invention second method embodiment.

The front is mentioned, for given information bit sequence s=[s (0), and s (1) ..., s (K-1)], the LDPC coding is to determine M check bit p=[p (0), p (1) ..., p (M-1)], the LDPC code word that obtains is c=[sp].Information bit sequence s is divided into groups:

s＝[u(0)，u(1)，…，u(k _b-1)]，u(i)＝[s _iz，s _iz+1，…，s _(i+1)z-1]

Subscript z in u (i) grouping is more than or equal to 1, and is special, and the situation that subscript z equals 1 is equivalent to not grouping.At this moment, be grouped into information bit sequence s as follows:

S=[s (0), s (1) ..., s (K-1)], then correspondingly, u (i)=[s _i]

Similarly, with check bit p be:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[P _i]。

Employed H matrix and aforementioned similar, as follows:

H _bSeparated into two parts, wherein H _B1Be systematic bits, H _B2Be Parity Check Bits, so

H _B2Can also be further divided into two parts, wherein vector h _bBe weighting, H ' _B2Be dual diagonal matrix.H ' _B2In the matrix, i represents line number, and j represents columns, and when i=j and i=j+1, matrix element is 1; Be 0 under other situation.

H in the fundamental matrix _b(0)=1, h _b(m _b-1)=1, the three are worth h _b(j)=1,0＜j＜(m _b-1), as follows:

Based on this, the present invention second method embodiment comprises:

Step S1: the value of calculating arbitrary check bit.

As previously mentioned, according to Hbm, can get

$P_{p(x,k_b)}v\left(0\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\underset{i=0}{\overset{m_b-1}{\mathrm{\Σ}}}{p}_{i,j}u\left(j\right)$

1≤x≤m wherein _b-2, Pi represents that the unit matrix of z * z obtains through right cyclic shift i.

Following formula multiply by

Then can obtain v (0), wherein $P_{p(x,k_b)}^{-1}=P_{z-p(x,k_b)}.$

V (0) is the value of arbitrary check bit, like this, can calculate the value of arbitrary check bit v (0).

Step S2: the value of utilizing other check bit of value parallel computation of described arbitrary check bit.

Concrete, can be according to the value of described arbitrary check bit, and utilize the value of information bit sequence and other check bit of check matrix parallel computation.

Preceding step has calculated arbitrary check bit v (0), among the step S2, and according to v (0), parallel computation v (1)～v (m _b-1).

Can calculate according to following formula:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is information bit sequence s=[s (0), s (1) ..., s (K-1)] in the value of a corresponding element s (i).

According to following formula, can calculate other each check bit v (i), i=1,2 ..., m _b-1, and the calculating of each v (i) can only calculate according to v (0), and unlike needing to depend on v (i-1) in the prior art.

In addition, the check matrix H matrix constructs in advance, therefore, and check matrix Can precompute and come and storage, thereby, in cataloged procedure, can directly read storage

Can further reduce the time delay of coding like this, promptly improve the efficient of coding.

This method embodiment can also comprise step S3: utilize the code word after information bit and check bit obtain encoding.

Information bit sequence s=[s (0), s (1) ..., s (K-1)] be given, so, calculate each v (i) after, just can be as the formula c=[sp of front] code word after obtaining encoding.

Below introduce the first device embodiment of the present invention.Fig. 2 shows the block diagram of device embodiment, as scheming:

The calculation element of check bit comprises initial check bit computing unit 21 in a kind of low density parity check code coding, check bit parallel computation unit 22 wherein,

Initial check bit computing unit 21 is used for the value of the initial check bit of computation of parity bits grouping;

Check bit parallel computation unit 22 is used for utilizing the value of described other check bit of initial value parallel computation check bit grouping.

Described check bit parallel computation unit 22 comprises some parallel computation devices 221, each parallel computation device 221 is according to the value of described arbitrary check bit grouping, and utilizes the value of check bit in information bit sequence and other check bit grouping of check matrix parallel computation.

The value of other check bit during described parallel computation device can divide into groups according to following formula parallel computation check bit:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is the class value in the information bit sequence s grouping, s=[u (0), and u (1) ..., u (k _b-1)], u (i)=[s _Iz, s _Iz+1..., s _{(i+1) z-1}].

Described device also comprises the code word computing unit, is used to utilize the code word after given information bit and described check bit obtain encoding.

Described code word computing unit 23 utilizes formula c=[sp] code word after obtaining encoding;

Wherein, s is given information bit, and described information bit sequence s is grouped into:

s＝[u(0)，u(1)，…，u(k _b-1)]，u(i)＝[s _iz，s _iz+1，…，s _(i+1)z-1]

Described check bit p is grouped into:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _iz，p _iz+1，…，p _(i+1)z-1]。

Described device can also comprise memory cell 24, is used for storage

Result of calculation, the m that described check bit parallel computation unit 22 comprises _b-1 parallel computation device 221 utilizes described cell stores

The value of other check bit in the grouping of parallel computation check bit.

Utilize the above-mentioned first device embodiment to realize that check bit Calculation Method and the aforementioned first method embodiment are similar.

Below introduce the present invention second device embodiment.Similar shown in this embodiment block diagram and Fig. 2.

The calculation element of check bit comprises initial check bit computing unit in a kind of low density parity check code coding, check bit parallel computation unit wherein,

Initial check bit computing unit is used to calculate the value of arbitrary check bit;

Check bit parallel computation unit is used to utilize the value of other check bit of value parallel computation of described arbitrary check bit.

Described check bit parallel computation unit comprises some parallel computation devices, and each parallel computation device is according to the value of described arbitrary check bit, and utilizes the value of information bit sequence and other check bit of check matrix parallel computation.

Described parallel computation device is according to the value of other check bit of following formula parallel computation:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is information bit sequence s=[s (0), s (1) ..., s (K-1)] in the value of a corresponding element s (i).

Described device can also comprise the code word computing unit, is used to utilize the code word after given information bit and described check bit obtain encoding.

Described code word computing unit utilizes formula c=[sp] code word after obtaining encoding;

Wherein, s is given information bit, and described information bit sequence s is grouped into:

s＝[s(0)，s(1)，…，s(K-1)]

Described check bit p is grouped into:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _i]。

Described device can also comprise memory cell, is used for storage

Result of calculation, the described cell stores of parallel computation devices use that described check bit parallel computation unit comprises

The value of other check bit of parallel computation.

Utilize the above-mentioned second device embodiment to realize that check bit Calculation Method and the aforementioned second method embodiment are similar.

By above embodiment as seen, after calculating the value of the arbitrary check bit grouping in the check bit grouping, after the value of check bit calculated the value of the initial check bit in the check bit grouping during other check bit of value parallel computation that utilizes described arbitrary check bit to divide into groups divided into groups, utilize the value of other check bit in the described initial value parallel computation check bit grouping, and then utilize code word after given information bit and described check bit obtain encoding, like this, other each check bit outside the initial check bit of value that calculates check bit in other check bit grouping that can walk abreast, thereby can reduce the time delay that coding calculates, improve the efficient of coding.

Though described the embodiment of the invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wish that appended claim comprises these distortion and variation and do not break away from spirit of the present invention.

Claims (24)

1, the computational methods of check bit in a kind of low density parity check code coding is characterized in that, comprising:

The value of the arbitrary check bit grouping in the computation of parity bits grouping;

The value of check bit during other check bit of value parallel computation that utilizes described arbitrary check bit to divide into groups divides into groups.

2, the method for claim 1 is characterized in that, the value of check bit comprised during described other check bit of value parallel computation that utilizes described arbitrary check bit to divide into groups divided into groups:

According to the value of described arbitrary check bit grouping, and utilize the value of check bit in information bit sequence and other check bit grouping of check matrix parallel computation.

3, method as claimed in claim 2 is characterized in that, described value according to arbitrary check bit grouping, and utilize the value of check bit in information bit sequence and other check bit grouping of check matrix parallel computation to comprise:

Value according to other check bit in the grouping of following formula parallel computation check bit:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is the class value in the information bit sequence s grouping, s=[u (0), and u (1) ..., u (k _b-1)], u (i)=[s _Iz, s _Iz+1..., s _{(i+1) z-1}].

4, the method for claim 1 is characterized in that, described method also comprises:

Utilize the code word after given information bit and described check bit obtain encoding.

5, method as claimed in claim 4 is characterized in that, describedly utilizes the code word after given information bit and described check bit obtain encoding to comprise:

Utilize formula c=[s p] code word after obtaining encoding;

Wherein, s is given information bit, and described information bit sequence s is grouped into:

s＝[u(0)，u(1)，…，u(k _b-1)]，u(i)＝[s _iz，s _iz+1，…，s _(i+1)z-1]

Described check bit p is grouped into:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _iz，p _iz+1，…，p _(i+1)z-1]。

6, method as claimed in claim 3 is characterized in that,

Direct reading pre-stored in the cataloged procedure

7, the computational methods of check bit in a kind of low density parity check code coding is characterized in that, comprising:

Calculate the value of arbitrary check bit;

Utilize the value of other check bit of value parallel computation of described arbitrary check bit.

8, method as claimed in claim 7 is characterized in that, the described value of other check bit of value parallel computation of described arbitrary check bit of utilizing comprises:

According to the value of described arbitrary check bit, and utilize the value of information bit sequence and other check bit of check matrix parallel computation.

9, method as claimed in claim 8 is characterized in that, described value according to arbitrary check bit, and utilize the value of information bit sequence and other check bit of check matrix parallel computation to comprise:

Value according to other check bit of following formula parallel computation:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is information bit sequence s=[s (0), s (1) ..., s (K-1)] in the value of a corresponding element s (i).

10, method as claimed in claim 7 is characterized in that, described method also comprises:

Utilize the code word after given information bit and described check bit obtain encoding.

11, method as claimed in claim 10 is characterized in that, describedly utilizes the code word after given information bit and described check bit obtain encoding to comprise:

Utilize formula c=[s p] code word after obtaining encoding;

Wherein, s is given information bit, and described information bit sequence s is grouped into:

s＝[s(0)，s(1)，…，s(K-1)]

Described check bit p is grouped into:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _i]。

12, method as claimed in claim 9 is characterized in that,

Direct reading pre-stored in the cataloged procedure

13, the calculation element of check bit in a kind of low density parity check code coding is characterized in that, comprises initial check bit computing unit, check bit parallel computation unit wherein,

Initial check bit computing unit is used for the value of arbitrary check bit grouping of computation of parity bits grouping;

Check bit parallel computation unit is used for utilizing the value of other check bit grouping check bit of value parallel computation of described arbitrary check bit grouping.

14, device as claimed in claim 13, it is characterized in that, described check bit parallel computation unit comprises some parallel computation devices, each parallel computation device is according to the value of described arbitrary check bit grouping, and utilizes the value of check bit in information bit sequence and other check bit grouping of check matrix parallel computation.

15, device as claimed in claim 14 is characterized in that, the value of other check bit during described parallel computation device divides into groups according to following formula parallel computation check bit:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is the class value in the information bit sequence s grouping, s=[u (0), and u (1) ..., u (k _b-1)], u (i)=[s _Iz, s _Iz+1..., s _{(i+1) z-1}].

16, device as claimed in claim 13 is characterized in that, also comprises the code word computing unit, is used to utilize the code word after given information bit and described check bit obtain encoding.

17, device as claimed in claim 16 is characterized in that, described code word computing unit utilizes formula c=[s p] code word after obtaining encoding;

Wherein, s is given information bit, and described information bit sequence s is grouped into:

s＝[u(0)，u(1)，…，u(k _b-1)]，u(i)＝[s _iz，s _iz+1，…，s( _i+1)z-1]

Described check bit p is grouped into:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _iz，p _iz+1，…，p _(i+1)z-1]。

18, device as claimed in claim 13 is characterized in that, also comprises memory cell, is used for storage

Result of calculation, the described cell stores of parallel computation devices use that described check bit parallel computation unit comprises

The value of other check bit in the grouping of parallel computation check bit.

19, the calculation element of check bit in a kind of low density parity check code coding is characterized in that, comprises initial check bit computing unit, check bit parallel computation unit wherein,

Initial check bit computing unit is used to calculate the value of arbitrary check bit;

Check bit parallel computation unit is used to utilize the value of other check bit of value parallel computation of described arbitrary check bit.

20, device as claimed in claim 19, it is characterized in that, described check bit parallel computation unit comprises some parallel computation devices, and each parallel computation device is according to the value of described arbitrary check bit, and utilizes the value of information bit sequence and other check bit of check matrix parallel computation.

21, device as claimed in claim 20 is characterized in that, described parallel computation device is according to the value of other check bit of following formula parallel computation:

$\begin{array}{cc}v\left(i\right)=\underset{j=0}{\overset{k_b-1}{\mathrm{\Σ}}}\left(\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,j)}\right)u\left(j\right)+\underset{q=0}{\overset{i-1}{\mathrm{\Σ}}}{P}_{p(q,k_b)}v\left(0\right)& i=1,\·\·\·,m_b-1\end{array}$

Wherein,

Obtained by the check matrix H matrix computations of constructing in advance, described u (j) is information bit sequence s=[s (0), s (1) ..., s (K-1)] in the value of a corresponding element s (i).

22, device as claimed in claim 19 is characterized in that, also comprises the code word computing unit, is used to utilize the code word after given information bit and described check bit obtain encoding.

23, device as claimed in claim 22 is characterized in that, described code word computing unit utilizes formula c=[s p] code word after obtaining encoding;

Wherein, s is given information bit, and described information bit sequence s is grouped into:

s＝[s(0)，s(1)，…，s(K-1)]

Described check bit p is grouped into:

p＝[v(0)，v(1)，…，v(m _b-1)]，v(i)＝[p _i]。

24, device as claimed in claim 19 is characterized in that, also comprises memory cell, is used for storage

Result of calculation, the described cell stores of parallel computation devices use that described check bit parallel computation unit comprises

The value of other check bit of parallel computation.

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