CN101464802A - Updating system of controller programming code, network memory device with the same and its updating method - Google Patents
Updating system of controller programming code, network memory device with the same and its updating method Download PDFInfo
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- CN101464802A CN101464802A CNA2007103005971A CN200710300597A CN101464802A CN 101464802 A CN101464802 A CN 101464802A CN A2007103005971 A CNA2007103005971 A CN A2007103005971A CN 200710300597 A CN200710300597 A CN 200710300597A CN 101464802 A CN101464802 A CN 101464802A
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Abstract
The invention discloses an updating system used for a controller programming code, network storage equipment provided with the updating system, and an updating method thereof. The invention comprises an application unit, a core cache, a dual channel control module and a universal input/output control module. The application unit receives an updating command and a programming code document from a network; the core cache downloads the programming code document according to the updating command; the dual channel control module is used for reading the programming code document stored in the core cache and converting the programming code document to a clock signal and a data signal; and the universal input/output control module is provided with a clock channel and a data channel, which are used for transmitting the clock signal and the data signal to the network storage equipment, and updating a source programming code stored in a controller by utilizing the clock signal and the data signal.
Description
Technical field
The invention relates to a kind of update system and update method thereof, particularly relevant for a kind of update system and update method thereof of director demon sign indicating number of foundation two wire protocols, it sees through far-end network and carries out a update command and receive a programming code document, be stored in original program sign indicating number in the controller with renewal, the invention still further relates to the network storage equipment of update system with director demon sign indicating number.
Background technology
Along with the maturation of infotech and the fast development of network communication, the application that sees through the internet access data is very general, for example user computer is connected in via network access and shares out network storage device on the internet, for example addition type network storage medium (Network Attached Storage, NAS).Yet in order to make described network storage device have the more applications scope, need to revise its inner original program sign indicating number, that is the procedure code that single-chip is carried out in the modification network storage device, perhaps need debug and again during the new procedure code of burning when described procedure code, must see through boundary scan (the Joint Test Action Group of described network storage device inside, JTAG) Port is revised original procedure code or new procedure code is burned onto in the single-chip, causes its refresh routine inconvenient in the extreme.
In other words, in the manufacture process of network storage device, in order to upgrade the procedure code in the single-chip, the development board of described network storage device is provided with the JTAG Port, thereby takies the usable area of development board.Secondly, revised procedure code repeatedly must be burned onto described single-chip in the process of procedure code debug, till procedure code is by test, so the developer must purchase special-purpose cd-rom recorder and come the revised procedure code of burning, and cost is higher.And after network storage device was sold to the user, how manufacturer must manipulate program, replication tool and the using method instruction user of burning, quite inconvenient.In addition, when user's desire is upgraded the procedure code of single-chip, must take the shell of network storage device apart, just can carry out the burning of new procedures sign indicating number, because after described network storage device dispatched from the factory, the JTAG Port was enclosed in the casing, very inconvenience.Therefore need a kind of new-type updating device of development and update method.
Summary of the invention
An object of the present invention is to provide a kind of update system and update method thereof of director demon sign indicating number, be applicable to the network storage equipment, two output/input Ports by update system are simulated two wire protocols, replacing existing JTAG Port, and utilize two output/input Ports to be written into the non-voltile memory of a procedure code to described controller.
Another purpose of the present invention provides a kind of update system and update method thereof of director demon sign indicating number, be applicable to the network storage equipment, make the client see through the needed procedure code of network selecting, and utilize described two wire protocols to be written into selected procedure code recordable paper, the problem that solves recordable paper that the client must mail by manufacturer when upgrading single-chip at every turn and replication tool and need repeat to install the set environment of burning.
Another object of the present invention provides a kind of update system and update method thereof of director demon sign indicating number, be applicable to the network storage equipment, make the client see through the needed procedure code of network selecting, and utilize described two wire protocols to be written into selected procedure code recordable paper, avoid taking apart the problem that product could upgrade the procedure code of single-chip.
The update system of director demon sign indicating number of the present invention comprises a primary processor and a controller, and primary processor is coupled to controller via clock passage and data channel.Primary processor comprises application program unit, core cache, binary channels control module and general I/O control module.Specifically, application program unit receives update command and the described programming code document from described network.The described update command of core cache foundation is downloaded the programming code document from described application program unit, and is stored in described core cache.The binary channels control module is in order to reading the programming code document that is stored in described core cache, and converts described programming code document to a clock signal and a data-signal.General I/O control module is in order to receive described clock signal and described data-signal, and have a clock passage and a data channel, to transmit described clock signal and described data-signal respectively, upgrade the original program sign indicating number that is stored in the controller to utilize described clock signal and described data-signal to the described network storage equipment.
Application program unit more comprises socket module and I/O control module, and the socket module is coupled to described network, and the I/O control module couples described socket module to described binary channels control module.The socket module sees through described network and communicates by letter with described server and the foundation of described user computer, to receive described update command and described programming code document.The I/O control module is in order to transmit described update command to described binary channels control module.
Described controller more comprises two wire protocol modules, sequencing unit and non-voltile memory.Two wire protocol modules receive respectively from the described clock signal of described clock passage and described data channel and described data-signal.The sequencing unit has a control register and a data register, in order to writing described update command to described control register, and writes described programming code document to described data register.Non-voltile memory has described original program sign indicating number in order to storage, and according to described update command, described sequencing unit writes to described non-voltile memory with described programming code document, to cover described original program sign indicating number.
According to above-mentioned, the binary channels control module of the update system of director demon sign indicating number is electrically connected at the controller with two wire protocol modules via general I/O control module, the step of the flash memory in the controller being carried out sequencing according to clock passage and data channel is to replace the original program sign indicating number in the flash memory.That is utilize two output/input Ports of update system to come simulated clock simulation clock passage and data channel, for example use the universal output of primary processor/go into Port to simulate two wire protocol interfaces, make primary processor and controller carry out address and data communication transmission.
The present invention's update method comprises the following steps:
(a) update system of director demon sign indicating number is carried out initialization.
(b) utilize the network service code via the network opening controller, make user computer and update system carry out communication, to be in the control model state.
(c) application program unit sees through described network and receives from a programming code document of described server and from the update command of described user computer.
(d) application program unit is selected a control model according to update command, comprises the pattern of writing, erasing mode and correction mode.
(d1) the binary channels control module writes to described programming code document according to update command the non-voltile memory of controller, that is when application program unit receives described update command, via the described clock signal of described clock channel transfer to controller, transmit described programming code document to described controller, with the original program sign indicating number in the non-voltile memory that upgrades described controller according to described clock signal via described data channel simultaneously.
(d2) the binary channels control module is wiped original program sign indicating number within the described non-voltile memory according to update command.
(d3) the binary channels control module is calculated the total value of the programming code document within the described non-voltile memory according to update command, to check the correctness of described programming code document.When described programming code document incorrect, the clock signal of described clock passage of resetting.
(e) update system is passed the operation information of control model and execution result back to user computer.
For the present invention's foregoing can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 discloses the calcspar according to the update system of the procedure code of embodiment of the invention middle controller;
Fig. 2 discloses the detailed block diagram according to the update system of the procedure code of Fig. 1 middle controller of the present invention;
Fig. 3 A discloses the synoptic diagram according to the kenel module of binary channels control module among Fig. 2 of the present invention;
Fig. 3 B discloses the synoptic diagram according to the register cell of binary channels control module among Fig. 2 of the present invention;
Fig. 4 discloses the detailed block diagram according to Fig. 2 middle controller of the present invention.
5A-5D figure discloses the read/write sequential chart of simulating two wire protocols according to general I/O (GPIO) control module in the embodiment of the invention;
Fig. 6 discloses the process flow diagram according to the update method of the procedure code of implementation controller in the embodiment of the invention.
[main element symbol description]
100 update system, 102 user computers
104 servers, 106 primary processors
108 controller 110a clock passages
114 core cache, 116 binary channels control modules
116a kenel module 116b register cell
118 general I/O control module 120a clock passages
120b data channel 122a control register
302 erase pagings 304 write the flash memory block
306 read flash memory block 308 writes address register
310 read address registers 312 write data register
314 read data register
Embodiment
Fig. 1 discloses the calcspar according to the update system 100 of embodiment of the invention middle controller procedure code.Described update system 100 sees through network and is respectively coupled to user computer 102 and server 104, mainly comprises a primary processor 106 and controller 108.When upgrading, described user computer 102 is chosen via network and is stored in server 104 1 programming code document, and sends a update command to update system 100.Then the primary processor 106 of update system 100 is downloaded described programming code document according to described update command, and sees through one or two wire protocol (two-channel protocol), utilizes described programming code document to upgrade the original program sign indicating number that is stored in the controller 102.Wherein, programming code document is writable execute file for example, described two wire protocols are meant clock passage 110a and data channel 110b, in order to transmit clock signal and the data-signal corresponding to described programming code document respectively, to reach the purpose of the procedure code in the update controller 108.In one embodiment, the clock passage 110a of two wire protocols of micro controller 108 is connected in a general I/O port of primary processor 106, and the data channel 110b of described two wire protocols is connected in another general I/O port of primary processor 106.The update system 100 of director demon sign indicating number of the present invention is applicable to addition type network storage medium (NAS), primary processor 106 for example is processor or the similar processor of model C PU-8313E, and controller 108 for example is the single-chip or the similar control chip of 8051 series, in the preferred embodiment, controller 108 is the single-chip with two wire protocols for example.The technology contents of update system 100 will be in hereinafter describing in detail.
Fig. 2 discloses the detailed block diagram according to the update system 100 of Fig. 1 middle controller procedure code of the present invention.Update system 100 comprises primary processor 106 and controller 108, and primary processor 106 is coupled to controller 108 via clock passage 110a and data channel 110b.Primary processor 106 comprises application program unit 112, core cache 114, binary channels control module 116 and general I/O, and (general purposeinput/output, GPIO) control module 118.Application program unit 112 via network-coupled in user computer 102 and server 104, and application program unit 112 is respectively coupled to core cache 114 and binary channels control module 116, binary channels control module 116 is respectively coupled to core cache 114 and general I/O (GPIO) control module 118, and general I/O (GPIO) control module 118 is coupled to controller 108.Described network can be wired as connect with cable, or wireless network is as meeting the technology of bluetooth (Bluetooth) standard; Also can be Wide Area Network (WAN), as internet (Internet); Or LAN (LAN), as enterprise network (Intranet) or Ethernet (Ethernet).
Specifically, application program unit 112 receptions are from the update command and the described programming code document of described network.The described update command of core cache 114 foundations is downloaded the programming code document from described application program unit 112, and is stored in core cache 114.Binary channels control module 116 is in order to reading the programming code document that is stored in core cache 114, and converts described programming code document to a clock signal and a data-signal.General I/O control module 118 is in order to receive described clock signal and described data-signal, and have clock passage 110a and data channel 110b, transmitting described clock signal and described data-signal respectively to the described network storage equipment, to utilize described clock signal and described data-signal to upgrade to be stored in the original program sign indicating number in the controller 108.
Described binary channels control module 116 more comprises kenel module 116a and register cell 116b, cooperates respectively with reference to figure 3A and Fig. 3 B with Fig. 1.
With reference to figure 3A, it discloses the synoptic diagram according to the kenel module of binary channels control module 116 among Fig. 2 of the present invention.Kenel module 116a is coupled to described I/O control module 112b, in order to store the control kenel of described controller 108, with the access kenel of management non-voltile memory.The control kenel of described controller 108 be selected from kenel, the erase paging (erase flashpage) 302 of erase device (erase flash device) 300 kenel, write the kenel of flash memory block (write flash block) 304 and read a kind of in the kenel that the kenel of flash memory block (read flash block) 306 forms.When update system 100 is erasure controller 102 according to the renewal kenel of update command, then be appointed as erase device 300.When update system 100 is paging when wiping according to the renewal kenel of update command, then be appointed as and write flash memory block 304.To be according to the renewal kenel of update command that block is write fashionable when update system 100, then is appointed as and reads flash memory block 306.
With reference to figure 3B, it discloses the synoptic diagram according to the register cell of binary channels control module among Fig. 2 of the present invention.Register cell 116b is coupled to described kenel module 116a, has a plurality of registers, and the described update command of foundation reads from described core cache 114 described programming code document and is stored in described register.In one embodiment, according to two wire protocols, wherein said register is selected from and writes address register (write addressregister) 308, read address register (read address register) 310, writes a kind of in data register (write data register) 312 and the read data register (read dataregister) 314.Binary channels control module 116 is analyzed the programming code document that is stored in core cache 112, the address information of desiring to write to controller 108 left in write address register 308, leave the address information of desiring Read Controller 108 in read address register 310, the deposit data of desiring to write to controller 108 is being write data register 312, and the deposit data that will desire Read Controller 108 is in read data register 314.
Described controller 108 more comprises two wire protocol modules 120, sequencing unit 122 and non-voltile memory 124.Described two wire protocol modules 120 couple described general I/O control module 118 to described sequencing unit 122, and described sequencing unit 122 is coupled to described non-voltile memory 124.Two wire protocol modules 120 receive respectively from described clock passage 110a and described clock signal of described data channel 110b and described data-signal.Sequencing unit 122 has control register 122a and data register 122b, as shown in Figure 4, in order to writing described update command to described control register 122a, and writes described programming code document to described data register 122b.Non-voltile memory 124 has described original program sign indicating number in order to storage, and according to described update command, described sequencing unit 122 writes to described non-voltile memory 124 with described programming code document, to cover described original program sign indicating number.Non-voltile memory 124 is flash memory (flash memory) for example.
In one embodiment, described sequencing unit 122 is according to described update command, to wipe the original program sign indicating number within the described non-voltile memory 124.In another embodiment, described sequencing unit 122 is according to described update command, with the total value (check sum) of calculating the programming code document within the described non-voltile memory 124, to check the correctness of described programming code document.
According to above-mentioned, the binary channels control module 116 of the update system 100 of director demon sign indicating number is electrically connected at the controller 108 with two wire protocol modules 120 via general I/O control module 118, the step of the flash memorys 124 in the controller 108 being carried out sequencing according to clock passage 120a and data channel 120b is to replace the original program sign indicating number in the flash memory 124.That is utilize two output/input Ports of update system 100 to come simulated clock simulation clock passage 120a and data channel 120b, for example use the universal output of primary processor 106/go into Port (GPIO) to simulate two wire protocol interfaces, make primary processor 106 and controller 108 carry out address and data communication transmission.
5A-5D figure discloses the read/write sequential chart according to 118 simulations of general I/O (GPIO) control module in the embodiment of the invention, two wire protocols.According to two wire protocols, when update system 100 was received update command, control register unit 114 and clock source 118 were via clock passage 120a and data channel 120b difference clock signal " C2CK " and data-signal " C2D ".
Fig. 5 A explicit address register write sequential, according to clock signal " C2CK ", the time section of data-signal " C2D " is in regular turn for beginning (START) section, instruction (INS) section, address (ADDRESS) section and stop (STOP) section.In one embodiment, make the invalid activation of data.Then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 10 (chronomeres).Form data high levle state then, make the effective activation of data again, then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 30 (chronomeres) for example.Form data high levle state subsequently, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 30 (chronomeres).The address parameter that will write address register then is sent to described sequencing unit 122 via described general I/O control module 118, and forms data high levle and data low level.Make the invalid activation of data at last, make the clock signal of two wire protocol modules open a sluice gate to start again, finish binary channels and finish signal.
Fig. 5 B explicit address register read sequential, according to clock signal " C2CK ", the time section of data-signal " C2D " is in regular turn for beginning (START) section, instruction (INS) section, address (ADDRESS) section and stop (STOP) section.In one embodiment, make the invalid activation of data.Then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 10 (chronomeres).Form data low level state then, make the effective activation of data again, then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 30 (chronomeres) for example.Form data high levle state subsequently, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 30 (chronomeres).To be sent to read address register from described general I/O control module 118 then.Make the invalid activation of data at last, make the clock signal of two wire protocol modules open a sluice gate to start again, finish binary channels and finish signal, return address parameter.
Fig. 5 C video data register write sequential, according to clock signal " C2CK ", the time section of data-signal " C2D " is in regular turn for beginning (START) section, instruction (INS) section, data length (LENGTH) section, data (DATA) section, wait (WAIT) section and stopping (STOP) section.In one embodiment, make the invalid activation of data.Then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 10 (chronomeres).Form data high levle state then, make the effective activation of data again, then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 30 (chronomeres) for example.Form data low level state subsequently, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 30 (chronomeres).Form data low level state then, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 20 (chronomeres); Form data low level state, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 20 (chronomeres).The data parameters that will write address register then is sent to described sequencing unit 122 via general I/O control module 118, and forms data high levle and data low level.Then make the invalid activation of data, continue to make the clock signal of two wire protocol modules to open a sluice gate to start again.Make the invalid activation of data at last, make the clock signal of two wire protocol modules open a sluice gate to start again, finish binary channels and finish signal.
Reading in the sequential of Fig. 5 D video data register, according to clock signal " C2CK ", the time section of data-signal " C2D " is in regular turn for beginning (START) section, instruction (INS) section, data length (LENGTH) section, wait (WAIT) section, data (DATA) section and stopping (STOP) section.In one embodiment, make the invalid activation of data.Then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 10 (chronomeres).Form data low level state then, make the effective activation of data again, then make the clock signal of two wire protocol modules open a sluice gate to start, and its designated value is 30 (chronomeres) for example.Form data low level state subsequently, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 30 (chronomeres).Form data low level state then, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 20 (chronomeres); Form data low level state, make the clock signal of two wire protocol modules open a sluice gate to start again, and its designated value is 20 (chronomeres).Then make the invalid activation of data, continue to make the clock signal of two wire protocol modules to open a sluice gate to start again.The data parameters that will write address register then is sent to described sequencing unit 122 via general I/O control module 118.Make the invalid activation of data at last, make the clock signal of two wire protocol modules open a sluice gate to start again, finish binary channels and finish signal, return data parameter.
According to above-mentioned, the update system of the procedure code of controller of the present invention is by two wire protocol interfaces, and the step of the flash memory in the controller 126 being carried out sequencing according to clock passage 120a and data channel 120b is to replace the original program sign indicating number in the flash memory 126.Or simulate two wire protocols by two output/input Ports of update system, to be written into the non-voltile memory of a procedure code to described controller.The present invention is applicable to general operating system, for example LINUX system or similarly system.
With reference to figure 1, Fig. 2 and Fig. 6, Fig. 6 discloses the process flow diagram according to the update method of the procedure code of implementation controller in the embodiment of the invention.The update method of the procedure code of controller of the present invention is applicable to the network storage equipment, the described network storage equipment sees through network-coupled in server 104 and user computer 102, described user computer 102 sends a update command, and described update method comprises the following steps:
In step S500, the binary channels control module 116 of the update system 100 of the procedure code of controller is carried out initialization.
In step S502, utilize the network service code via network opening controller 108, make user computer 102 and update system 100 carry out communication, to be in the control model state.If opening controller 108 not, then withdraw from the binary channels control module 116 of update system 100.
In step S504, application program unit 112 sees through described network and receives from a programming code document of described server 104 and from the update command of described user computer 102.
In step S506, application program unit 112 is selected a control model according to update command, comprises the pattern of writing, erasing mode and correction mode.
Writing in the pattern of step S506a, binary channels control module 116 writes to described programming code document according to update command the non-voltile memory 124 of controller 108, that is when application program unit 112 receives described update command, via the described clock signal of described clock channel transfer to controller 108, transmit described programming code document to described controller 108 according to described clock signal via described data channel simultaneously, with the original program sign indicating number in the non-voltile memory 124 that upgrades described controller 108.In one embodiment, binary channels control module 116 reads data in the core cache 114 in batches to register cell 116b, in regular turn the data in the register cell 116b are write to non-voltile memory 124 then, till the data in running through core cache 114.Finish after the write step S506a closing controller 108 and withdraw from update system 100.
In the erasing mode of step S506b, binary channels control module 116 is wiped original program sign indicating number within the described non-voltile memory 124 according to update command.Finish after the erase step S506b closing controller 108.
In the correction mode of step S506c, binary channels control module 116 is calculated the total value of the programming code document within the described non-voltile memory 124 according to update command, to check the correctness of described programming code document.When described programming code document incorrect, the clock signal of described clock passage of resetting.Finish after the aligning step S506c closing controller 108.
In step S508, update system 100 is passed the operation information of control model and execution result back to user computer 102.
Characteristics of the present invention comprise: (1) sees through the network original program sign indicating number of update controller by the way of distal end; (2) have the function of burning program code data, need not use extra cd-rom recorder, saved exploitation and use cost; (3) solve the problem that burning data that the client must mail by manufacturer when upgrading single-chip at every turn and replication tool and need repeating installed the set environment of burning; And (4) client utilizes two line technologies to be written into selected procedure code burning data, the problem of avoiding taking apart product.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, the technical staff in the technical field of the invention, without departing from the spirit and scope of the invention; when can doing various changes and retouching, so the present invention's protection domain is when being as the criterion with claim.
Claims (20)
1. the update system of a director demon sign indicating number, be arranged in the network storage equipment, the described network storage equipment sees through a network-coupled in a server and a user computer, described user computer sends a update command, make the described network storage equipment see through the programming code document of described network reception from described server, described update system comprises:
One application program unit receives update command and described programming code document from described network;
One core cache according to the programming code document of described update command download from described application program unit, and is stored in described core cache;
One binary channels control module is respectively coupled to described application program unit and described core cache, in order to reading the described programming code document that is stored in described core cache, and converts described programming code document to a clock signal and a data-signal; And
One general I/O control module, in order to receive described clock signal and described data-signal, and have a clock passage and a data channel, to transmit described clock signal and described data-signal respectively to the described network storage equipment, utilize described clock signal and described data-signal, be stored in original program sign indicating number in this controller with renewal.
2. update system as claimed in claim 1 is characterized in that, described application program unit more comprises:
One socket module sees through described network and communicates by letter with described server and the foundation of described user computer, to receive described update command and described programming code document; And
One I/O control module is in order to transmit described update command to described binary channels control module.
3. update system as claimed in claim 2 is characterized in that, described binary channels control module more comprises:
One kenel module is coupled to described I/O control module, in order to store a control kenel of described controller; And
One register cell is coupled to described kenel module, has a plurality of registers, and the described update command of foundation reads from the programming code document of described core cache and is stored in these registers.
4. update system as claimed in claim 3, it is characterized in that, the control kenel of described controller be selected from kenel, the erase paging of erase device kenel, write the kenel of flash memory block and read a kind of in the kenel that the kenel of flash memory block forms.
5. update system as claimed in claim 3 is characterized in that, the register of described register cell is selected from and writes address register, read address register, writes a kind of in data register and the read data register.
6. update system as claimed in claim 3 is characterized in that, described controller more comprises:
One or two wire protocol module is coupled to described general I/O control module, receives clock signal and data-signal from described clock passage and described data channel respectively;
One sequencing unit is coupled to described two wire protocol modules, has a control register and a data register, in order to writing described update command to described control register, and writes described programming code document to described data register; And
One non-voltile memory has described original program sign indicating number, and according to described update command, described sequencing unit writes to described non-voltile memory with described programming code document, to cover described original program sign indicating number.
7. update system as claimed in claim 6 is characterized in that, described sequencing unit is according to described update command, to wipe the original program sign indicating number within the described non-voltile memory.
8. update system as claimed in claim 6 is characterized in that, described sequencing unit is according to described update command, to calculate the total value of the programming code document within the described non-voltile memory, to check the correctness of described programming code document.
9. update system as claimed in claim 6 is characterized in that, when described programming code document incorrect, and the described binary channels control module clock signal of described clock passage of resetting.
10. the network storage equipment of the update system of the procedure code with controller, the described network storage equipment sees through a network-coupled in a server and a user computer, described user computer sends a update command, make the described network storage equipment see through the programming code document of described network reception from described server, the described network storage equipment comprises:
One application program unit receives described update command and described programming code document from described network;
One core cache according to the described programming code document of described update command download from described application program unit, and is stored in described core cache;
One binary channels control module is respectively coupled to described application program unit and described core cache, in order to reading the described programming code document that is stored in described core cache, and converts described programming code document to a clock signal and a data-signal; And
One general I/O control module, in order to receive described clock signal and described data-signal, and have a clock passage and a data channel, to transmit described clock signal and described data-signal respectively to the described network storage equipment, utilize described clock signal and described data-signal, be stored in original program sign indicating number in the controller with renewal.
11. the network storage equipment as claimed in claim 10 is characterized in that, described application program unit more comprises:
One socket module sees through described network and communicates by letter with described server and the foundation of described user computer, to receive described update command and described programming code document; And
One I/O control module is in order to transmit described update command to described binary channels control module.
12. the network storage equipment as claimed in claim 11 is characterized in that, described binary channels control module more comprises:
One kenel module is coupled to described I/O control module, in order to store a control kenel of described controller; And
One register cell is coupled to described kenel module, has a plurality of registers, and the described update command of foundation reads from the programming code document of described core cache and is stored in these registers.
13. the network storage equipment as claimed in claim 12, it is characterized in that, the described control kenel system of described controller be selected from kenel, the erase paging of erase device kenel, write the kenel of flash memory block and read a kind of in the kenel that the kenel of flash memory block forms.
14. the network storage equipment as claimed in claim 12 is characterized in that, the register of described register cell is selected from and writes address register, read address register, writes a kind of in data register and the read data register.
15. the network storage equipment as claimed in claim 12 is characterized in that, described controller more comprises:
One or two wire protocol module is coupled to described general I/O control module, receives clock signal and data-signal from described clock passage and described data channel respectively;
One sequencing unit is coupled to described two wire protocol modules, has a control register and a data register, in order to writing described update command to described control register, and writes described programming code document to described data register; And
One non-voltile memory has the original program sign indicating number, and according to described update command, described sequencing unit writes to described non-voltile memory with described programming code document, to cover described original program sign indicating number.
16. the network storage equipment as claimed in claim 15 is characterized in that, described sequencing unit is according to described update command, to wipe the original program sign indicating number within the described non-voltile memory.
17. the network storage equipment as claimed in claim 15 is characterized in that, described sequencing unit is according to described update command, to calculate the total value of the programming code document within the described non-voltile memory, to check the correctness of described programming code document.
18. the update method of a director demon sign indicating number, be applicable to a network storage equipment, the described network storage equipment sees through network-coupled in a server and a user computer, and described user computer sends a update command to the described network storage equipment, and described update method comprises the following steps:
Carry out the initialization of a update system;
Seeing through described network receives from the programming code document of described server and from the update command of described user computer;
Select a control model according to described update command, described control model comprises the pattern of writing, erasing mode and correction mode; And
When being in the said write pattern, and when described update system receives described update command, via the controller of a clock channel transfer one clock signal to described update system, transmit described programming code document to described controller, to upgrade the original program sign indicating number in the described controller according to described clock signal via described data channel simultaneously.
19. update method as claimed in claim 18 is characterized in that, when being in described erasing mode, wipes original program sign indicating number in the described controller according to update command.
20. update method as claimed in claim 18 is characterized in that, when being in described correction mode, calculates the total value of the programming code document in the described controller according to update command, to check the correctness of described programming code document.
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| CNA2007103005971A CN101464802A (en) | 2007-12-21 | 2007-12-21 | Updating system of controller programming code, network memory device with the same and its updating method |
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| CNA2007103005971A CN101464802A (en) | 2007-12-21 | 2007-12-21 | Updating system of controller programming code, network memory device with the same and its updating method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253845A (en) * | 2010-05-20 | 2011-11-23 | 英业达科技有限公司 | Server system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253845A (en) * | 2010-05-20 | 2011-11-23 | 英业达科技有限公司 | Server system |
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