CN101459195B - Electrolytic transistor and manufacturing process thereof - Google Patents
Electrolytic transistor and manufacturing process thereof Download PDFInfo
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- CN101459195B CN101459195B CN200810214451XA CN200810214451A CN101459195B CN 101459195 B CN101459195 B CN 101459195B CN 200810214451X A CN200810214451X A CN 200810214451XA CN 200810214451 A CN200810214451 A CN 200810214451A CN 101459195 B CN101459195 B CN 101459195B
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Abstract
An electrolyte transistor comprises a grid structure, two source electrode/ drain electrodes, an electrolyte layer and a buried type conducting layer. The grid structure comprises a grid dielectric layer and a grid which are located above a substrate. The two source electrodes/drain electrodes are separated, which are located above the substrate located on two sides of the grid structure. The electrolyte layer is located between the two source electrodes/drain electrodes and is contacted with the two source electrodes/drain electrodes, is also located between the grid structure and the substrate and is contacted with the grid structure and the substrate. The buried type conducting layer is located between the electrolyte layer and the substrate. The electrolyte layer between the two source electrodes/drain electrodes is provided with grooves, and the electric conductivity of the electrolyte layer can be changed through the oxidation-reduction reaction of the electrolyte layer to open or close the grooves.
Description
[technical field]
The present invention relates to a kind of transistor and manufacture method thereof, particularly relate to a kind of electrolytic transistor and manufacture method thereof.
[background technology]
Transistor is the most basic electronic component during semiconductor is made.Typical transistor is a kind of MOS field-effect transistor.MOS field-effect transistor be by metal oxide layer the semiconductor structure that is similar to electric capacity that forms that is stacked in regular turn.Because MOS field-effect transistor is formed on the rigid silicon substrate, its cost is higher and be subjected to bigger restriction on using.
Existing at present research uses semi-conducting polymer to be manufactured with field effect transistors.Organic field effect tube is to be used as channel with semi-conducting polymer, and its operation principle mainly is to see through extra electric field to make charged carriers characteristic generation change in the semi-conducting polymer.The advantage of organic field effect tube is at chilling process (＜100 ℃) engineering properties preferably to be arranged, and the element overall weight is light more a lot of than conventional transistor.Moreover its manufacturing cost is lower, also can save time.In addition, it can make the large tracts of land element, and can be applicable to the pliability electronic component.
Another kind of transistor is the electrochemical transistor element, and it is to utilize the electrochemical redox reaction of organic material to reach its effect.Organic material in this kind electrochemical transistor assembly mainly comprises electrolyte and conducting polymer, and it can and go back between the ortho states and change in oxidation state.In other words, organic material has two states at least, wherein a kind of ortho states of going back for low electric conductivity; And another kind is that conductivity is relatively than the former high oxidation state.This kind element can utilize the difference of its electrical conductivity to be applied to inductor, for example is to be used for the oxidation of sensing solution.Yet the cost of manufacture of this kind element is higher and make comparatively difficulty usually, is difficult to a large amount of manufacturings.
[summary of the invention]
The present invention proposes a kind of electrolytic transistor, and it comprises grid structure (gate structure), two source/drains (source/drain), dielectric substrate and buried type conducting layer.Grid structure comprises gate dielectric (gate dielectric layer) and grid, is positioned at the substrate top.Two source/drains, the substrate top that is positioned at the grid structure both sides separated from one another.Dielectric substrate, between two source/drains and be in contact with it, and between grid structure and substrate and be in contact with it.Buried type conducting layer is between dielectric substrate and substrate.Dielectric layer is positioned at around the buried type conducting layer, and is covered on the buried type conducting layer and has opening, expose portion buried type conducting layer, and isolated buried type conducting layer and two source/drains.This dielectric substrate is formed on the opening of dielectric layer and with buried type conducting layer and electrically connects, and the dielectric substrate between two source/drains has raceway groove, changes its conductivity by the dielectric substrate redox reaction, to open or to close raceway groove.
The present invention proposes a kind of manufacture method of electrolytic transistor.This method is included in and forms buried type conducting layer on the substrate.Then, form dielectric layer on substrate, dielectric layer has opening, exposes buried type conducting layer.Then, on the dielectric layer of opening both sides, form source/drain respectively.Afterwards, between two source/drains, form dielectric substrate.Then, on dielectric substrate, form gate dielectric and grid, to constitute grid structure.
The present invention's electrolytic transistor, it can use flexible base plate to make, and manufacture method is simple and easy, can make in a large number.
For the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described below in detail.
[description of drawings]
Figure 1A to 1D is the manufacturing process generalized section of a kind of electrolytic transistor of illustrating according to embodiment of the present invention.
[main description of reference numerals]
100: substrate 110: gate dielectric
102: buried type conducting layer 112: opening
104: dielectric layer 114: grid
106: source/drain 116: grid structure
108: dielectric substrate 120: raceway groove
[embodiment]
Figure 1A to 1D is the manufacturing process generalized section of a kind of electrolytic transistor of illustrating according to embodiment of the present invention.
Please refer to Figure 1A, on substrate 100, form buried type conducting layer 102.Substrate 100 can be rigid substrate or bendable substrate.Rigid substrate for example has silicon (SOI) substrate on semiconductor substrate such as silicon substrate, semiconducting compound substrate such as sige substrate, insulated substrate such as glass or the insulating barrier.Bendable substrate is plastic base such as polyethylene terephthalate (Polyethylene Terephthalate for example, PET), Polyethylene Naphthalate (Poly (ethylene naphthalene-2,6-dicarboxylate), PEN), polyethylene (Polyethylene), polypropylene, Merlon (Polycarbonate); Paper; Overlay paper (coatedpaper), its coating such as resin, polyethylene or polyphenyl alkene; Corrugated board (corrugated board) or laminated paper (paper laminate).The material of buried type conducting layer 102 for example is metal, metal alloy or metal nitride, as aluminium, gold, silver, copper, tungsten, nickel, albronze, titanium nitride, tantalum nitride, molybdenum nitride or its combination.Buried type conducting layer 102 can adopt ink-jet printing technology directly to form.The formation method of buried type conducting layer 102 also can be earlier to electroplate or the mode of vapour deposition forms code-pattern flush type conductive material layer earlier, again via little shadow and etch process so that its patterning.Vapour deposition process comprises chemical vapour deposition technique or physical vaporous deposition such as sputter, evaporation.
Then, please continue, on substrate 100, form dielectric layer 104 with reference to Figure 1A.Dielectric layer 104 has opening 112, exposes buried type conducting layer 102.
The material of dielectric layer 104 for example is that polymer such as polyethylene phenol (PVP), silica, tetraethyl silica alkane (TEOS) silica, non-impurity-doped silex glass, phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), fluorine doped silicon glass (FSG), spin-on glasses (SOG), silicon nitride, dielectric constant are lower than dielectric layer of 4 etc.The formation method of dielectric layer 104 can be identical or different with buried type conducting layer 102.The formation method of dielectric layer 104 for example is to adopt the technology of ink jet printing directly to form the dielectric layer 104 with opening 112.The formation method of dielectric layer 104 also can adopt chemical vapour deposition technique or spin coating technique to form the code-pattern dielectric materials layer earlier, again via little shadow, etch process patterning, has the dielectric layer 104 of opening 112 with formation.
Afterwards, please refer to Figure 1B, on the dielectric layer 104 of opening 112 both sides, form source/drain 106 respectively.The material of source/drain 106 can be identical or different with buried type conducting layer 102.The material of source/drain 106 for example is aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.The formation method of source/drain 106 can be identical or different with buried type conducting layer 102 or dielectric layer.The formation method of source/drain 106 can adopt ink-jet printing technology directly to form.The formation method of source/drain 106 also can be earlier to electroplate or the mode of vapour deposition forms the code-pattern conductive material layer earlier, again via little shadow and etch process so that its patterning.Vapour deposition process comprises chemical vapour deposition technique or physical vaporous deposition such as sputter, evaporation.
, please refer to Fig. 1 C, between two source/drains 106, form dielectric substrate 108, to electrically connect buried type conducting layer 102 and two source/drains 106 thereafter.The material of dielectric substrate 108 for example is a solid electrolyte.Solid electrolyte for example is Germanium selenide (GeSe), germanium sulfide (GeS), AgTeSe, AgTeS or the AgSeS of silver-doped, copper, chromium or niobium.Solid electrolyte also can be an organic material.Organic material can see through electrochemical mode, by the change of redox state, to change its conductivity.Organic material is a kind of polymer, and it has conductivity in the state of oxidation at least.Organic material also optionally also comprises polyanionic compound (polyanion compound).In one embodiment, this polymeric material is to be selected from polythiophene (polythiophenes), polypyrrole (polypyrroles), polyaniline (polyanilines), poly-different azoles naphthalene (polyisothianaphtalenes), polyphenylene vinylene (polyphenylene vinylenes) and copolymer thereof.In one embodiment, polymeric material is 3, and the 4-dialkoxythiophene (3, polymer 4-dialkoxythiophene) or copolymer.3, two alkoxyls in the 4-dialkoxythiophene can be identical or different, or constitute oxygen-alkylidene-oxo bridge (oxy-alkylene-oxy bridge) that selectivity replaces jointly.In one embodiment, 3, the 4-dialkoxythiophene is selected from poly-(3,4-methylene dioxy thiophene) (poly (3,4-methylenedioxythiophene)), poly-(3,4-ethylidene dioxy thiophene) (poly (3,4-ethylenedioxythiophene), poly-(3,4-propylidene dioxy thiophene) (poly (3,4-propylenedioxythiophene)) and poly-(3,4-butylidene dioxy thiophene) (poly (3,4-butylenedioxythiophene)).Polyanionic compound is poly-(styrene sulfonic acid) (poly (styrene sulphonic acid)) or its esters.
Solid electrolyte also comprises adhesive (binder).Adhesive has colloid property.Adhesive is selected from gelatin (gelatine), gelatine derivative (gelatine derivative), polyacrylic acid (polyacrylic acid), polymethylacrylic acid (polymethacrylic acid), polyvinylpyrrolidone (poly (vinyl-pyrrolidone), polysaccharide (polysaccharides), polyacrylamide (polyacrylamides), polyurethanes (polyurethanes), PPOX (polypropyleneoxides), poly(ethylene oxide) (polyethylene oxides), poly-(styrene sulfonic acid) (poly (styrenesulphonic acid)) and polyvinyl alcohol (poly (vinyl alcohol)) and its esters and its copolymer, and they optionally are crosslinked.Solid electrolyte can also comprise ion salt.In addition, solid electrolyte can comprise also that hygroscopic salt (hygroscopic salt) for example is a magnesium chloride, to keep its contained moisture.The formation method of dielectric substrate 108 can be identical or different with source/drain 106, buried type conducting layer 102 or dielectric layer 104.The formation method of dielectric substrate 108 can adopt ink-jet printing technology directly covering dielectric substrate 108 between two source/drains 106 and on two source/drains 106 of part.The formation method of dielectric substrate 108 also can utilize the mode of physical vapour deposition (PVD) such as sputter, evaporation to form the code-pattern electrolyte material layer, again via little shadow and etch process so that its patterning.
Afterwards, please refer to Fig. 1 D, on dielectric substrate 108, form grid structure 116.Grid structure 116 comprises gate dielectric 110 and grid 114.The material of gate dielectric 110 for example is silica, silicon nitride, silicon oxynitride or other high dielectric constant material.The formation method of gate dielectric 110 can be identical or different with source/drain 106, buried type conducting layer 102 or dielectric layer.The method that gate dielectric 110 forms for example is ink-jet printing technology, spin coating technique, thermal oxidation method or chemical vapour deposition technique.The material of grid 114 can be identical or different with source/drain 106, buried type conducting layer 102.The material of grid 114 for example is aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.The formation method of grid 114 can be identical or different with gate dielectric 110, source/drain 106, buried type conducting layer 102 or dielectric layer.The formation method of grid 114 can adopt ink-jet printing technology directly to form.The formation method of grid 114 also can be earlier to electroplate or the mode of vapour deposition forms the code-pattern conductive material layer earlier, again via little shadow and etch process so that its patterning.Vapour deposition process comprises chemical vapour deposition technique or physical vaporous deposition such as sputter, evaporation.
In one embodiment, grid 114, gate dielectric 110 all adopt identical ink-jet printing technology to form.Because its technology can need not carried out little shadow and etch process fully, therefore, its technology is easy, quick.
In embodiments of the present invention, the dielectric substrate 108 between two source/drains 106 can be used as raceway groove 120, and dielectric substrate 108 changes its conductivity by redox reaction, to open or to close raceway groove 120.In one embodiment, this element belongs to vague and general type (depletion mode) transistor, and when not applying bias voltage to grid 114, dielectric substrate 108 is for having the oxidation state of high conductivity; When the grid 114 at this assembly applied malleation, the dielectric substrate 108 of grid 114 belows was reduced into the ortho states of going back with low electric conductivity.In other words, give grid 114 not applying bias voltage, and buried type conducting layer 102 ground connection or float and two source/drains 106 between when pressure reduction is arranged, the current lead-through of the channel region between the source/drain 106.And applying malleation to grid 114, buried type conducting layer 102 ground connection, source electrode 106 ground connection, and drain 106 when connecing positive voltage, electronics is offered the dielectric substrate 108 of grid 114 belows by the ground connection or the buried type conducting layer 102 of floating, make it that reduction reaction take place and become to have the ortho states of going back of low electric conductivity, and cause raceway groove to be closed.Because the electronics source of supply under channel, therefore, can effectively shorten electron displacement length (electron migrate length).On the other hand, because buried type conducting layer 102 can be connected with transistorized source electrode 106, make element when operation, grid 114 and buried type conducting layer 102 produce potential difference naturally, and then cause electric charge to carry out inside in electrolyte and transmit (internaltransfer).Therefore, the present invention can be by the shortening of electron displacement length and is produced potential difference naturally and significantly promote transistorized reaction speed.
In the embodiment of the present invention, buried type conducting layer can be connected with transistorized source electrode, makes element when operation, and grid and buried type conducting layer produce potential difference naturally, therefore, when operating, do not need to provide in addition negative supply to grid.
On the other hand, because the electrolytic transistor of embodiment of the present invention is rectilinear structure, electric charge can in time be supplied to the electrolyte in the channel region between two source/drains, makes electrolyte can carry out redox reaction rapidly, therefore, transistorized reaction speed is very fast.
The electrolytic transistor of embodiment of the present invention can be a kind of applying under the situation of bias voltage, redox state in the electrolyte just can change, and after removing bias voltage, therefore the element that mobile electron in the electrolyte and moving iron can come back to initial conditions can be applicable on dynamic electrolytic matter transistor (dynamic electrolyte transistor) or the bifurcation electrolytic transistor (bi-stableelectrolyte transistor).
The electrolytic transistor of embodiment of the present invention, it can use flexible base plate to make, and manufacture method is simple and easy, can make in a large number.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; Ying Kezuo changes arbitrarily and retouches, so protection scope of the present invention should be as the criterion with the claims restricted portion.
Claims (37)
1. electrolytic transistor comprises:
Grid structure, it comprises gate dielectric and grid, is positioned at the substrate top;
Two source/drains, it is separated from one another, is positioned at this substrate top of these grid structure both sides;
Dielectric substrate, between this two source/drain and be in contact with it, and between this grid structure and this substrate;
Buried type conducting layer, its between this dielectric substrate and this substrate, and
Dielectric layer is positioned at around this buried type conducting layer, and is covered on this buried type conducting layer and has opening, expose portion buried type conducting layer, and isolated this buried type conducting layer and two source/drains;
Wherein, this dielectric substrate is formed on the opening of dielectric layer and with buried type conducting layer and electrically connects, this dielectric substrate between this two source/drain comprises raceway groove, and the redox reaction by this dielectric substrate changes its conductivity, to open or to close this raceway groove.
2. electrolytic transistor as claimed in claim 1, wherein the material of this dielectric substrate comprises solid electrolyte.
3. electrolytic transistor as claimed in claim 2, wherein this solid electrolyte comprises Germanium selenide, germanium sulfide, AgTeSe, AgTeS, AgSeS or the organic material of silver-doped, copper, chromium or niobium.
4. electrolytic transistor as claimed in claim 3, wherein organic material is a kind of polymeric material.
5. electrolytic transistor as claimed in claim 4, wherein this polymeric material is selected from polythiophene, polypyrrole, polyaniline, poly-different azoles naphthalene, polyphenylene vinylene and copolymer thereof.
6. electrolytic transistor as claimed in claim 4, wherein this polymeric material is 3, the polymer of 4-dialkoxythiophene.
7. electrolytic transistor as claimed in claim 4, wherein this polymeric material is 3, the copolymer of 4-dialkoxythiophene.
8. as claim 6 or 7 described electrolytic transistors, wherein this 3, the polymer of 4-dialkoxythiophene or copolymer are selected from poly-(3,4-methylene dioxy thiophene), poly-(3,4-ethylidene dioxy thiophene), poly-(3,4-propylidene dioxy thiophene) and poly-(3,4-butylidene dioxy thiophene).
9. electrolytic transistor as claimed in claim 3, wherein this organic material also comprises anionic compound.
10. electrolytic transistor as claimed in claim 9, wherein this anionic compound comprises poly-(styrene sulfonic acid) or its esters.
11. electrolytic transistor as claimed in claim 3, wherein this organic material also comprises adhesive.
12. electrolytic transistor as claimed in claim 11, wherein this adhesive is selected from gelatin, gelatine derivative, polyacrylic acid, polymethylacrylic acid, polyvinylpyrrolidone, polysaccharide, polyacrylamide, polyurethanes, PPOX, poly(ethylene oxide), poly-(styrene sulfonic acid) and polyvinyl alcohol and its esters and its copolymer.
13. electrolytic transistor as claimed in claim 2, wherein this solid electrolyte also comprises ion salt.
14. electrolytic transistor as claimed in claim 2, wherein this dielectric layer is also isolated this two source/drain and this substrate.
15. electrolytic transistor as claimed in claim 1, wherein this dielectric layer is also isolated this two source/drain and this substrate.
16. electrolytic transistor as claimed in claim 1, wherein the material of this two source/drain comprises aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.
17. electrolytic transistor as claimed in claim 1, wherein the material of this grid comprises aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.
18. electrolytic transistor as claimed in claim 1, wherein the material of this buried type conducting layer comprises aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.
19. electrolytic transistor as claimed in claim 1 is vague and general transistor npn npn.
20. the manufacture method of an electrolytic transistor comprises:
On substrate, form buried type conducting layer;
Form dielectric layer on this substrate, this dielectric layer has opening, exposes this buried type conducting layer;
On this dielectric layer of these opening both sides, form source/drain respectively;
Between this two source/drain, form dielectric substrate; And
On this dielectric substrate, form gate dielectric and grid, to constitute grid structure.
21. the manufacture method of electrolytic transistor as claimed in claim 20, wherein this dielectric layer, this two source/drain, this dielectric substrate, this grid structure and this buried type conducting layer are to form with identical technical method.
22. the manufacture method of electrolytic transistor as claimed in claim 21, wherein this dielectric layer, this two source/drain, this dielectric substrate, this grid structure and this buried type conducting layer are to form with the technology of ink jet printing.
23. the manufacture method of electrolytic transistor as claimed in claim 20, wherein the material of this dielectric substrate comprises solid electrolyte.
24. the manufacture method of electrolytic transistor as claimed in claim 23, wherein this solid electrolyte comprises Germanium selenide, germanium sulfide, AgTeSe, AgTeS or the AgSeS of silver-doped, copper, chromium or niobium, or can have the organic material of conductivity with electrochemical means by the change of its redox state.
25. the manufacture method of electrolytic transistor as claimed in claim 24, wherein organic material is a kind of polymeric material.
26. the manufacture method of electrolytic transistor as claimed in claim 25, wherein this polymeric material is selected from polythiophene, polypyrrole, polyaniline, poly-different azoles naphthalene, polyphenylene vinylene and copolymer thereof.
27. the manufacture method of electrolytic transistor as claimed in claim 25, wherein this polymeric material is 3, the polymer of 4-dialkoxythiophene.
28. the manufacture method of electrolytic transistor as claimed in claim 25, wherein this polymeric material is 3, the copolymer of 4-dialkoxythiophene.
29. manufacture method as claim 27 or 28 described electrolytic transistors, wherein this 3, the polymer of 4-dialkoxythiophene or copolymer are selected from poly-(3,4-methylene dioxy thiophene), poly-(3,4-ethylidene dioxy thiophene), poly-(3,4-propylidene dioxy thiophene) and poly-(3,4-butylidene dioxy thiophene).
30. the manufacture method of electrolytic transistor as claimed in claim 24, wherein this organic material also comprises anionic compound.
31. the manufacture method of electrolytic transistor as claimed in claim 30, wherein this anionic compound comprises poly-(styrene sulfonic acid) or its esters.
32. the manufacture method of electrolytic transistor as claimed in claim 24, wherein this organic material also comprises adhesive.
33. the manufacture method of electrolytic transistor as claimed in claim 32, wherein this adhesive is selected from gelatin, gelatine derivative, polyacrylic acid, polymethylacrylic acid, polyvinylpyrrolidone, polysaccharide, polyacrylamide, polyurethanes, PPOX, poly(ethylene oxide), poly-(styrene sulfonic acid) and polyvinyl alcohol and its esters and its copolymer.
34. the manufacture method of electrolytic transistor as claimed in claim 23, wherein this solid electrolyte also comprises ion salt.
35. the manufacture method of electrolytic transistor as claimed in claim 20, wherein the material of this two source/drain comprises aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.
36. the manufacture method of electrolytic transistor as claimed in claim 20, wherein the material of this grid comprises aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.
37. the manufacture method of electrolytic transistor as claimed in claim 20, wherein the material of this buried type conducting layer comprises aluminium, silver, gold, platinum, copper, albronze, tungsten, nickel, titanium nitride, tantalum nitride, molybdenum nitride or its combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810214451XA CN101459195B (en) | 2007-12-10 | 2008-08-26 | Electrolytic transistor and manufacturing process thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710197183.0 | 2007-12-10 | ||
| CN200710197183 | 2007-12-10 | ||
| CN200810214451XA CN101459195B (en) | 2007-12-10 | 2008-08-26 | Electrolytic transistor and manufacturing process thereof |
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| CN101459195A CN101459195A (en) | 2009-06-17 |
| CN101459195B true CN101459195B (en) | 2011-05-18 |
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| CN102893403B (en) | 2010-05-21 | 2016-08-03 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
| CN111048664A (en) * | 2019-12-07 | 2020-04-21 | 福州大学 | Organic electrochemical transistor with vertical structure and preparation method thereof |
| CN115394186A (en) * | 2022-05-31 | 2022-11-25 | 四川京龙光电科技有限公司 | High-density ultrathin flexible display device, display device and preparation method of display device |
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