KR20160112030A - Thin-film transistor having dual gate electrode - Google Patents
Thin-film transistor having dual gate electrode Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13069—Thin film transistor [TFT]
Abstract
The present invention relates to a dual gate thin film transistor, and more particularly, to a dual gate thin film transistor having a substrate; A bottom gate electrode located on the substrate; A gate insulating layer disposed over the entire surface of the substrate including the bottom gate electrode; Source / drain electrodes spaced apart from each other on the gate insulating layer; A semiconductor layer disposed over the entire surface of the gate insulating layer including the source / drain electrodes; An ion layer located on the front surface of the semiconductor layer; And a top gate electrode positioned on the ionic layer.
Description
The present invention relates to a dual gate thin film transistor, and more particularly, to a dual gate thin film transistor including an ion gel as an insulating film.
Thin film transistors (TFTs) capable of a low-temperature solution process can be applied to various flexible electronic devices implemented on a polymer substrate such as driving elements of a next generation flexible display or logic circuits of an ultra low-cost RFID (Radio Frequency Identification) Recently, active research has been conducted due to the possibility.
In recent years, interest in flexible electronic circuits and devices has been explosively increasing as various wearable devices have appeared on the market. Manufacture of electronic devices and displays through a printing process, such as printing newspapers on flexible substrates, dramatically reduces manufacturing costs . Semiconductor and insulator materials used in solution process TFTs are typically organic semiconductor inks, metal oxide inks, and nanomaterial-based semiconductor inks such as CNT and QD. Since they can be processed in solution, they can be manufactured inexpensively through various printing processes and applied to roll-to-roll process in the future, which enables mass production at low cost and high processing speed, , Which is a commercial advantage.
However, the transistor manufactured through such a printing process has a lower performance in terms of charge mobility and a uniformity among the devices compared to a silicon transistor manufactured by a vacuum process. In particular, organic thin film transistors based on organic semiconductors have low theoretical mobility of 100 cm 2 / Vs due to the characteristics of organic materials and are not applicable to devices requiring high performance at a current level of 10 cm 2 / Vs. In addition, the oxide-based transistor (eg IGZO) has only a mobility of 10-30 cm2 / Vs, which requires improvement.
On the other hand, in a transistor, physical properties required for a gate insulating film are high dielectric constant and high dielectric constant. The gate insulating film must exist between the semiconductor layer and the gate electrode in the transistor so as to have a high insulating property to prevent the current of the gate electrode from flowing directly to the semiconductor layer. The current flowing from the gate electrode to the semiconductor layer through the insulating film is referred to as a gate leakage current. The greater the gate leakage current, the higher the power consumption of the manufactured electronic circuit and the higher the likelihood that the circuit will not function as a function.
A high dielectric constant is required so that a relatively large amount of current is induced in the semiconductor layer with respect to the voltage applied at the gate electrode. In particular, the organic insulating film has relatively more flexible characteristics than the inorganic insulating film, and has recently been actively studied because it has properties favorable to the implementation of the next generation flexible display and electronic circuit.
However, the organic insulating film made of a polymer has a relatively low dielectric constant, which results in a relatively low capacitance to limit the driving voltage of the transistor to a relatively low level. One way to increase the capacitance is to use a thin insulating film. However, in the case of a polymer, it has a large amount of air voids and pinholes in the thin film and the density is low, so it is not easy to obtain the desired insulating property with a thin thickness .
Therefore, in order to effectively lower the driving voltage of a transistor to be applied to a display or an electronic device, a lot of research and development on a material and process technology for a flexible organic insulating film having a high dielectric constant and a high insulating property are required.
Recently, an ion-gel insulating film containing a variety of ionic and polymeric insulators and imparting the characteristics of a gate insulating film through ionic dipoles through the transfer of ions has been known to have a very high dielectric constant and a capacitance, There have been numerous reports of effective lowering. Conventional polymer insulating membranes have a storage capacity of 1 to 100 nF / cm 2 , while ion gel insulating membranes have a capacity of 1 to 100 μF / cm 2 , usually 100 times or more High charges can be induced at the same gate voltage.
However, such an ion-gel insulating film can effectively lower the driving voltage, but the electric double layer is formed through the movement of the ions, and the charge is induced through the ionic layer, so that the driving speed is very low, .
On the other hand, a dual gate transistor refers to a transistor in which two gate electrodes of a top gate and a bottom gate in one element are located above and below a semiconductor layer and two insulator layers. In this dual gate transistor, a structure is proposed in which a conductive electrode and an insulating film are provided for the top gate and the gate insulating film, respectively, and a semiconductor insulating film is provided for the bottom gate and the gate insulating film, and a conductive electrode and a conventional polymer insulating film or oxide insulating film.
When an ion-gel insulating film is applied to such a dual-gate transistor, that is, when an ion-gel insulating film is formed and a gate voltage is applied, ions are moved by a gate voltage instead of forming a dipole to form an electrical double layer, The transistor using the ionic gel as an insulating film has a very low charge transfer rate. Disadvantages of such an ion gel are that ions are relatively slow in moving relative to the dipole, so that the corresponding speed of the ion for fast switching is slow and the driving speed of the transistor is very slow.
Accordingly, there has been a demand for development of a dual gate transistor capable of achieving a high capacitive capacitance and a high driving speed.
In order to overcome the above problems, an object of the present invention is to provide a dual gate transistor capable of obtaining a high capacitance and a high driving speed.
Another object of the present invention is to provide a dual gate transistor capable of stable transistor driving with easy voltage correction.
According to an aspect of the present invention, A bottom gate electrode located on the substrate; A gate insulating layer disposed over the entire surface of the substrate including the bottom gate electrode; Source / drain electrodes spaced apart from each other on the gate insulating layer; A semiconductor layer disposed over the entire surface of the gate insulating layer including the source / drain electrodes; An ion layer located on the front surface of the semiconductor layer; And a top gate electrode positioned on the ionic layer.
The present invention also provides a semiconductor device, A bottom gate electrode located on the substrate; An ion layer disposed over the entire surface of the substrate including the bottom gate electrode; A semiconductor layer located on the ionic layer; Source / drain electrodes spaced apart from each other so as to be included in an upper portion of the semiconductor layer; A gate insulating layer disposed over the entire surface of the semiconductor layer on the source / drain electrode; And a top gate electrode positioned on the gate insulating layer.
Also, a dual gate thin film transistor according to the present invention has a thickness (h) of 1 to 10 nm.
Also, the present invention provides a dual gate thin film transistor comprising an ionic gel or an ionic liquid.
Also, the ionic gel of the present invention is prepared by mixing an ionic liquid and a polymer, wherein the polymer is at least one selected from the group consisting of poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride-hexafluoro propylene) , P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG) and PVDF-TrFE.
The present invention also provides a dual gate thin film transistor characterized in that the mixing ratio of the ionic liquid and the polymer in the ion gel is 0.1: 9.9 to 9.9: 0.1 by weight.
The ionic liquid of the present invention is characterized by being selected from the group consisting of [EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF 6 ], and [EMIM] [OctSO 4 ] And a gate electrode formed on the gate insulating film.
In addition, the gate insulating layer of the present invention may be an organic polymer, such as polystyrene (PS), polymethylmethacrylate (PMMA), a phenolic polymer, an acrylic polymer, an imide polymer, an arylether polymer, At least one of SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3, and Ta 2 O 3 is selected from the group consisting of a polymer, a p-xylylene polymer, a vinyl alcohol polymer, 2 > O < 5 >.
Further, the present invention provides a dual gate thin film transistor in which when a voltage is applied, a high charge is formed in the semiconductor layer due to the ion layer and a high charge amount moves in the channel due to diffusion to improve the driving speed on the source / to provide.
In the case of forming the ion layer below the top gate in the dual gate transistor according to the present invention, since the ion-gel material is used as the top gate insulating film, very high charges are accumulated on the semiconductor layer and the thickness of the semiconductor layer is less than 10 nm When the thickness is thin, such a large amount of charge is diffused to the lower portion of the semiconductor layer having a relatively small charge amount, and the voltage is applied to the bottom gate electrode to move in the lower channel of the dual gate transistor. The bottom gate can obtain a high driving speed at the same time, thereby providing a transistor with remarkably improved charge mobility and driving speed. That is, a high charge amount due to the ion layer is diffused to the bottom of the semiconductor layer to drive the bottom gate.
In the case of forming the ion layer on the bottom gate in the dual gate transistor according to the present invention, since the ion gel material is applied to the bottom gate insulating layer, a high charge is accumulated in the lower part of the semiconductor layer, The voltage is applied to the upper channel of the dual gate transistor so that the bottom gate electrode and the ion layer can simultaneously obtain a high driving speed due to the high gate mobility and the top gate. .
The dual gate transistor according to the present invention is characterized in that the semiconductor thin film has a small thickness so that a high charge amount formed by the ion layer moves into another channel in the other gate to drive such a high charge amount by a gate other than the ion layer to improve the driving speed on the source / It is effective.
In addition, since the transistor according to the present invention can be calibrated by adjusting the voltage of the gate electrode with which the ion layer is in contact to prevent operation instability, stable transistor driving becomes possible.
1 schematically illustrates a process for fabricating a thin film transistor according to an embodiment of the present invention.
2 illustrates a thin film transistor structure according to an embodiment of the present invention.
FIG. 3 shows the amount of charge according to the height position when the thickness of the semiconductor layer of the transistor is set to 100 nm and 10 nm.
4 is a graph illustrating a change in voltage applied to a thin film transistor according to an embodiment of the present invention.
5 illustrates a thin film transistor structure according to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. First, it should be noted that, in the drawings, the same components or parts have the same reference numerals as much as possible. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted so as to avoid obscuring the subject matter of the present invention.
The terms " about "," substantially ", etc. used to the extent that they are used herein are intended to be taken to mean an approximation of, or approximation to, the numerical values of manufacturing and material tolerances inherent in the meanings mentioned, Accurate or absolute numbers are used to help prevent unauthorized exploitation by unauthorized intruders of the referenced disclosure.
1 schematically illustrates a process for fabricating a thin film transistor according to an embodiment of the present invention. 2 illustrates a thin film transistor structure according to an embodiment of the present invention.
Referring to FIGS. 1 and 2, a method of manufacturing a semiconductor device includes providing a substrate, forming a bottom gate electrode disposed on the substrate, forming a gate insulating layer over the entire surface of the substrate including a bottom gate electrode on the bottom gate electrode, Forming a source / drain electrode spaced apart from the gate insulating layer, forming a semiconductor layer over the entire surface of the gate insulating layer including the source / drain electrode, and forming an ion layer on the front surface of the semiconductor layer And a top gate electrode positioned on the ionic layer is formed to fabricate a thin film transistor.
The substrate may be a flexible substrate such as a transparent substrate such as glass, a silicon substrate, a plastic substrate, or a metal foil substrate. Examples of plastic substrates include, but are not limited to, polyethersulphone, polyacrylate, polyetherimide, polyethyelenen napthalate, polyethyeleneterepthalate, polyphenylene sulfide, Polyallylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propinoate, and the like can be used.
A bottom gate electrode may be formed on the substrate. The bottom gate electrode can form a gate electrode through thin film deposition or inkjet printing in a high vacuum chamber. The gate electrode may be formed of one selected from the group consisting of aluminum (Al), aluminum alloy (Al), molybdenum (Mo), molybdenum alloy, silver nanowire, gallium indium eutectic, PEDOT; PSS and the like. The bottom gate electrode can be manufactured using a printing process such as inkjet printing or spraying using the above materials as ink. Since the vacuum process can be eliminated by forming the bottom gate electrode through such a printing process, the manufacturing cost can be expected to be reduced.
A gate insulating layer including the bottom gate electrode may be formed on the bottom gate electrode.
The gate insulating layer is preferably formed of an organic polymer, but not limited thereto, and may be formed of an oxide. Examples of the organic polymer include imide polymers such as polystyrene (PS), polymethyl methacrylate (PMMA), phenol polymer, acrylic polymer and polyimide, arylether polymer, amide polymer, fluoropolymer, p It is preferable to use at least one selected from the group consisting of a polyisocyanate-based polymer, a polyisocyanate-based polymer, a zirylene-based polymer, a vinyl alcohol-based polymer, and parylene. As the oxide, it is preferable to use at least one selected from the group consisting of SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3 and Ta 2 O 5 for the gate insulating layer.
The role of the gate insulating layer is to enable electrons to form an induced dipole to accumulate charge. The gate insulating layer has a high dielectric constant, so that the driving voltage is high, but the transistor can be driven at a high driving speed. A high driving speed in transistors of electronic devices such as computers currently used is obtained by using such a gate insulating layer.
And source / drain electrodes spaced apart from each other may be formed on the gate insulating layer.
The source / drain electrode may be formed of a single layer selected from Au, Al, Ag, Mg, Ca, Yb, Cs-ITO or an alloy thereof. And may further comprise a metal layer. In addition, by using graphene, carbon nanotube (CNT), PEDOT: PSS conductive polymer silver nanowire, etc., it is possible to manufacture a more flexible device than the existing metal, A source / drain electrode can be manufactured using a printing process such as inkjet printing or spraying. Since the source / drain electrodes are formed through the printing process and the vacuum process can be eliminated, the manufacturing cost can be expected to be reduced.
A semiconductor layer may be formed over the entire surface of the gate insulating layer including the source / drain electrode on the source / drain electrode.
The semiconductor layer may be an N-type organic semiconductor, a P-type organic semiconductor, or an oxide semiconductor. The N-type organic semiconductor may be an n-type organic semiconductor, a n-type organic semiconductor, a n-type organic semiconductor, a nano- A partially fluorinated phthalocyanine-based material, a perylene tetracarboxylic diimide-based material, a perylene tetracarboxylic dianhydride-based material, a naphthalene-based material, a perylene tetracarboxylic dianhydride- A naphthalene tetracarboxylic dianhydride-based material or a naphthalene tetracarboxylic dianhydride-based material may be preferably used. Here, the acene-based material may be selected from anthracene, tetracene, pentacene, perylene, or quinoline.
The P-type organic semiconductor may be one selected from the group consisting of acene, poly-thienylenevinylene, poly-3-hexylthiophen, alpha -hexathienylene, Naphthalene, alpha-6-thiophene, alpha-4-thiophene, rubrene, polythiophene, polyparaphenylene Examples of the polymer include polyparaphenylenevinylene, polyparaphenylene, polyfluorene, polythiophenevinylene, polythiophene-heterocyclic aromatic copolymer, triarylamine triarylamine, or a derivative thereof, wherein the asenic material is any one of pentacene, perylene, tetracene, and anthracene.
As the oxide semiconductor layer, an oxide semiconductor layer can be formed using IGZO, IZO, ZnO, or the like.
The semiconductor layer can be formed into a thin film by thermal evaporation or sputtering in a vacuum chamber. In addition, the material that can be dissolved in the solvent is formed on the source / drain electrode by a method such as spin coating, spraying, inkjet, flexography, screen, dip-coating and gravure . This can form a pattern on the electrode surface and a local area of the substrate. After the formation of the semiconductor layer, heat treatment or optical exposure can be performed to improve device performance such as semiconductor crystallinity and stability.
In the present invention, the thickness (h) of the semiconductor layer is preferably 1 to 10 nm. The thickness of the semiconductor layer refers to the distance between the upper portion of the source / drain electrode and the lower portion of the ionic layer. When the thickness of the semiconductor layer is small, a high charge accumulation caused by the ionic layer diffuses to the underlying semiconductor layer with high efficiency It is possible to effectively move to the lower channel. That is, a fast driving speed can be obtained.
The thickness of the transistor channel formed in the semiconductor and insulator interface through the application of the gate voltage in the organic transistor and the oxide transistor driven in the accumulation mode is generally about 1 to 5 nm (molecular layer 2-3 layers). Advanced Materials 25 (31), 4210-4244 (2013))
Therefore, when the thickness of the semiconductor layer is within 10 nm, the channel formed on the upper part of the dual gate is mixed with the channel formed with the lower part, so that the charge formed on the upper part or the lower part can be diffused to the lower part or the upper part. This effect is doubled as the thickness of the semiconductor layer becomes thinner.
FIG. 3 shows the amount of charge according to the height position when the thickness of the semiconductor layer of the transistor is set to 100 nm and 10 nm.
3, an IGZO oxide semiconductor layer is formed as a semiconductor layer. When the semiconductor layer is 100 nm, a high charge amount due to channels formed on the upper and lower layers is not effectively transferred to the middle of the semiconductor layer, And the charge amount of the intermediate layer are greatly different from each other.
On the other hand, when the semiconductor layer is 10 nm, the charges formed on the upper and lower sides are effectively diffused to the intermediate layer, and the amount of charge of the semiconductor layer spreads evenly in the semiconductor.
Therefore, when a semiconductor layer within 10 nm is used, a high charge amount on the semiconductor layer formed by the ion gel is effectively diffused to the lower side of the semiconductor layer, and a high driving speed can be obtained by eliminating the lower gate, And can be implemented at the same time.
When a voltage is applied to the top gate electrode and the bottom gate electrode, a large amount of charge is accumulated through a high dielectric constant and a capacitance due to the ionic layer. By thinning the semiconductor layer, To the channel of the semiconductor layer.
An ion layer may be formed over the entire surface of the semiconductor layer.
At this time, the ionic layer can form a layer with an ionic liquid, and a layer can be formed by an ionic gel in which an ionic liquid and a polymer are mixed. When the ionic layer is formed of an ionic gel, a specific polymer may be appropriately mixed with the ionic liquid.
As ionic liquids, 1-Ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF 6 ], and [EMIM] [OctSO 4 ] One or more can be selected from the groups.
In the case of the ion gel, the ion gel is excellent in stretchability, which is also helpful in the production of a stretchable element in the future. The ionic liquid is mixed with an ionic liquid and a polymer. Examples of the polymer include poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride- hexafluoro propylene) -HFP), tetra-arylene poly (ethylene glycol) (Tetra-PEG), PVDF-TrFE, and the like, and any polymer that can be mixed with the ionic liquid can be used without limitation.
It is preferable that the mixing ratio of the ionic liquid and the polymer is in the range of 0.1: 9.9 to 9.9: 0.1 by weight. At this time, a solvent such as methylene chloride is required for mixing, and the mixing ratio of the ionic liquid, the polymer and the solvent is about 10:90 by weight.
A method for preparing an ionic layer as an ion gel is a method in which a solution prepared by mixing an ionic liquid and a polymer in a solvent is formed and the solution is heated on a hot plate at about 80 DEG C for about 6 hours to prepare a solvent Completely dissolved and mixed to prepare an ion gel.
When an ion layer is formed between the semiconductor layer and the top gate insulating film in the state where the bottom gate electrode and the bottom gate insulating film are formed, very high charges are accumulated in the semiconductor layer due to the application of the ion gel material to the top gate insulating film, So that the top gate electrode and the ion layer can simultaneously acquire the high driving speed due to the high gate mobility and the bottom gate.
That is, when a voltage is applied to the top gate electrode, a high charge amount is accumulated in the semiconductor layer due to the influence of the ion layer. When a voltage is applied to the bottom gate electrode, migration occurs in the channel of the transistor, .
4 is a graph illustrating a change in voltage applied to a thin film transistor according to an embodiment of the present invention.
In the present invention, a large amount of charge is formed in the semiconductor layer due to the ion layer located on the semiconductor layer, and many charges formed are easily diffused downward because the semiconductor layer is thin, and are driven by adjusting the bottom gate electrode.
When the thickness of the semiconductor layer is as thin as 10 nm or less, a high charge accumulation caused by the ion layer can be efficiently diffused to the underlying semiconductor layer to effectively move to the bottom channel, thereby achieving a fast driving speed.
Referring to FIG. 4, charges are accumulated on the ion layer due to + voltage application of the top gate electrode, and charges are accumulated and diffused downward due to the thin semiconductor layer, .
A top gate electrode can be formed on the ionic layer. The top gate electrode may be formed in the same manner as the formation of the bottom gate electrode. Alternatively, the bottom gate electrode may be formed of aluminum (Al), aluminum alloy (Al), molybdenum (Mo), molybdenum alloy A silver nanowire, gallium indium eutectic, PEDOT, PSS, or the like.
Thus, a thin film transistor according to an embodiment of the present invention can be completed.
5 illustrates a thin film transistor structure according to another embodiment of the present invention.
Referring to FIG. 5, an ion layer can be formed on the bottom gate electrode. A bottom gate electrode located on the substrate; An ion layer disposed over the entire surface of the substrate including the bottom gate electrode; A semiconductor layer located on the ionic layer; Source / drain electrodes spaced apart from each other so as to be included in an upper portion of the semiconductor layer; A gate insulating layer disposed over the entire surface of the semiconductor layer on the source / drain electrode; And a top gate electrode positioned on the gate insulating layer. The dual gate thin film transistor can be provided.
In this case, the respective structures are the same as those described above, so a detailed description thereof will be omitted. It is preferable that the thickness h of the semiconductor layer is 1 to 10 nm. The thickness of the semiconductor layer can be regarded as the distance between the lower portion of the source / drain electrode and the upper portion of the ion layer.
Hereinafter, specific embodiments of the present invention will be described in detail.
Example 1
Substrate preparation and gate insulation layer formation
In manufacturing a thin film transistor, a glass substrate is prepared, and a gate insulating layer is formed on the substrate. The insulating layer is dissolved in n-butyl acetate using polystyrene (PS) To form a gate insulating layer.
Source / drain electrode and semiconductor layer formation
Source / drain electrodes were formed on the gate insulating layer, and then P3HT was used to form a semiconductor layer. The thickness h of the semiconductor layer was 10 nm.
Ion layer formation
The polymer was mixed with methylene chloride solvent using PVDF-TrFE as an ionic liquid, and the ionic liquid: polymer: [1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) And the solvent was mixed at a weight ratio of 0.7: 9.3: 90 to prepare a solution. The solution was heated on a hot plate at 80 DEG C for 6 hours to completely dissolve and mix the material in a solvent to prepare an ion gel, which was used to form an ion layer.
Top gate electrode formation
A thin film transistor was fabricated by depositing aluminum (Al) to form a top gate electrode in a part of the upper part of the ionic layer.
Comparative Example One
The procedure of Example 1 was repeated,
The gate insulating layer was not applied and a layer was formed of the same material as that used for the ion layer in the gate insulating layer.
Comparative Example 2
The procedure of Example 1 was repeated,
A layer was formed of the same material as that used for the gate insulating layer in the ion layer without applying the ionic layer.
As a result of the experiment, in Example 1, a very high charge is accumulated in the semiconductor layer and the voltage is applied to the bottom gate electrode to move in the channel of the transistor. Therefore, due to the top gate electrode and the ion layer, A high driving speed can be obtained at the same time.
On the other hand, Comparative Example 1 exhibits high charge mobility, but the performance of the driving speed is considerably slow. In the case of Comparative Example 2, the driving speed is high but the charge amount is not high.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. It will be clear to those who have knowledge of.
Claims (9)
A bottom gate electrode located on the substrate;
A gate insulating layer disposed over the entire surface of the substrate including the bottom gate electrode;
Source / drain electrodes spaced apart from each other on the gate insulating layer;
A semiconductor layer disposed over the entire surface of the gate insulating layer including the source / drain electrodes;
An ion layer located on the front surface of the semiconductor layer; And
And a top gate electrode positioned on the ionic layer.
A bottom gate electrode located on the substrate;
An ion layer disposed over the entire surface of the substrate including the bottom gate electrode;
A semiconductor layer located on the ionic layer;
Source / drain electrodes spaced apart from each other so as to be included in an upper portion of the semiconductor layer;
A gate insulating layer disposed over the entire surface of the semiconductor layer on the source / drain electrode; And
And a top gate electrode positioned on the gate insulating layer.
Wherein the semiconductor layer has a thickness (h) of 1 to 10 nm.
Wherein the ionic layer comprises an ionic gel or an ionic liquid.
The ionic gel is prepared by mixing an ionic liquid and a polymer,
The polymer may be selected from the group consisting of poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride- hexafluoropropylene), P (VDF-HFP), tetra- PEG), and PVDF-TrFE.
Wherein the mixing ratio of the ionic liquid and the polymer is 0.1: 9.9 to 9.9: 0.1 weight ratio.
The ionic liquid is a dual-gate, characterized in that the at least one selected from the group consisting of [EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF 6], and [EMIM] [OctSO 4] Thin film transistor.
The gate insulating layer may be an organic polymer, such as polystyrene (PS), polymethylmethacrylate (PMMA), a phenolic polymer, an acrylic polymer, an imide polymer, an arylether polymer, an amide polymer, At least one member selected from the group consisting of a zirylene-based polymer, a vinyl alcohol-based polymer, and parylene,
Wherein at least one oxide is selected from the group consisting of SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3 and Ta 2 O 5 .
Wherein a high charge is formed in the semiconductor layer due to the ion layer when a voltage is applied, and a high charge amount moves in the channel due to diffusion to improve the driving speed on the source / drain electrode.
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| PCT/KR2016/002509 WO2016148460A1 (en) | 2015-03-17 | 2016-03-14 | Dual gate thin film transistor |
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| KR20180136324A (en) * | 2017-06-14 | 2018-12-24 | 광운대학교 산학협력단 | High Performance Solution-Processed Zinc-Tin-Oxide Thin-Film Transistors Employing Ferroelectric Copolymers Fabricated at Low Temperature for Transparent Flexible Displays and encapsulation process method of ZTO TFT device using fluoroploymer thin film |
| KR20200117124A (en) * | 2019-04-03 | 2020-10-14 | 재단법인대구경북과학기술원 | Transistor module comprising capacitive touch sensor, piezoelectric sensor and dual-gate transistor |
| KR20200118986A (en) * | 2019-04-09 | 2020-10-19 | 중앙대학교 산학협력단 | Electrically stable organic electrolyte-gated transistors and their fabrication method |
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| CN107393965A (en) * | 2017-07-17 | 2017-11-24 | 华南理工大学 | Planar double-gated oxide thin film transistor and preparation method thereof |
| US11189733B2 (en) | 2018-01-10 | 2021-11-30 | Intel Corporation | Thin-film transistors with low contact resistance |
| CN108847424B (en) * | 2018-04-24 | 2021-09-03 | 京东方科技集团股份有限公司 | Thin film transistor, sensor, biological detection device and method |
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| KR101088056B1 (en) * | 2010-02-05 | 2011-11-29 | 연세대학교 산학협력단 | Organic field effect transistor and method for manufacturing thereof |
| KR101489866B1 (en) * | 2012-10-05 | 2015-02-06 | 성균관대학교산학협력단 | Graphene field effect transistor with dielectrics and gate electrodes having stable behaviors despite high strains, and manufacturing method of the same |
| EP2811525B1 (en) * | 2013-03-14 | 2019-02-13 | Karlsruher Institut für Technologie | Electrochemically-gated field-effect transistor, method for its manufacture, its use, and electronics comprising said field- effect transistor |
| JP6191235B2 (en) * | 2013-05-20 | 2017-09-06 | 富士電機株式会社 | Organic transistor and manufacturing method thereof |
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| US20080191200A1 (en) | 2007-02-08 | 2008-08-14 | Regents Of The University Of Minnesota | Ion gels and electronic devices utilizing ion gels |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20180136324A (en) * | 2017-06-14 | 2018-12-24 | 광운대학교 산학협력단 | High Performance Solution-Processed Zinc-Tin-Oxide Thin-Film Transistors Employing Ferroelectric Copolymers Fabricated at Low Temperature for Transparent Flexible Displays and encapsulation process method of ZTO TFT device using fluoroploymer thin film |
| KR20200117124A (en) * | 2019-04-03 | 2020-10-14 | 재단법인대구경북과학기술원 | Transistor module comprising capacitive touch sensor, piezoelectric sensor and dual-gate transistor |
| KR20200118986A (en) * | 2019-04-09 | 2020-10-19 | 중앙대학교 산학협력단 | Electrically stable organic electrolyte-gated transistors and their fabrication method |
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