CN101459111A - Shallow groove isolation region forming method and dielectric layer forming method - Google Patents
Shallow groove isolation region forming method and dielectric layer forming method Download PDFInfo
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- CN101459111A CN101459111A CNA2007100944982A CN200710094498A CN101459111A CN 101459111 A CN101459111 A CN 101459111A CN A2007100944982 A CNA2007100944982 A CN A2007100944982A CN 200710094498 A CN200710094498 A CN 200710094498A CN 101459111 A CN101459111 A CN 101459111A
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Abstract
A method of forming a shallow trench isolation region comprises steps of forming a shallow trench on a semiconductor substrate, utilizing the deposition-etching-deposition process to deposit an isolating lamination covering on the shallow trench, executing plasma repairing operation on the semiconductor substrate after the isolating lamination is deposited, re-executing the operation of isolating lamination deposition and the follow-up operation of plasma repairing, thereby forming an isolating layer filling the shallow trench. The method of forming a shallow trench isolation region can reduce defects of an interlayer of the shallow trench region. The invention provides a method for forming a dielectric layer, which can decrease defects of an interlayer in the dielectric layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of shallow channel isolation area formation method and dielectric layer formation method.
Background technology
Along with the increase of integrated circuit integrated level, must constantly dwindle in order to the size in active region isolation district in the isolation of semiconductor devices.Be used to isolate the regional oxidizing process (LOCOS) of active area in the traditional handicraft because the oxidation at the active area edge causes the field oxide edge to have the shape of a beak (Bird ' sbeak), and make that in semiconductor device effective isolation length is restricted between the active area.Because can avoid the shortcoming of above-mentioned zone oxidizing process, shallow trench isolation is from (Shallow Trenchlsolation, STI) technology is widely used in the isolation between the active area in the semiconductor device in recent years.
For guaranteeing the filling effect of STI, use high-density plasma chemical vapor deposition (HDPCVD) technology usually and carry out the sti oxide filling with synchronous deposition-etching power.As on August 16th, 2006 disclosed publication number a kind ofly be used for improving the gap to fill the high-throughput HDP-CVD processes processing method of using related for what provide in the Chinese patent application of " CN 1819123A ", for obtaining good clearance filling capability, usually adopt the method for multistage deposition-etching phase combination to fill the gap, promptly, employing deposition-etching-deposition-etching-... (deposition-etch-deposition-etch-......-deposition-etch-d eposition, method DEP) is filled the gap to-deposition-etching-deposition.
In the practice, as shown in Figure 1, after forming described shallow trench 12 at semiconductor-based the end 10, experiencing each grade deposition-etching process all can form and have certain thickness isolation layering 20, as shown in Figure 2, the shallow groove isolation layer 30 of using the method formation of multistage deposition-etching phase combination comprises two-layer at least described isolation layering 20, and 20 orders of each described isolation layering form, answer close proximity, form even, fine and close shallow groove isolation layer 30 jointly.
Yet actual production finds that as shown in Figure 3, each 20 of described isolation layering of using the method formation of multistage deposition-etching phase combination has interlayer defect 40, and described interlayer defect 40 will influence the electric property and the reliability of device.The generation that how to reduce described interlayer defect becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The invention provides a kind of shallow channel isolation area formation method, can reduce described shallow channel isolation area intraformational bed generation of defects; The invention provides a kind of dielectric layer formation method, can reduce described dielectric layer intraformational bed generation of defects.
A kind of shallow channel isolation area formation method provided by the invention comprises:
On the described semiconductor-based end, form shallow trench;
Isolate layering with deposition-etching-depositing operation deposition, described isolation layering covers described shallow trench;
To carrying out plasma reparation operation in the semiconductor-based end that deposits after the described isolation layering;
Repeat deposition and isolate the operation and subsequent the plasma reparation operation of layering, to form the separator of filling described shallow trench.
Alternatively, described deposition-etching-depositing operation utilizes high-density plasma chemical vapor deposition technology to carry out; The reparation gas of using when alternatively, carrying out plasma reparation operation comprises hydrogen, nitrogen, oxygen or argon gas; Alternatively, the range of flow of described reparation gas is 100～500sccm; Alternatively, to operate required plasma dissociation power bracket be 1000～5000 watts in described plasma reparation; Alternatively, to operate required plasma sputter power bracket be 500～3000 watts in described plasma reparation.
A kind of dielectric layer formation method provided by the invention comprises:
The semiconductor-based end, be provided;
With deposition-etching-depositing operation metallization medium layer layering, described dielectric layer layering covers the described semiconductor-based end;
To carrying out plasma reparation operation in the semiconductor-based end that deposits after the described dielectric layer layering;
Repeat the operation and subsequent the plasma reparation operation of metallization medium layer layering, to form described dielectric layer.
Alternatively, described deposition-etching-depositing operation utilizes high-density plasma chemical vapor deposition technology to carry out; The reparation gas of using when alternatively, carrying out plasma reparation operation comprises hydrogen, nitrogen, oxygen or argon gas; Alternatively, the range of flow of described reparation gas is 100～500sccm; Alternatively, to operate required plasma dissociation power bracket be 1000～5000 watts in described plasma reparation; Alternatively, to operate required plasma sputter power bracket be 500～3000 watts in described plasma reparation.
Compared with prior art, technique scheme has the following advantages:
The shallow channel isolation area formation method that technique scheme provides is repaired step by increase plasma after each level deposition-etching operation, to remove the top layer of the part separator that forms via arbitrary grade of deposition-etching operation, isolates layering and form; Then, minimizing is formed at the accessory substance that forms after the part insulation surface experience etching operation; And then, the generation that the isolation of minimizing and follow-up formation divides the described interlayer defect of interlayer;
The optional mode of the shallow channel isolation area formation method that technique scheme provides, repair gas by selecting nitrogen or hydrogen as plasma, utilize its character that can generate volatile material, but the top layer of the part separator that forms via arbitrary grade of deposition-etching operation is removed in the applied chemistry effect with the above-mentioned accessory substance generation chemical reaction that is positioned at the part insulation surface;
The optional mode of the shallow channel isolation area formation method that technique scheme provides, repair gas by selecting oxygen or argon gas as plasma, utilize its can with the above-mentioned character that is positioned at the accessory substance generation physical sputtering of part insulation surface, but the Applied Physics reaction mechanism is removed the top layer via the part separator of arbitrary grade of deposition-etching operation formation;
The dielectric layer formation method that technique scheme provides is repaired step by increase plasma after each level deposition-etching operation, with the top layer of removal via the part dielectric layer of arbitrary grade of deposition-etching operation formation, and forms dielectric stratifying; Then, minimizing is formed at the accessory substance that forms after the experience etching operation of part dielectric layer surface; And then, the generation of described interlayer defect between the dielectric stratifying of minimizing and follow-up formation;
The optional mode of the dielectric layer formation method that technique scheme provides, repair gas by selecting nitrogen or hydrogen as plasma, utilize its character that can generate volatile material, but the top layer of the part dielectric layer that forms via arbitrary grade of deposition-etching operation is removed in the applied chemistry effect with the above-mentioned accessory substance generation chemical reaction that is positioned at part dielectric layer surface;
The optional mode of the dielectric layer formation method that technique scheme provides, repair gas by selecting oxygen or argon gas as plasma, utilize its can with the above-mentioned character that is positioned at the accessory substance generation physical sputtering on part dielectric layer surface, but the Applied Physics reaction mechanism is removed the top layer via the part dielectric layer of arbitrary grade of deposition-etching operation formation.
Description of drawings
Fig. 1 is for using the structural representation of the isolation layering of single-stage deposition-etching technics formation in the explanation prior art;
Fig. 2 is the structural representation of the multistage deposition of application-shallow groove isolation layer that etching technics forms in the explanation prior art;
Fig. 3 is for using the shallow groove isolation layer structural representation with interlayer defect that multistage deposition-etching technics forms in the explanation prior art;
Fig. 4 is the schematic flow sheet of the formation shallow channel isolation area of the explanation embodiment of the invention;
Fig. 5 is the semiconductor-based bottom structure schematic diagram of the explanation embodiment of the invention;
Fig. 6 for the explanation embodiment of the invention the formation shallow trench after semiconductor-based bottom structure schematic diagram;
Fig. 7 is the semiconductor-based bottom structure schematic diagram after the formation isolation layering in shallow trench of the explanation embodiment of the invention;
Fig. 8 is the semiconductor-based bottom structure schematic diagram after the execution plasma reparation of the explanation embodiment of the invention is operated;
Fig. 9 is the semiconductor-based bottom structure schematic diagram behind the formation separator in shallow trench of the explanation embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 4, using the step that method provided by the invention forms shallow channel isolation area comprises:
Step 401:, provide the semiconductor-based end 100 in conjunction with Fig. 4 and shown in Figure 5.
The described semiconductor-based end 100, have passivation layer or the separator that forms in turn and the Semiconductor substrate (substrate) of passivation layer for defining device active region and surface.Described Semiconductor substrate comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).
The described semiconductor-based end 100, can utilize traditional twin well process to obtain, and promptly forms via operations such as oxidation growth, ion injection and annealing to have the Semiconductor substrate of corresponding NMOS and PMOS transistor active area.Described passivation layer can utilize low-pressure chemical vapor phase deposition (LPCVD) equipment, under high temperature (about 750 degrees centigrade) condition, generates silicon nitride (Si via ammonia and dichlorosilane reaction
3N
4) obtain.Described passivation material includes but not limited to a kind of or its combination in silicon nitride, silicon oxynitride (SiON), carborundum (SiC), silicon oxide carbide (SiCO) or the carbonitride of silicium (SiCN); Described oxide layer can utilize thermal oxidation technology to obtain, and described thermal oxidation technology can use high-temperature oxydation equipment or oxidation furnace carries out.The process that forms described passivation layer comprises steps such as deposition, grinding and detection; The process that forms described oxide layer can comprise thermal oxidation and detect step, specifically can use any traditional technology, does not repeat them here.
Step 402: in conjunction with Fig. 4 and shown in Figure 6, form shallow trench 120 on the described semiconductor-based end 100, to form shallow channel isolation area behind the layer deposited isolating in described shallow trench 120, described separator comprises two-layer at least isolation layering.
The step that forms described shallow trench 120 comprises: form patterned resist layer on the semiconductor-based end, described semiconductor-based basal surface has passivation layer; With described patterned resist layer is mask, the described passivation layer of etching; With the described passivation layer after the etching is hard mask, the described semiconductor-based end of etched portions.
Perhaps, the step that forms described shallow trench 120 comprises: form patterned resist layer on the semiconductor-based end, described semiconductor-based basal surface has separator and the passivation layer that forms in turn; With described patterned resist layer is mask, the described passivation layer of etching; With the described passivation layer after the etching is hard mask, the order described separator of etching and the described semiconductor-based end of part.
The step of layer deposited isolating comprises the operation that is pre-formed pad oxide in described shallow trench 120; The operation of described formation pad oxide can utilize thermal oxidation technology or insitu moisture generate (in situsteam generation, ISSG) technology is carried out; The operation that forms described pad oxide can be repaired the lattice damage of the semiconductor-based end that causes when forming described shallow trench; Also can reduce the damage that plasma that the subsequent deposition process relates to causes described shallow trench sidewall and diapire.
In the actual production, adopt deposition-etching-depositing operation to form described separator usually, described deposition-etching-depositing operation can utilize high-density plasma chemical vapor deposition (HDP) technology to carry out.
Described deposition-etching-depositing operation is: at first, and the described separator of deposition part; Then, the established separator of etched portions (in the presents, the part separator that forms after the etching being called the isolation layering); And then sequential aggradation is isolated layering, to form separator.
Step 403: in conjunction with Fig. 4 and shown in Figure 7, isolate layering 140 with deposition-etching-depositing operation deposition, described isolation layering 140 covers described shallow trench 120.
The process conditions of the electroless copper deposition operation that relates to when forming described isolation layering 140 comprise: reacting gas comprises silane (SiH
4) and oxygen (O
2), the top flux scope of described silane is 10～1000 cc/min (sccm), as 20sccm, 30sccm, 50sccm or 70sccm; The lateral flow weight range of described silane is 50～150sccm, as 70sccm, 90sccm, 110sccm or 130sccm; The range of flow of described oxygen is 100～300sccm, as 120sccm, 150sccm, 200sccm or 250sccm; Buffer gas comprises hydrogen (H
2) and helium (He), described hydrogen and helium also can be simultaneously as sputter gases, and the range of flow of described hydrogen is 50～200sccm, as 70sccm, 90sccm, 130sccm or 150sccm; The range of flow of described helium is 100～500sccm, as 200sccm, 300sccm, 350sccm or 400sccm; Required plasma dissociation power (SRF) scope is 5000～10000 watts (W), as 6000W, 7000W, 8000W or 9000W; Required plasma sputter power (BRF) scope is 1000～5000W, as 2000W, 3000W, 3500W or 4000W.The reaction temperature that relates to can be 450～550 degrees centigrade, as 500 degrees centigrade.
The process conditions of the etching operation that relates to when forming described isolation layering 140 comprise: reacting gas comprises Nitrogen trifluoride (NF
3), the range of flow of described Nitrogen trifluoride is 100～300sccm, as 120sccm, 150sccm, 200sccm or 250sccm; Buffer gas comprises hydrogen (H
2) and helium (He), described hydrogen and helium also can be simultaneously as sputter gases, and the range of flow of described hydrogen is 50～200sccm, as 70sccm, 90sccm, 130sccm or 150sccm; The range of flow of described helium is 100～300sccm, as 120sccm, 150sccm, 170sccm or 200sccm; Required plasma dissociation top is 1000～3000 watts (W) to power (SRF top) scope, as 1200W, 1500W, 2000W or 2500W; Required plasma dissociation side direction power (SRF side) scope is 3000～10000 watts (W), as 4000W, 5000W, 6000W or 8000W; Required plasma sputter power (BRF) scope is 500～3000W, as 700W, 1000W, 1500W or 2000W.The reaction temperature that relates to can be 400～500 degrees centigrade, as 450 degrees centigrade.
Between above-mentioned electroless copper deposition operation and etching operation, also can comprise transition step, so that the reacting gas that deposition process relates to reacts completely; The process conditions that relate to comprise: transition gas comprises oxygen (O
2), the range of flow of described oxygen is 100～300sccm, as 120sccm, 150sccm, 200sccm or 250sccm; Buffer gas comprises hydrogen (H
2) and helium (He), described hydrogen and helium also can be simultaneously as sputter gases, and the range of flow of described hydrogen is 50～200sccm, as 70sccm, 90sccm, 130sccm or 150sccm; The range of flow of described helium is 100～500sccm, as 200sccm, 300sccm, 350sccm or 400sccm; Required plasma dissociation power (SRF) scope is 1000～5000 watts (W), as 2000W, 2500W, 3000W or 4000W; Required plasma sputter power (BRF) can be 0 or technology on feasible arbitrary value, as 1000～5000W, specifically can be 2000W, 3000W, 3500W or 4000W.The reaction temperature that relates to can be 450～550 degrees centigrade, as 500 degrees centigrade.
Step 404: to carrying out plasma reparation operation in the semiconductor-based end that deposits after the described isolation layering, the semiconductor-based end 102 that having of experiencing that described reparation operation back obtains isolated layering 142, as shown in Figure 8.
Actual production finds to have internal structure usually and differ from the interlayer of isolating layering between described isolation layering that forms and follow-up isolation layering, and described interlayer defect will influence the electric property and the reliability of device; The present inventor thinks after analyzing that described interlayer defect is to cause owing to the part insulation surface that forms has polymer deficiency.How to remove forming the polymer that part separator rear surface has, become the subject matter that the present invention solves.
Think after the present inventor's undergoing analysis and the practice,, become the direction of removing described polymer carrying out plasma reparation operation in the semiconductor-based end that deposits after the described isolation layering.
The process conditions that relate to comprise: repair gas and can comprise hydrogen (H
2) or nitrogen (N
2), the range of flow of described hydrogen or nitrogen is 100～500sccm, as 150sccm, 200sccm, 250sccm or 350sccm; Required plasma dissociation power (SRF) scope is 1000～5000 watts (W), as 2000W, 2500W, 3000W or 4000W; Required plasma sputter power (BRF) scope is 500～3000W, as 700W, 1000W, 1500W or 2000W.The reaction temperature that relates to can be 450～550 degrees centigrade, as 500 degrees centigrade.
The duration of described plasma reparation operation determines that according to process conditions and product requirement for 65 nanometers and following technology thereof, the duration of described plasma reparation operation can be 5～15 seconds, as 8 seconds, 10 seconds or 12 seconds.
The present inventor thinks after analyzing that described polymer deficiency is for experiencing the accessory substance that comprises the contained element of etching gas that forms after the etching operation; Usually, comprise fluorine (F) in the etching gas, cause in the described polymer and comprise fluorine, when utilizing described hydrogen or nitrogen to repair described polymer, obtain to comprise the plasma of hydrogen or nitrogen behind described hydrogen of ionization or the nitrogen, described plasma easily with described polymer in the fluorine generation chemical reaction that comprises, can reduce even eliminate described polymer deficiency then, further can reduce the generation of follow-up interlayer defect.
Described reparation gas also can comprise oxygen (O
2) or argon gas (Ar), the present inventor thinks after analyzing, oxygen or argon gas because its particle particle is bigger, can reduces even eliminate described polymer deficiency when repairing gas by the sputter effect; The process conditions that relate to comprise: the range of flow of described oxygen or argon gas is 100～500sccm, as 150sccm, 200sccm, 250sccm or 350sccm; Required plasma dissociation power (SRF) scope is 1000～5000 watts (W), as 2000W, 2500W, 3000W or 4000W; Required plasma sputter power (BRF) scope is 500～3000W, as 700W, 1000W, 1500W or 2000W.The reaction temperature that relates to can be 450～550 degrees centigrade, as 500 degrees centigrade.
The duration of described plasma reparation operation determines that according to process conditions and product requirement for 65 nanometers and following technology thereof, the duration of described plasma reparation operation can be 5～15 seconds, as 8 seconds, 10 seconds or 12 seconds.
Step 405: in conjunction with Fig. 4 and shown in Figure 9, the operation and subsequent the plasma reparation that are repeated deposition isolation layering the semiconductor-based end 102 that experiences plasma reparation operation are operated, to form the separator 160 of filling described shallow trench.
Use deposition-etching-depositing operation and deposit when comprising the separator of two-layer at least isolation layering, after forming each isolation layering, all need carry out plasma reparation operation; The concrete number of the isolation layering that described separator comprises is determined according to production requirement.
It should be noted that described deposition-etching-depositing operation is not limited to utilize high-density plasma chemical vapor deposition (HDP) technology to carry out; Deposition that relates in described deposition-etching-depositing operation and etching operation all can be used arbitrary conventional deposition and the etching technics in the existing manufacture of semiconductor, as chemical vapor deposition method and plasma etch process.
In addition, when using deposition-etching-depositing operation plated metal front medium layer or other interlayer dielectric layers, the inventive method stands good.That is, the present invention also provides a kind of dielectric layer formation method, and the step of using method formation dielectric layer provided by the invention comprises: the semiconductor-based end is provided; With deposition-etching-depositing operation metallization medium layer layering, described dielectric layer layering covers the described semiconductor-based end; To carrying out plasma reparation operation in the semiconductor-based end that deposits after the described dielectric layer layering; The operation and subsequent the plasma reparation that are repeated the metallization medium layer layering the semiconductor-based end that experiences plasma reparation operation are operated, to form described dielectric layer.
For before-metal medium layer, on the Semiconductor substrate definition device active region and finish shallow trench isolation from, then form grid structure and source region and drain region after, form the semiconductor-based end.Described before-metal medium layer covers described grid structure and source region and drain region, and fills up the linear slit that is positioned between described grid structure; Described grid structure comprises the side wall and the gate oxide of grid, all around gate.Described grid structure also can comprise the barrier layer that covers described grid and side wall.
For other interlayer dielectric layers, on the Semiconductor substrate definition device active region and finish shallow trench isolation from, then form grid structure and source region and drain region after, and then deposit first interlayer dielectric layer, after forming the 1st layer of through hole and groove subsequently, sequential aggradation second interlayer dielectric layer, second layer through hole and groove ..., behind deposition N-1 interlayer dielectric layer, after continuing to form N-1 layer through hole and groove, form the semiconductor-based end.
Obviously, number N can be any natural number, and as 1,3,5,7 or 9 etc., the concrete number of described interlayer dielectric layer is determined according to product requirement.
The process conditions that described plasma reparation operation relates to comprise: repair gas and can comprise hydrogen (H
2), nitrogen (N
2), oxygen (O
2) or argon gas (Ar), the range of flow of described reparation gas is 100～500sccm, as 150sccm, 200sccm, 250sccm or 350sccm; Required plasma dissociation power (SRF) scope is 1000～5000 watts (W), as 2000W, 2500W, 3000W or 4000W; Required plasma sputter power (BRF) scope is 500～3000W, as 700W, 1000W, 1500W or 2000W.The reaction temperature that relates to can be 450～550 degrees centigrade, as 500 degrees centigrade.
The duration of described plasma reparation operation determines that according to process conditions and product requirement for 65 nanometers and following technology thereof, the duration of described plasma reparation operation can be 5～15 seconds, as 8 seconds, 10 seconds or 12 seconds.
The present inventor thinks after analyzing, when utilizing described hydrogen or nitrogen to repair described polymer, obtain to comprise the plasma of hydrogen or nitrogen behind described hydrogen of ionization or the nitrogen, described plasma be easy to described polymer in the fluorine that comprises and nitrogen generation chemical reaction and reduce even eliminate described polymer deficiency; And utilize oxygen or argon gas when repairing gas, because its particle particle is bigger, can reduce even eliminate described polymer deficiency by the sputter effect; Further can reduce the generation of follow-up interlayer defect.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (12)
1. a shallow channel isolation area formation method is characterized in that, comprising:
On the semiconductor-based end, form shallow trench;
Isolate layering with deposition-etching-depositing operation deposition, described isolation layering covers described shallow trench;
To carrying out plasma reparation operation in the semiconductor-based end that deposits after the described isolation layering;
Repeat deposition and isolate the operation and subsequent the plasma reparation operation of layering, to form the separator of filling described shallow trench.
2. shallow channel isolation area formation method according to claim 1 is characterized in that: described deposition-etching-depositing operation utilizes high-density plasma chemical vapor deposition technology to carry out.
3. shallow channel isolation area formation method according to claim 1 and 2 is characterized in that: the reparation gas of using when carrying out plasma reparation operation comprises hydrogen, nitrogen, oxygen or argon gas.
4. shallow channel isolation area formation method according to claim 1 and 2 is characterized in that: the range of flow of described reparation gas is 100～500sccm.
5. shallow channel isolation area formation method according to claim 1 and 2 is characterized in that: it is 1000～5000 watts that required plasma dissociation power bracket is operated in described plasma reparation.
6. shallow channel isolation area formation method according to claim 1 and 2 is characterized in that: it is 500～3000 watts that required plasma sputter power bracket is operated in described plasma reparation.
7. a dielectric layer formation method is characterized in that, comprising:
The semiconductor-based end, be provided;
With deposition-etching-depositing operation metallization medium layer layering, described dielectric layer layering covers the described semiconductor-based end;
To carrying out plasma reparation operation in the semiconductor-based end that deposits after the described dielectric layer layering;
Repeat the operation and subsequent the plasma reparation operation of metallization medium layer layering, to form described dielectric layer.
8. dielectric layer formation method according to claim 7 is characterized in that: described deposition-etching-depositing operation utilizes high-density plasma chemical vapor deposition technology to carry out.
9. according to claim 7 or 8 described dielectric layer formation methods, it is characterized in that: the reparation gas of using when carrying out plasma reparation operation comprises hydrogen, nitrogen, oxygen or argon gas.
10. according to claim 7 or 8 described dielectric layer formation methods, it is characterized in that: the range of flow of described reparation gas is 100～500sccm.
11. according to claim 7 or 8 described dielectric layer formation methods, it is characterized in that: it is 1000～5000 watts that required plasma dissociation power bracket is operated in described plasma reparation.
12. according to claim 7 or 8 described dielectric layer formation methods, it is characterized in that: it is 500～3000 watts that required plasma sputter power bracket is operated in described plasma reparation.
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| KR20180010315A (en) * | 2015-06-19 | 2018-01-30 | 어플라이드 머티어리얼스, 인코포레이티드 | Methods for depositing dielectric films through a physical vapor deposition process |
| CN108064411A (en) * | 2015-06-19 | 2018-05-22 | 应用材料公司 | Via the method for dielectric film deposited by physical vapour deposition (PVD) |
| KR102513422B1 (en) | 2015-06-19 | 2023-03-22 | 어플라이드 머티어리얼스, 인코포레이티드 | Methods for Depositing Dielectric Films Via a Physical Vapor Deposition Process |
| CN110265353A (en) * | 2019-06-28 | 2019-09-20 | 芯盟科技有限公司 | Groove isolation construction and forming method thereof |
| CN110265353B (en) * | 2019-06-28 | 2021-06-04 | 芯盟科技有限公司 | Trench isolation structure and forming method thereof |
| CN113035769A (en) * | 2021-02-25 | 2021-06-25 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN113025991A (en) * | 2021-02-26 | 2021-06-25 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| US11942320B2 (en) | 2021-02-26 | 2024-03-26 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure |
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