CN101441611A - Isolating circuit - Google Patents
Isolating circuit Download PDFInfo
- Publication number
- CN101441611A CN101441611A CNA2007101934367A CN200710193436A CN101441611A CN 101441611 A CN101441611 A CN 101441611A CN A2007101934367 A CNA2007101934367 A CN A2007101934367A CN 200710193436 A CN200710193436 A CN 200710193436A CN 101441611 A CN101441611 A CN 101441611A
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- circuit
- buffer circuit
- signal
- buffer
- main circuit
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Abstract
The invention discloses an isolating circuit. The isolating circuit is coupled between a main circuit and a secondary circuit and is used for isolating or conducting an inner integrated circuit signal. When the electric property of the main circuit is electrified and the electric property of the secondary circuit is unelectrified, the isolating circuit isolates the main circuit from transmitting the inner integrated circuit signal to the secondary circuit; and when the electric properties of the main circuit and the secondary circuit are electrified, the isolating circuit conducts the main circuit to transmit the inner integrated circuit signal to the driven circuit. The isolating circuit solves the problem of signal isolation between the main circuit and the secondary circuit and can strengthen the operating stability of an inner integrated circuit bus.
Description
Technical field
The invention relates to a kind of buffer circuit, and particularly in the framework about a kind of principal and subordinate's circuit, be used for main circuit and from the buffer circuit between the circuit.
Background technology
About in the architecture design of principal and subordinate's circuit, main circuit and from the internal integration circuit between the circuit (InterIntegrated Circuit, I2C) signal on draw voltage the running classification on different.Please refer to Fig. 1.Fig. 1 illustrates main circuit and transmits the I2C signal to the circuit diagram from circuit.Be to receive standby to be used as and to draw voltage on the main circuit 10 with operating voltage P3V3_STBY, and be to receive running voltage P3V3 and P5V to be used as and to draw voltage from circuit 20, wherein level shifter 30 is being arranged from circuit 20, this level shifter 30 is that the voltage of signals level is changed, and level shifter 30 receives running voltage P3V3 and operates.
When at holding state, just not when normal operation, have only main circuit 10 that supply electric power is arranged, then do not supply from circuit 20.Therefore, when holding state, running voltage P3V3 and P5V do not supply electric power and give from circuit 20, have only the electric power of standby with running voltage P3V3_STBY supply main circuit 10.When holding state; from the P3V3 of circuit 20 and P5V for there not being electric power; promptly from circuit 20 electrically for the main circuit 10 that do not power on electrically for powering on; the I2C serial data signal I2C_SDA of main circuit 10 and the voltage level of I2C serial clock signal I2C_SCL may be dragged down from circuit 20, and cause principal and subordinate's circuit running undesired or cause system's instability.
Summary of the invention
The purpose of this invention is to provide a kind of buffer circuit, solve main circuit and, can strengthen the running stability of internal integration bus of circuit (I2C bus) from the isolating problem of the internal integration circuit signal between the circuit.
The present invention provides a kind of buffer circuit in addition, can make signal be isolated or be switched on, and can avoid this voltage of signals level by drop-down when buffer circuit is isolated a signal.
The present invention proposes a kind of buffer circuit, is coupled to main circuit and between the circuit, is used for described main circuit and described from isolating between the circuit or conducting internal integration circuit signal.When described main circuit electrically for power on described from circuit electrically when not powering on, described buffer circuit is isolated described internal integration circuit signal and is sent to described from circuit; When described main circuit and described from circuit electrically when powering on, the described internal integration circuit signal of described buffer circuit conducting is sent to described from circuit.
Above-mentioned buffer circuit, in one embodiment, described main circuit is a mainboard, described is backboard from circuit.
Above-mentioned buffer circuit, in one embodiment, described buffer circuit is the metal-oxide semiconductor switch.
Above-mentioned buffer circuit, in one embodiment, described main circuit be electrically coupled to the first running voltage, described buffer circuit second operates voltage with described from being electrically coupled to of circuit.
From another viewpoint, the present invention proposes a kind of buffer circuit in addition, is coupled to the signal output part of main circuit, is used to isolate or the transmission signal of the described main circuit of conducting.When described main circuit electrically for powering on, and described buffer circuit is electrical when not powering on, described buffer circuit makes signal be avoided the voltage of signals level by drop-down by isolation; When described main circuit and described buffer circuit electrically when powering on, described buffer circuit is switched on signal and sends out.
According to the described buffer circuit of embodiments of the invention, because of adopt buffer circuit be coupled to main circuit with between the circuit, when signal that buffer circuit isolation main circuit is exported, can avoid this voltage of signals level by drop-down.Therefore, buffer circuit can solve main circuit and from the isolating problem of the internal integration circuit signal between the circuit, also can strengthen the running stability of internal integration bus of circuit (I2C Bus).
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiments of the invention cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is that traditional main circuit transmits the I2C signal to the circuit diagram from circuit.
Fig. 2 is the circuit diagram of buffer circuit according to an embodiment of the invention, and this buffer circuit is coupled to main circuit and between the circuit.
Embodiment
At internal integration circuit that main circuit sent (Inter Integrated Circuit, I2C) signal is by drop-down problem, the present invention isolates the I2C signal at main circuit and from utilization buffer circuit between the circuit.Please refer to Fig. 2, Fig. 2 is the circuit diagram of buffer circuit according to an embodiment of the invention.This buffer circuit 40 is coupled to main circuit 10 and between the circuit 20.Because when holding state, from the P3V3 of circuit 20 and P5V for there not being electric power, promptly from circuit 20 electrically for the main circuit 10 that do not power on electrically for powering on, must avoid therefore understanding that the I2C serial data signal I2C_SDA of main circuit 10 and the voltage level of I2C serial clock signal I2C_SCL are dragged down from circuit 20.Wherein, standby is different running voltage with running voltage P3V3_STBY with running voltage P3V3 and P5V with the electric power that operates voltage P3V3_STBY supply main circuit 10, standby.This buffer circuit 40 can be designed to itself electrically when not powering on, and has to intercept main circuit 10 and transmit the I2C signals to the function from circuit 20, and when buffer circuit 40 powers on, and has conducting main circuit 10 and transmits the I2C signals extremely from the function of circuit 20.Running is undesired thereby buffer circuit 40 can be avoided principal and subordinate's circuit, also avoids system's instability.
In another embodiment, buffer circuit 40 is designed to have the switch of controlled terminal, for example with metal-oxide semiconductor (Metal Oxide Semicondutor, MOS) switch.When buffer circuit 40 constitutes with MOS switch I S1 and IS2, wherein the grid of the grid of MOS switch I S1 and MOS switch I S1 is the controlled terminal of buffer circuit 40 and is connected to running voltage P3V3, makes whether buffer circuit 40 can decide electrically whether powering on of buffer circuit 40 according to the electric power supply of running voltage P3V3.The source electrode of MOS switch I S1 and drain electrode are coupled in main circuit 10 and between the circuit 20, are responsible for the I2C serial data signal I2C_SDA of obstruct or conducting main circuit 10; The source electrode of MOS switch I S2 and drain electrode are coupled in main circuit 10 and between the circuit 20, are responsible for the I2C serial clock signal I2C_SCL of obstruct or conducting main circuit 10.The knowledgeable that knows usually who is familiar with this area should understand, and the embodiment in the buffer circuit 40 is improper to exceed with the MOS switch.In addition, be the buffer circuit 40 of assembly with the MOS switch, wherein the quantity of MOS switch should not exceeded with the quantity of present embodiment, can suitably increase and decrease according to the quantity number of I2C signal.
In addition, in another embodiment, the main circuit 10 of the foregoing description can be the motherboard circuit of computer (not illustrating), and from circuit 20 back plane circuitry of computer for this reason, so buffer circuit 40 can be isolated between motherboard circuit and back plane circuitry or the transmission of conducting I2C signal.
Because buffer circuit 40 is coupled to main circuit 10 and between the circuit 20, when normal operation, main circuit 10, supply electric power is arranged from circuit 20 and buffer circuit 40, main circuit 10 can transmit the I2C signal to from circuit 20; When holding state, running voltage P3V3 and P5V do not supply electric power and give from circuit 20 and buffer circuit 40, so buffer circuit 40 itself electrically for not powering on, thereby has and intercepts main circuit 10 and transmit the I2C signals extremely from the function of circuit 20.Therefore, buffer circuit 40 makes main circuit 10 can avoid being subjected to influence from circuit 20 at holding state at present.
Generally speaking, according to the buffer circuit of the embodiment of the invention, because of adopt buffer circuit be coupled to main circuit with between the circuit, when signal that buffer circuit isolation main circuit is exported, can avoid the voltage of signals level by drop-down.Therefore, buffer circuit of the present invention solves main circuit and from the Signal Spacing problem between the circuit, more can strengthen the running stability of internal integration bus of circuit (I2C Bus).
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (8)
1. buffer circuit, be coupled to main circuit and between the circuit, be used for described main circuit and described from isolating between the circuit or conducting internal integration circuit signal, when described main circuit electrically for power on described from circuit electrically when not powering on, described buffer circuit is isolated described internal integration circuit signal and is sent to described from circuit, when described main circuit and described from circuit electrically when powering on, the described internal integration circuit signal of described buffer circuit conducting is sent to described from circuit.
2. buffer circuit as claimed in claim 1 is characterized in that, described main circuit is a mainboard, and described is backboard from circuit.
3. buffer circuit as claimed in claim 1 is characterized in that, described buffer circuit is the metal-oxide semiconductor switch.
4. buffer circuit as claimed in claim 1 is characterized in that, described main circuit be electrically coupled to the first running voltage, described buffer circuit second operates voltage with described from being electrically coupled to of circuit.
5. buffer circuit, be coupled to the signal output part of main circuit, be used to isolate or the transmission signal of the described main circuit of conducting, when described main circuit electrically for powering on, and described buffer circuit electrically when not powering on, described buffer circuit makes signal be avoided the voltage of signals level by drop-down by isolation, when described main circuit and described buffer circuit electrically when powering on, described buffer circuit is switched on signal and sends out.
6. buffer circuit as claimed in claim 5 is characterized in that, described main circuit is a mainboard.
7. buffer circuit as claimed in claim 5 is characterized in that, described buffer circuit is the metal-oxide semiconductor switch.
8. buffer circuit as claimed in claim 5 is characterized in that, described main circuit be electrically coupled to first the running voltage, described from circuit be electrically coupled to second the running voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101934367A CN101441611A (en) | 2007-11-21 | 2007-11-21 | Isolating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101934367A CN101441611A (en) | 2007-11-21 | 2007-11-21 | Isolating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101441611A true CN101441611A (en) | 2009-05-27 |
Family
ID=40726053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101934367A Pending CN101441611A (en) | 2007-11-21 | 2007-11-21 | Isolating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101441611A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107678999A (en) * | 2017-10-25 | 2018-02-09 | 东莞博力威电池有限公司 | A kind of I2C isolation circuits |
| WO2020114074A1 (en) * | 2018-12-03 | 2020-06-11 | 珠海格力电器股份有限公司 | Isolation circuit system and method for signal isolation thereby |
-
2007
- 2007-11-21 CN CNA2007101934367A patent/CN101441611A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107678999A (en) * | 2017-10-25 | 2018-02-09 | 东莞博力威电池有限公司 | A kind of I2C isolation circuits |
| WO2020114074A1 (en) * | 2018-12-03 | 2020-06-11 | 珠海格力电器股份有限公司 | Isolation circuit system and method for signal isolation thereby |
| US11888307B2 (en) | 2018-12-03 | 2024-01-30 | Gree Electric Appliances, Inc. Of Zhuhai | Isolation circuit system and signal isolation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090527 |