CN101441585B - Accurate synchronizing method of three-module redundant fault tolerant computer - Google Patents
Accurate synchronizing method of three-module redundant fault tolerant computer Download PDFInfo
- Publication number
- CN101441585B CN101441585B CN200910000651XA CN200910000651A CN101441585B CN 101441585 B CN101441585 B CN 101441585B CN 200910000651X A CN200910000651X A CN 200910000651XA CN 200910000651 A CN200910000651 A CN 200910000651A CN 101441585 B CN101441585 B CN 101441585B
- Authority
- CN
- China
- Prior art keywords
- state
- synchronization
- synchronous
- synchronizer
- machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Hardware Redundancy (AREA)
Abstract
The invention provides a method for accurately synchronizing a triplication redundancy fault-tolerant computer. The method comprises the following steps: embedding synchronizers which are completely the same in three computer modules respectively; tracking synchronizing states of the three computers by a group of shared signal wires; and realizing accurate synchronization of the three computer modules in execution state, timeslice timing and time base counting through state locking or state inserting.
Description
Technical field
The present invention relates to the synchronous method of a kind of redundancy fault-tolerant computer, relate in particular to a kind of method of precise synchronization of embedded three-module redundant fault tolerant computer.
Background technology
Embedded computer is widely used in the every field of national economy as the core apparatus of automatic control system, and its reliability and security receives much concern always.Three-module redundant fault tolerant computer is got two votings in three, under the situation that single computer module breaks down, can export correct result, correctness and security under the system of assurance nonserviceables are to improve one of embedded computer security and the most effective means of reliability.At national economy key areas such as space flight, aviation, railway, chemical industry strong application demand is arranged.
Simultaneous techniques is one of key foundation technology of embedded three-module redundant fault tolerant computer, and is all the more so in the control occasion of high-speed cruising.It is used in the elimination system the asynchronous degree that causes because of factors such as clock, input delays between three computer modules, make in the system three computer modules program execution state, cycle regularly and reach consistent relatively state on the time benchmark.Only in this way three computer modules just can collect identical input signal in the system, simultaneously output are given the voting machine output of putting to the vote after calculating, finish the triplication redundancy fault tolerance veritably.Some at a high speed, accurate embedded Control occasion (reaching the Train Control of 300km/h such as speed per hour), frequency, the time precision of the control signal of system's output all had very high demand.This just requires the three-module redundant fault tolerant computer system can reach very high synchronization accuracy.
After three-module redundant fault tolerant computer was born, people just studied various simultaneous techniquess constantly, proposed to comprise tasks synchronization, interrupted synchronously, common clock, phase-locked synchronous, multistage multiple method for synchronous synchronously.Each is variant because of specific implementation is different for synchronization accuracy, how at tens of us between the number ms.
Tasks synchronization be with independent operating in the system, have certain logic function the once operation of task as synchronous foundation, one or more key points are set in task.When task run arrives key point, by data exchange channel, between three machines switching task state of a process data and (or) application data.In identical key point, the status data of normal tasks and application data should have consistance preferably, by comparison, the voting to state and application data, the program execution state of three computer modules are synchronized in the regular hour scope.The ultimate principle of tasks synchronization as shown in Figure 3, core concept is by the mutual wait between three machines, inserts certain stand-by period in the task on two machines faster in operation, makes them synchronous with the slowest Realization by Machine.The key point of tasks synchronization can be the data voting comparison point, also can be the special synchronous points that is provided with.It is a kind of loose synchronous that tasks synchronization belongs to, can be divided into three kinds of operating system grade, routine library and user classes on user's participation program, on hardware supported, can be divided into forms such as shared storage, parallel communications, serial communication, more common based on the routine library implementation of serial communication.The sort of mode no matter, its synchronization accuracy depends on exchanges data speed and state judgement time, generally can only reach μ S level, shared storage also can be introduced new Single Point of Faliure failure mode to system.
Interrupt utilizing synchronously the trigger point of a public exterior interrupt as system synchronization.After external interrupt arrived, three computer modules were judged the other side's interruption status recognition mutually, enter interrupt service routine synchronously, carry out state and exchanges data in interrupt service routine, and three computer module time references are realized synchronously.
This method of synchronization is discerned exterior interrupt by making three machines in the same instruction cycle, can make the synchronization accuracy of the time reference of system reach an instruction execution cycle.Though also can in interrupt service routine, carry out the output of control signal and the collection of input signal, guarantee the synchronism of the input of three machines, output procedure, the executing state of three machines is reached synchronously, can not adapt to the application scenario of embedded control system.Public exterior interrupt has also been introduced new Single Point of Faliure failure mode to system.
Common clock belongs to a kind of tightly coupled hardware synchronization mode synchronously, its core concept is to allow all computer modules adopt same common clock source in the system, can guarantee system clock and the synchronous accuracy of time benchmark, but can cause thrashing during clock source module fault, introduce the Single Point of Faliure failure mode.The reliability of clock module can be improved by the mode of redundancy clock, but the Single Point of Faliure failure mode can't be eliminated fully.This method of synchronization can not guarantee the consistance of three computer module executing states simultaneously, must could guarantee the synchronous fully of three-module redundant fault tolerant computer system in conjunction with other simultaneous techniquess.This method of synchronization is seldom used at present.
Phase-locked is to utilize three computer clock signals to carry out reciprocal feedback synchronously, generates a reference signal, and serves as according to the clock drift of proofreading and correct self with this reference signal, thereby reaches the purpose of clock synchronization.There is not the Single Point of Faliure failure mode in this method, can realize the precise synchronization of each computer module clock simultaneously, but it realizes relative complex, can only realize the synchronous of clock self yet, can not guarantee the synchronous of machine executing state.
In sum, although people are obtaining a large amount of achievements in research aspect the simultaneous techniques of three-module redundant fault tolerant computer, but along with deepening continuously of using of embedded control system with embedded data is handled and the raising of control accuracy, existing simultaneous techniques is the at a high speed accurate application demand of embedded Control well, is badly in need of the low-cost highly reliable three-module redundant fault tolerant computer precise synchronization technology of research.
Summary of the invention
The present invention is intended to study a kind of precise synchronization technology, by two state machine tracks and locking, so that the state synchronized precision of three-module redundant fault tolerant computer and Shi Ji synchronization accuracy reach below the 30ns, and save valuable interconnect resource, reduce and realize cost and other system resource overhead.
The present invention realizes by adopting following technical scheme.
A kind of method of three-module redundant fault tolerant computer precise synchronization, it is characterized in that, in each of three computer modules, embed an identical synchronizer, to realize the state synchronized of three computer modules, cycle synchronisation and Shi Ji are synchronous, described synchronizer comprises synchronization state tracker and the state lock that links to each other with this synchronization state tracker, timeslice timer and time base counter, described synchronization state tracker is by one group of synchronous signal line of sharing, adopt the dicyclo state machine to monitor the solicited status of three synchronizers and the duty of time base counter, this dicyclo state machine comprises state synchronized state machine and Shi Ji synchronous state machine
Described state synchronized state machine is used to realize state synchronized, and the method for this state synchronized comprises:
(1) when needs carried out state synchronized, computer module sent synchronization request to synchronizer, started synchronization state tracker and entered search;
(2) after synchronization state tracker starts, send the state synchronized request of this machine, and the synchronization request of beginning other two synchronizers of search on the shared synchronous signals line, the state lock of utilization makes computer module enter one and keeps state;
(3) after the synchronization request of search, change track-while-scan state (4) immediately over to, follow the tracks of this machine and the solicited status that sends the synchronizer of synchronization request, and continue the synchronization request of the 3rd synchronizer of search from any one synchronizer;
(4) search the synchronization request of the 3rd synchronizer after, change the tracking mode of step (5) over to; If in official hour, fail to search the synchronization request of the 3rd synchronizer, think that then synchronous fault takes place the 3rd computer module, also changes the tracking mode of step (5) over to;
(5) record current search result continues to follow the tracks of existing 1 cycle of synchronization request, if no abnormal situation changes step (6) over to; If the synchronization request that has searched lost efficacy, then change step (2) over to and follow the tracks of again;
(6) lock-out state of disarm state lock, completion status is synchronous;
The base synchronous state machine is used to realize time base synchronously when described, this time base employing synchronously method of approaching gradually, the base synchronous state machine clock period when time error of supposing each synchronism eliminates is N, this time basic synchronous method comprise:
(1) in the time base counter work, constantly broadcast self working state by synchronization state tracker to other synchronizers, synchronization state tracker is in each broadcasting time base counter duty, and base is followed the tracks of during startup;
(2) carry out necessary state delay after, base status signal when other synchronizers of search are sent here on the shared synchronous signals line;
The time delay of base state when (3) sending, on this machine time base counter, insert N-1 or zero latent period according to other synchronizers;
(4), then in the time base counter of this machine, insert N waiting status if other synchronizers are not sent time base status signal in the clock period of regulation.
Preferably, in status synchronizing process, if search time base status signal, synchronization state tracker locks status synchronizing process, and the base synchronous state machine is held the synchronous status tracking of line timebase when starting immediately.
Preferably, state synchronized realizes by two levels of software and hardware, when system arrives synchronous points, at first exchange the executing state and the synchronizing information of three machines by the exchanges data path by software, realize the synchronously thick of three machines, then, restart synchronizer and carry out hardware synchronization, realize the precise synchronization of three machines.
Preferably, the step of cycle synchronisation comprises:
(1) in status synchronizing process, the timeslice timer is forced zero setting;
(2) just allow the timeslice timer to begin counting after state synchronized finishes;
(3) the timeslice timer is after its count value reaches setting, generation time sheet interrupt request.
Description of drawings
Fig. 1 is the synchronizing circuit composition frame chart based on status tracking of the present invention;
Fig. 2 is the process flow diagram of dicyclo state machine of the present invention;
Fig. 3 is the time flow chart of tasks synchronization in the prior art.
Embodiment
In general, three-module redundant fault tolerant computer comprises synchronous three aspects of state synchronized, cycle synchronisation, system time reference (time base) synchronously.State synchronized is by a synchronizing process, makes the instruction executing state of three computer modules reach consistent relatively; Embedded computer generally adopts property control of fixed time slicing performance period or data acquisition task, cycle synchronisation is exactly the consistance that guarantees the task performance period of each computer module in the three-module redundant fault tolerant computer, it generally carries out at the section start of duty cycle, is a kind of special shape of state synchronized; The time base be used for making each computer module can keep an identical time reference synchronously.The precision of state synchronized has determined the precision of embedded triplication redundancy computer data acquiring and control signal output, directly affects the control accuracy of triplication redundancy computing machine and the highest output speed of control signal.
In order to improve the synchronous degree of accuracy of three machines, the present invention adopts synchronizing linkage shown in Figure 1, in each computer module, embed an identical hardware synchronization device, utilize one group to share the synchronous regime that signal wire is followed the tracks of three machines, insert by state locking or state, realize that three computer modules are in executing state, the regularly timely basic enumerative precise synchronization of timeslice.
Synchronizer comprises synchronization state tracker (SSTU) and the state lock, timeslice timer and the time base counter that link to each other with this SSTU.SSTU adopts a dicyclo state machine as shown in Figure 2 monitoring the duty of the solicited status and the time base counter of three synchronizers by one group of synchronous signal line (SSL) of sharing always.This dicyclo state machine comprises state synchronized state machine and Shi Ji synchronous state machine.This state synchronized state machine is used to realize state synchronized.State synchronization method is as follows:
(1) when needs carried out state synchronized, computer module sent synchronization request to synchronizer, started SSTU and entered search;
(2) after SSTU starts, send the state synchronized request of this machine, and the synchronization request of beginning other two synchronizers of search on SSL, utilize state lock (SLU) to make computer module enter one and keep state;
(3) after the synchronization request of search, change track-while-scan state (4) immediately over to, follow the tracks of this machine and the solicited status that sends the synchronizer of synchronization request, and continue the synchronization request of the 3rd synchronizer of search from any one synchronizer;
(4) search the synchronization request of the 3rd synchronizer after, change the tracking mode of step (5) over to; If (as 256 state machine clocks) fail to search the synchronization request of the 3rd synchronizer in official hour, think that then synchronous fault takes place the 3rd computer module, also changes the tracking mode of step (5) over to;
(5) record current search result continues to follow the tracks of existing 1 cycle of synchronization request, if no abnormal situation changes step (6) over to; If the synchronization request that has searched lost efficacy, then change step (2) over to and follow the tracks of again;
(6) lock-out state of releasing SLU, completion status is synchronous.
Base synchronously when the base synchronous state machine was used to realize when described.The method that the employing synchronously of time base approaches gradually, when three computer module time reference counter existed than mistake, each synchronizing process only needs removed a part of error, repeatedly synchronously after, the time reference of three machines will reach fully synchronously gradually.The base synchronous state machine clock period when time error of supposing each synchronism eliminates is N, the time base method for synchronous as follows:
(1) in the time base counter work, constantly broadcasts self working state to other synchronizers by SSTU.SSTU starts the time basic tracking loop of dicyclo state machine in each broadcasting time base counter duty;
(2) carry out necessary state delay after, base status signal when other synchronizers of search are sent here on SSL;
The time delay of base state when (3) sending, on this machine time base counter, insert N-1 or zero latent period according to other synchronizers;
(4), then in the time base counter of this machine, insert N waiting status if other synchronizers are not sent time base status signal in the clock period of regulation.
After in a single day time base counter reached synchronously, they will realize a kind of state locking, constantly eliminate the error that three machine timing differentials are brought, and keep a kind of synchronous regime, make three time base counter errors on the computer module can not surpass 1 state machine clock.Because base synchronous state machine clock when having adopted hardware state lock mode, synchronizer also can guarantee after finishing synchronously, to make the error of three computer module executing states to be no more than.When the synchronizer work clock is 33MHz, just can guarantee that the synchronous precision of the state synchronized of three machines and time base reaches below the 30ns.
Need to prove, in status synchronizing process, if search time base status signal, SSTU can lock status synchronizing process, the base synchronous state machine is held the synchronous status tracking of line timebase when starting immediately, and the synchronous priority of base will be higher than state synchronized when that is to say.
Need to prove that also the step of cycle synchronisation generally includes:
(1) in status synchronizing process, the timeslice timer is forced zero setting;
(2) just allow the timeslice timer to begin counting after state synchronized finishes;
(3) the timeslice timer is after its count value reaches setting, generation time sheet interrupt request.
The requirement of aspects such as the restriction of consideration SSTU hardware resource and system reconfiguration is divided into two levels of software and hardware with state synchronized and realizes.When system arrives synchronous points, at first by software according to traditional tasks synchronization method, exchange the executing state and the synchronizing information of three machines by the exchanges data path, realize the synchronously thick of three machines, the asynchronous degree of the execution of three computer modules is reduced to certain scope.Then, restart synchronizer and carry out hardware synchronization, realize the precise synchronization of three machines.
Be the analysis that test result is carried out below.
According to above-mentioned novel synchronous method based on status tracking and locking, adopt the 80X86 processor, realized a three-module redundant fault tolerant computer, comprised the output of 10 way switch amounts and one 32 s' time basic timer.The system works clock frequency is 33MHz, precision 100ppm, and serial communication mode is adopted in the exchange of three machine datas, and traffic rate is 8MHz.Duty cycle is set at 100ms, carries out cycle synchronisation when the cycle begins one time.The switching value output function is arranged on about the 80ms of task execution, carries out state synchronized before the output.This three-module redundant fault tolerant computer sync correlation parameter measurements is as shown in table 1.
The main synchronization parameter measurement result of table 1
| Measurement parameter | Measured value |
| The state synchronized precision | ＜30ns |
| Time base synchronization accuracy | ＜30ns |
| Lock in time expense | ＜200ns |
| Switching value signal maximum error | ＜32ns |
As can be seen from Table 1, the state synchronized precision of this three-module redundant fault tolerant computer and time base synchronization accuracy have all reached below the 30ns, and method for synchronous that this explanation the present invention provides has good three machine synchronization accuracies.The error of switching value signal output is greater than the about 2ns of state synchronized precision, and this part error is because the new accumulated error that three machine clock drifts cause in the switching value written-out program implementation.
Compare with method for synchronous in the past, the state-based that the present invention provides is followed the tracks of the method for synchronous with locking mechanism, can effectively improve the synchronization accuracy of three-module redundant fault tolerant computer, in the situation of using general precision clock oscillator (100ppm), the time base of three machines is reached below the 30ns with the state synchronized precision synchronously, and the while can not introduced new single point failure fault mode to system. The method adopts pure digi-tal state machine implementation, can utilize easily the low-cost highly reliable Project Realization of advanced device realization such as CPLD/FPGA, is conducive to make up a kind of standardized embedded three-module redundant fault tolerant computer kernel.
Claims (4)
1. the method for a three-module redundant fault tolerant computer precise synchronization, it is characterized in that, in each of three computer modules, embed an identical synchronizer, to realize the state synchronized of three computer modules, cycle synchronisation and Shi Ji are synchronous, described synchronizer comprises synchronization state tracker and the state lock that links to each other with this synchronization state tracker, timeslice timer and time base counter, described synchronization state tracker is by one group of synchronous signal line of sharing, adopt the dicyclo state machine to monitor the solicited status of three synchronizers and the duty of time base counter, this dicyclo state machine comprises state synchronized state machine and Shi Ji synchronous state machine, described state synchronized state machine is used to realize state synchronized, and the method for this state synchronized comprises:
(1) when needs carried out state synchronized, computer module sent synchronization request to synchronizer, started synchronization state tracker and entered search;
(2) after synchronization state tracker starts, send the state synchronized request of this machine, and the synchronization request of beginning other two synchronizers of search on the shared synchronous signals line, the state lock of utilization makes computer module enter one and keeps state;
(3) after the synchronization request that searches from any one synchronizer, change track-while-scan state step (4) immediately over to, follow the tracks of this machine and the solicited status that sends the synchronizer of synchronization request, and continue the synchronization request of the 3rd synchronizer of search;
(4) search the synchronization request of the 3rd synchronizer after, change the tracking mode of step (5) over to; If in official hour, fail to search the synchronization request of the 3rd synchronizer, think that then synchronous fault takes place the 3rd computer module, also changes the tracking mode of step (5) over to;
(5) record current search result continues to follow the tracks of existing 1 cycle of synchronization request, if no abnormal situation changes step (6) over to; If the synchronization request that has searched lost efficacy, then change step (2) over to and follow the tracks of again;
(6) lock-out state of disarm state lock, completion status is synchronous;
The base synchronous state machine is used to realize time base synchronously when described, this time base employing synchronously method of approaching gradually, the base synchronous state machine clock period when time error of supposing each synchronism eliminates is N, this time basic synchronous method comprise:
(1) in the time base counter work, constantly broadcast self working state by synchronization state tracker to other synchronizers, synchronization state tracker is in each broadcasting time base counter duty, and base is followed the tracks of during startup;
(2) carry out necessary state delay after, base status signal when other synchronizers of search are sent here on the shared synchronous signals line;
(3) according to other synchronizers send the time base state time delay, on this machine time base counter, insert N-1 or zero latent period;
(4), then in the time base counter of this machine, insert N waiting status if other synchronizers are not sent time base status signal in the clock period of regulation.
2. method according to claim 1, it is characterized in that: in status synchronizing process, if base status signal when searching, synchronization state tracker locks status synchronizing process, and the base synchronous state machine is held the synchronous status tracking of line timebase when starting immediately.
3. method according to claim 1, it is characterized in that: described state synchronized realizes by two levels of software and hardware, when system arrives synchronous points, at first by executing state and the synchronizing information of software by three computer modules of exchanges data path exchange, realize the synchronously thick of three computer modules, then, restart synchronizer and carry out hardware synchronization, realize the precise synchronization of three computer modules.
4. method according to claim 1 is characterized in that: the step of described cycle synchronisation comprises:
(1) in status synchronizing process, the timeslice timer is forced zero setting;
(2) just allow the timeslice timer to begin counting after state synchronized finishes;
(3) the timeslice timer is after its count value reaches setting, generation time sheet interrupt request.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910000651XA CN101441585B (en) | 2009-01-13 | 2009-01-13 | Accurate synchronizing method of three-module redundant fault tolerant computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910000651XA CN101441585B (en) | 2009-01-13 | 2009-01-13 | Accurate synchronizing method of three-module redundant fault tolerant computer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101441585A CN101441585A (en) | 2009-05-27 |
| CN101441585B true CN101441585B (en) | 2010-07-14 |
Family
ID=40726032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910000651XA Expired - Fee Related CN101441585B (en) | 2009-01-13 | 2009-01-13 | Accurate synchronizing method of three-module redundant fault tolerant computer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101441585B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101610145B (en) * | 2009-07-03 | 2013-08-07 | 中兴通讯股份有限公司 | Method and system for realizing synchronous control of distributed system |
| CN102621938A (en) * | 2011-01-28 | 2012-08-01 | 上海新华控制技术(集团)有限公司 | Triple redundancy control system in process control and method thereof |
| CN102724083A (en) * | 2012-05-25 | 2012-10-10 | 哈尔滨工程大学 | Degradable triple-modular redundancy computer system based on software synchronization |
| CN103473154B (en) * | 2013-08-23 | 2015-08-19 | 北京控制工程研究所 | A kind of three machine Hot Spare computing machines when airliner certainty annuity |
| CN103473156B (en) * | 2013-09-24 | 2015-07-08 | 北京控制工程研究所 | Hot backup fault-tolerance method based on real-time operating systems and used for three satellite borne computers |
| CN106533601A (en) * | 2016-10-27 | 2017-03-22 | 中国电子科技集团公司第三十二研究所 | Method for clock synchronization in modular redundancy system |
| CN106656396A (en) * | 2017-01-16 | 2017-05-10 | 南京恩瑞特实业有限公司 | Clock synchronization method in on-vehicle system |
| CN107894706B (en) * | 2017-12-05 | 2021-04-06 | 山东航天电子技术研究所 | On-satellite time management system based on FPGA and CPU integrated control |
| CN109951087B (en) * | 2019-03-22 | 2020-08-18 | 中国长江电力股份有限公司 | High-redundancy synchronization method of intelligent rectifier bridge based on FPGA and communication network |
| CN110134554B (en) * | 2019-05-21 | 2023-08-22 | 上海航天电子通讯设备研究所 | Synchronous and self-checking voting circuit |
| US12019166B2 (en) | 2021-07-13 | 2024-06-25 | Orolia Usa Inc. | Multiple redundant disciplined oscillator systems in a spoofing resistant reference time source system and methods thereof |
-
2009
- 2009-01-13 CN CN200910000651XA patent/CN101441585B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101441585A (en) | 2009-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101441585B (en) | Accurate synchronizing method of three-module redundant fault tolerant computer | |
| US20220012264A1 (en) | Pipelining Paxos State Machines | |
| CN101931580B (en) | System on chip adopting ARINC 659 rear panel data bus interface chip | |
| CN102111261B (en) | TDMOW serial bus-based distributed oscillographs synchronization method | |
| CN102361356B (en) | System and method for testing remote communication volume of transformer substation testing-controlling device | |
| CN102055544A (en) | System and method for synchronously monitoring secondary equipment time of power supply system | |
| CN109656239B (en) | A kind of rail locomotive network control system method for diagnosing faults and its diagnostic device | |
| CN103684734B (en) | A kind of hot-standby redundancy computer time synchronization system and method | |
| CN102752065A (en) | Time synchronization method and system | |
| US6981063B1 (en) | Method for time synchronization of a computer network, and computer network with time synchronization | |
| CN107239433A (en) | A kind of triple redundance computer synchronous method | |
| CN102195769A (en) | Clock synchronization method for automobile CAN (Control Area Network) | |
| CN103457716A (en) | Optimizing time synchronizing device for multi-channel clock sources | |
| CN104724145B (en) | A kind of locomotive velocity measuring range-measurement system | |
| CN110879549B (en) | Redundancy measurement architecture based on cross-comparison method and redundancy management method | |
| CN101694579B (en) | Soe intelligent module | |
| CN106647228B (en) | Converter station master clock fault judgment system | |
| CN106774397A (en) | A kind of four redundance flight control systems computer synchronous method | |
| CN110988599A (en) | Distributed wave recording high-precision synchronization method for power distribution fault indicator | |
| CN106814596B (en) | A kind of Hardware-in-the-Loop Simulation in Launch Vehicle test ground installation method for synchronizing time | |
| CN103699103B (en) | The method of sequence of events recording in scattered control system | |
| RU2279707C2 (en) | Fault-tolerant computing device and method for functioning of said device | |
| CN104881329B (en) | A kind of method of battery assembly off-line test platform multithreading time synchronization | |
| CN114488770B (en) | Dual redundancy control system for realizing dynamic time synchronization between aircraft equipment | |
| CN100547557C (en) | A kind of combined synchronization method of multi-module electronic system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100714 Termination date: 20180113 |