CN101436565A

CN101436565A - Method for preparing shallow plow groove isolation

Info

Publication number: CN101436565A
Application number: CNA2007100942243A
Authority: CN
Inventors: 陈华伦; 熊涛; 陈瑜; 陈雄斌; 罗啸
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-11-13
Filing date: 2007-11-13
Publication date: 2009-05-20

Abstract

The invention discloses a method for preparing a shallow groove isolator, which is used for preparing a semiconductor device with a size of 0.15um or below, and increases a step of using large inclined-angle injection of non-crystalline ions to make silicon atoms at the top angle of a groove fully non-crystallized before thermally growing a pad oxide layer in the process flow for preparing the prior shallow groove isolator. According to the characteristic that oxidation rate of amorphous silicon prepared by the method is quicker than that of crystalline silicon, the silicon is non-crystallized and then thermally oxidized to form the appearance of a smooth silicon interface of a groove top angle.

Description

Shallow trench isolation from the preparation method

Technical field

The present invention relates to a kind of shallow trench isolation from the preparation method, relate in particular to a kind of the shallow trench isolation that is used for 0.15um and following technology from the preparation method.

Background technology

Shallow trench isolation technology (Shallow Trench Isolation) be a kind of in very lagre scale integrated circuit (VLSIC) widely used device separation.Because the less relatively advantage of the tool area occupied of isolation structure of STI prepared own becomes the main flow device isolation structure that advanced process adopts.The principle of sti structure preparation is the etched open surface of silicon of part, uses CVD (CVD (Chemical Vapor Deposition) method) method SiO then ₂Insert in the groove that is excavated.General preparation flow is at present: (1) is the grow liners oxide layer on substrate, then the deposit hard mask layer; (2) photoresist coating and exposure imaging; (3) hard mask layer etching and removal photoresist; (4) dry etching forms groove on substrate; (5) cushion oxide layer of corner, wet etching groove top; (6) in the inboard heat growth of groove bed course oxide layer; (7) HDP oxide layer filling groove; (8) cmp and hard mask layer are removed.Like this, just formed the isolated area of oxide layer (oxide) at the non-active area of silicon chip.This shallow trench (STI) processing procedure is commonly referred to hard mask shallow ditch groove separation process.

At present, in 0.15 micron and following semiconductor production processing procedure, all adopted this technology usually.But this technology has a shortcoming, promptly all make the pattern of corner, shallow trench top become very sharp-pointed usually, as seen shown in Fig. 1 broken circle, be unfavorable for the control of device grids oxide layer attenuate effect (Gate oxide thinning effect) and narrow-channel effect and cause the leakage current (Inverse narrow-width channel effect) of device.

Summary of the invention

The technical problem to be solved in the present invention provide a kind of shallow trench isolation from the preparation method, the shallow trench isolation that adopts the preparation of this method is from can effectively avoiding in the fleet plough groove isolation structure corner, top silicon interface too sharp-pointed.

For solving the problems of the technologies described above, shallow trench isolation of the present invention from the preparation method, be used for the preparation of 0.15um and following size semiconductor device, comprise the steps:

(1) deposit cushion oxide layer and hard mask layer on the silicon substrate;

(2) photoresist coating and lithographic definition shallow trench zone;

(3) hard mask layer etching and removal photoresist;

(4) dry etching forms shallow trench on substrate;

(5) cushion oxide layer of corner, wet etching shallow trench top;

(6) ion injects the silicon substrate on shallow trench top, makes silicon atom wherein decrystallized;

(7) heat growth bed course oxide layer in shallow trench;

(8) fill shallow trench with HDPCVD technology silicon oxide deposition;

(9) CMP grinds and the hard mask layer removal.

Shallow trench isolation of the present invention from the preparation method, utilize oxidation rate this characteristic faster of amorphous silicon than the oxidation rate of crystalline silicon, by at traditional shallow trench isolation before the heat of preparation technology's flow process growth bed course oxide layer, utilizing decrystallized ion high inclination-angle to inject makes the silicon atom of shallow trench drift angle fully decrystallized, and then in ensuing heat growth oxidation (Liner oxidation) process, the silicon of the oxidation consumption of shallow trench drift angle is more than the silicon that sidewall oxidation consumes, finally obtain slick and sly shallow trench drift angle silicon interface pattern, avoid the element leakage that sharply causes because of drift angle.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the shallow ditch groove structure schematic diagram of prior art for preparing;

Fig. 2 is preparation method's of the present invention flow chart;

Fig. 3 is the cross section structure schematic diagram after the enforcement step of the present invention (2);

Fig. 4 is the cross section structure schematic diagram after the enforcement step of the present invention (3);

Fig. 5 is the cross section structure schematic diagram after the enforcement step of the present invention (4);

Fig. 6 is the cross section structure schematic diagram after the enforcement step of the present invention (5);

Fig. 7 is the cross section structure schematic diagram after the enforcement step of the present invention (6);

Fig. 8 is the cross section structure schematic diagram after the enforcement step of the present invention (7);

Fig. 9 is the cross section structure schematic diagram after the enforcement step of the present invention (9);

Embodiment

Shallow trench isolation of the present invention from the preparation method, be used for 0.15um and following dimension process.In conjunction with Fig. 2 technological process of the present invention is described:

(1) deposit cushion oxide layer and hard mask layer on the substrate.First deposit one cushion oxide layer on silicon substrate, after deposit hard mask layer thereon, common hard mask material layer is a silicon nitride, is used for the silicon substrate at etching process protection active area.

(2) photoresist coating and lithographic definition shallow trench zone (see figure 3).Be used in the photoetching process in the 0.15um technology, for the requirement of satisfying the photoetching resolution that less characteristic size brings and the depth of field (DOF) harsh especially, generally require photoresist thinner, the photoresist thickness that uses in photoresist thickness among the preparation method of the present invention and the normal 0.15um technology is similar.

(3) hard mask layer that exposes after the etching exposure, cushion oxide layer is to surface of silicon, and photoresist is removed in the back.

(4) dry etching silicon substrate forms shallow trench.

(5) cushion oxide layer of corner, wet etching shallow trench top.This step can make corner, groove top become slick and sly.

(6) ion injects the silicon substrate of shallow trench drift angle, makes silicon atom wherein decrystallized.Can adopt the decrystallized ion of high inclination-angle to inject, make the silicon atom of shallow trench drift angle fully decrystallized.Inject ion at this and can anyly can make the decrystallized ion of silicon atom, for example Si ion or germanium ion.The ion surface density of injecting is: 10 ¹⁴～10 ¹⁶Atom/square centimeter, the injection energy of silicon ion can be made as: 10-50kev, the injection energy of germanium ion can be made as: 30-80kev.In concrete enforcement, the inclination angle a that ion injects can be controlled between 30 degree～60 degree, guarantee to be infused in the shallow trench top corner regions, make amorphized siliconization.

(7) in the inboard heat growth of shallow trench bed course oxide layer.Because the oxidation rate of amorphous silicon is greater than the oxidation rate of crystalline silicon, when this goes on foot thermal oxidation, the silicon atom of the consumption of non-crystallization region is faster than the silicon atom that crystalline region consumes, the silicon of Gu Dingjiaochu and the interface of silica are more level and smooth, finally obtain slick and sly drift angle silicon interface pattern, avoid the element leakage that sharply causes because of drift angle.

(8) fill shallow trench with HDPCVD technology silicon oxide deposition.

(9) be that chemico-mechanical polishing (CMP) grinding makes substrate surface smooth at last, and remove hard mask layer.

Claims

1, a kind of shallow trench isolation from the preparation method, be used for 0.15um and following size semiconductor device the preparation, it is characterized in that this method comprises the steps:

(1) deposit cushion oxide layer and hard mask layer on the silicon substrate;

(2) photoresist coating and lithographic definition shallow trench zone;

(3) hard mask layer etching and removal photoresist;

(4) dry etching forms shallow trench on substrate;

(5) cushion oxide layer at wet etching shallow trench drift angle place;

(6) ion injects the silicon substrate of shallow trench drift angle, makes silicon atom wherein decrystallized;

(7) heat growth bed course oxide layer in shallow trench;

(8) fill shallow trench with HDPCVD technology silicon oxide deposition;

(9) CMP grinds, and hard mask layer and cushion oxide layer are removed.

2, according to the described preparation method of claim 1, it is characterized in that: it is 30～60 degree that described step (6) intermediate ion injects the inclination angle.

3, according to claim 1 or 2 described preparation methods, it is characterized in that: the ion dose surface density of injecting in the described step (6) is 10 ¹⁴～10 ¹⁶Atom/square centimeter.

4, according to the described preparation method of claim 3, it is characterized in that: the ion that injects in the described step (6) is silicon ion or germanium ion.

5, according to the described preparation method of claim 4, it is characterized in that: the injection energy of described silicon ion is: 10-50kev.

6, according to the described preparation method of claim 4, it is characterized in that: the injection energy of described germanium ion is: 30-80kev.