CN101383631B - Frequency Offset Estimation and Compensation Method for TD-SCDMA Terminal - Google Patents

Abstract

A frequency deviation estimation and compensation method of TD-SCDMA terminal, after receiving the analog-to-digital conversion of the signal, carry on the frequency deviation estimation and compensation in the digital domain; before sending the sending signal to the digital-to-analog conversion, carrying out frequency pre-bias in a digital domain; wherein: after the received signal is converted into a digital signal, the digital signal is mixed with local frequency generated by a carrier digital controlled oscillator, and the mixed signal is subjected to frequency offset estimator to estimate a residual frequency offset signal; converting the frequency offset signal into a local carrier signal which is increased along with the time through a complex multiplier and a complex register in a carrier numerically-controlled oscillator; the local carrier signal is multiplied by the received signal, thus forming a loop. As the loop converges, the frequency deviation eventually converges to within the desired error. Meanwhile, the frequency phase-locked loop and the sampling clock adjusting loop are twisted together, so that the algorithm can tolerate certain sampling frequency deviation.

Description

The frequency offset estimating at TD-SCDMA terminal and compensation method

Technical field

The present invention relates to wireless communication technology field, the frequency offset estimating and the compensation method at particularly a kind of TD-SCDMA terminal.

Background technology

TD-SCDMA (time division duplex-synchonism CDMA mobile communication system) is a kind of 3G (Third Generation) Moblie standard that is proposed by China, is one of the world's three big standards.At present, TD-SCDMA will soon move towards to use in China, and the research of relevant TD-SCDMA is just like a raging fire.

Because the unsteadiness of doppler phenomenon and crystal oscillator, all there are a frequency departure in the reception signal center frequency of any communication system and local oscillating frequency.Therefore must correct.General circuit for rectifying makes local oscillating frequency follow the tracks of the reception signal frequency exactly, is referred to as the automatic frequency tracking circuit.Automatic frequency tracking can be realized at analog domain, also can realize at numeric field.Along with the development of Digital Signal Processing, modern receiver is main with Digital Implementation.The TD-SCDMA system also is the same, and terminal receiver also must be carried out automatic frequency tracking.In addition, because the base station of TD-SCDMA receives the signal of a plurality of portable terminals simultaneously, their frequency departure has nothing in common with each other, and is unable to estimate and corrects.Therefore, each terminal use is before sending signal, and reply is sent frequency and done a prebias, and it is identical to make that each subscriber signal not only arrives time of base station, and the frequency that each subscriber signal arrives the base station is also identical.The present invention provides a kind of downstream frequency algorithm for estimating of numeric field, and this algorithm is used in the middle of the phase-locked loop, carries out frequency compensation to received signal.And, estimate the downstream frequency deviation of coming out, be used for simultaneously upstream frequency is carried out prebias.

Summary of the invention

The object of the present invention is to provide the frequency offset estimating and the compensation method at a kind of TD-SCDMA terminal.

For realizing above-mentioned purpose, the frequency offset estimating and the compensation method at TD-SCDMA provided by the invention terminal after the number conversion of reception signal mode, are carried out frequency offset estimating and compensation at numeric field; Sent signal before sending into digital-to-analogue conversion, in the advanced line frequency prebias of numeric field; Wherein:

After receiving conversion of signals and being digital signal, the local frequency mixing that at first produces with carrier number controlled oscillator (Carrier NCO), the signal after the mixing estimates remaining frequency offset signal through frequency offset estimator (Frequency Offset Estimator);

Look-up table, complex multiplier and the complex register (Register) of this frequency offset signal in carrier number controlled oscillator (Carrier NCO) converted to the local carrier signal that increases in time;

Local carrier signal and reception signal multiplication so constitute a loop.

Described frequency offset estimating and compensation method, wherein, remaining frequency offset signal

Estimation, be with after receiving signal and carrying out downlink frame synchronization gain used descending synchronous code s (n) and its position, will receive signal again and align with the complex conjugate of descending synchronous code s (n) and multiply each other, must y ⁰(n); Descending synchronous code s (n) is postponed to get s (n-1) behind the chip, and complex conjugate and reception signal multiplication with s (n-1) get y ¹(n); So obtain y ²(n), y ³(n) ..., y ^L-1(n); Wherein L is the delay length of multipath;

According to formula 1:

${\hat{R}}^i\left(k\right)=\frac{1}{N-K}\underset{n=k+1}{\overset{N}{\mathrm{\Σ}}}{y}^i\left(n\right)y^{i^{*}}(n-k),$ I=0,1 ..., L-1 (formula 1)

Calculate each y ⁱ(n), i=0,1 ..., the delay of L-1 is relevant

K=1,2 ..., M;

M is a positive integer; N is the length of descending synchronous code;

With each

I=0,1 ..., the L-1 addition: $\hat{R}\left(k\right)=\widehat{R^0}\left(k\right)+\hat{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2007101213715E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}^1}\left(k\right)+...+\widehat{R^{L-1}}\left(k\right),$ With formula 3

$\mathrm{\&Delta;}\hat{f}=\frac{1}{\mathrm{\&pi;}{T}_c(M+1)}\mathrm{Arg}\left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}\hat{R}\left(k\right)\right\}$ (formula 3)

T _cBe the time in sampling interval at Frequency Estimation place, i.e. chip period,

Calculate remaining frequency offset signal.

Described frequency offset estimating and compensation method, wherein, M gets N/2.

Described frequency offset estimating and compensation method, wherein, frequency offset signal is through getting into the carrier number controlled oscillator behind the low pass filter.

Described frequency offset estimating and compensation method, wherein, when frequency offset signal was changed through the carrier number controlled oscillator, this carrier number controlled oscillator converted this frequency offset signal to local carrier increments signal through look-up table.

Described frequency offset estimating and compensation method, wherein, the result after data in the digital controlled oscillator in the complex register and local carrier increment signal multiply each other deposits complex register at next clock.

Described frequency offset estimating and compensation method wherein, receive signal and under the clock about a 6MHz, sample;

Digital signal after the sampling is at first sent into an interpolater (Interpolator), and this interpolater spreading rate with four times under the control of hits controlled oscillator (Sampling NCO) is exported; The carrier wave of output signal and carrier number controlled oscillator (Carrier NCO) output multiplies each other through multiplier, sends into square root raised cosine filter (SRRC) then;

All with four times spreading rate work, the output one tunnel of square root raised cosine filter is sent into timing offset and is detected (TED) electric circuit inspection sampling clock deviation for this multiplier and square root raised cosine filter, forms the sampling clock track loop; Another road is extracted the output of square root raised cosine filter according to the time zero identical with the timing offset testing circuit, is drawn into sampling of a chip;

Frequency offset signal is through formula 3

$\mathrm{\&Delta;}\hat{f}=\frac{1}{\mathrm{\&pi;}{T}_c(M+1)}\mathrm{Arg}\left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}\hat{R}\left(k\right)\right\}$ (formula 3)

T wherein _cBe chip period, M is a positive integer,

Be each y ⁱ(n), i=0,1 ..., the delay of L-1 is relevant, k=1,2 ..., M.

Described frequency offset estimating and compensation method, wherein, sampling clock track loop and Frequency Estimation and track loop combine, and frequency offset estimating can be accomplished in a digital signal processor (DSP).

Description of drawings

Fig. 1 is the schematic diagram of downstream frequency compensation with the upstream frequency prebias of explanation TD-SCDMA.

Fig. 2 is the theory diagram that receive frequency is followed the tracks of phase-locked loop.

Fig. 3 is the algorithm flow chart of frequency offset estimating.

Fig. 4 is sampling clock track loop and frequency offset estimating and the block diagram that combines of compensation loop.

Fig. 5 is the hardware-software partition of explaining when sampling clock track loop and frequency offset estimating combine block diagram specifically to realize with compensation loop.

Embodiment

Below in conjunction with accompanying drawing frequency offset estimating provided by the invention and compensation method are described.

As shown in Figure 1, the compensation of downstream frequency and the biasing of upstream frequency are all carried out at numeric field.If estimate that the frequency deviation of coming out is Δ f; Then descending employing carrier wave

(T is the time in sampling interval at frequency compensation place) carries out frequency compensation, and up employing carrier wave carries out frequency prebias.On/descending frequency translation carries out between digital-to-analogue/analog-to-digital conversion and raised cosine filtering.

The tracking of downstream frequency is carried out in a phase-locked loop.Local frequency

mixing as shown in Figure 2, that the digital signal r of reception (n) at first produces with carrier number controlled oscillator (N.C.O).Signal after the mixing send to a frequency offset estimator (Frequency Offset Estimator) estimate remaining this frequency deviation of frequency deviation through a LPF (L.P.F) after, obtain

and send the local carrier digital controlled oscillator to.The carrier number controlled oscillator is at first through a look-up table (L.U.T); Convert frequency offset signal to carrier phase growth signal this phase place and increase signal through a complex multiplier, a complex register commentaries on classics (Register) changes local carrier

local carrier that increases in time into and multiplies each other with reception signal r (n) again.So constitute a loop.

The algorithm for estimating flow process of the frequency offset estimator among Fig. 2 (Frequency Offset Estimator) is as shown in Figure 3.At first, it is synchronous that the reception signal carries out downlink frame, and the back just can obtain used descending synchronous code s (n) and its position synchronously.To receive signal r (n) and align with the complex conjugate of descending synchronous code s (n) and multiply each other, y ⁰(n).With behind chip of down-going synchronous code delay s (n-1), with the complex conjugate of s (n-1) with receive signal r (n) and multiply each other, y ¹(n).And so on, can obtain y ²(n), y ³(n) ..., y ^L-1(n).Here L is meant the delay length of multipath.According to formula 1

${\hat{R}}^i\left(k\right)=\frac{1}{N-K}\underset{n=k+1}{\overset{N}{\mathrm{\&Sigma;}}}{y}^i\left(n\right)y^{i^{*}}(n-k),$ I=0,1 ..., L-1 (formula 1)

Can calculate each y ⁱN), i=0,1 ..., the delay of L-1 is relevant K=1,2 ..., M.Here M is a positive integer, and getting

N usually is the length of descending synchronous code.Obtain each

i=0; 1 ..., behind the L-1; 2 additions by formula

$\hat{R}\left(k\right)=\widehat{R^0}\left(k\right)+\widehat{R^1}\left(k\right)+...+\widehat{R^{L-1}}\left(k\right)$ (formula 2)

Then, utilize formula 3

$\mathrm{\&Delta;}\hat{f}=\frac{1}{\mathrm{\&pi;}{T}_c(M+1)}\mathrm{Arg}\left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}\hat{R}\left(k\right)\right\}$ (formula 3)

T _cBe the time in sampling interval at Frequency Estimation place, i.e. chip period,

Can calculate remaining frequency deviation.

During actual enforcement, must twist together sampling clock tracking circuit and frequency offset estimating and compensation loop.As shown in Figure 4.The analog signal that receives is sampled under a free-running clock.Digital signal after the sampling is at first sent into an interpolater (Interpolator), and this interpolater spreading rate with four times under the control of sampling clock digital controlled oscillator (Sampling NCO) is exported.The carrier multiplication of these output signals and carrier number controlled oscillator (Carrier NCO) output is sent into a square root raised cosine filter (SRRC) then.This multiplier and square root raised cosine filter are all with four times spreading rate work.The output of square root raised cosine filter is sent into timing offset detection (TED) circuit on the one hand and is removed to detect sampling clock deviation, forms the sampling clock track loop; According to the time zero identical, the output of square root raised cosine filter is extracted on the other hand, be drawn into sampling of a chip with the timing offset detection loop.Sampling after these extract, send into frequency offset estimator (Freq.Estimate) estimate frequency deviation and carry out filtering, through look-up table, output local carrier increment signal.This local carrier increment signal is sent into the carrier number controlled oscillator, forms the carrier signal that increases in time.This carrier signal again with the interpolation output multiplication of interpolater, so form a loop.Notice that frequency offset estimating is according to a sampling of chip gained in the loop, and frequency correction is to carry out according to four samplings of a chip, conversion of intermediate demand.

Concrete conversion regime is that the T in the local carrier signal

of output of look-up table (L.U.T) input type 3 gets

when look-up table (L.U.T) design of carrier number controlled oscillator (N.C.O)

Fig. 5 representes that frequency offset estimating can be accomplished by a digital signal processor (DSP) in software.Other parts are accomplished by the application-specific integrated circuit (ASIC) (ASIC) of hard wire logic.

Claims (8)

1. the frequency offset estimating at a TD-SCDMA terminal and compensation method after the number conversion of reception signal mode, carried out frequency offset estimating and compensation at numeric field; Sent signal before sending into digital-to-analogue conversion, in the advanced line frequency prebias of numeric field; Wherein:

After receiving conversion of signals and being digital signal, the local frequency mixing that at first produces with the carrier number controlled oscillator, the signal after the mixing estimates remaining frequency offset signal through frequency offset estimator;

Look-up table, complex multiplier and the complex register of this frequency offset signal in the carrier number controlled oscillator converted to the local carrier signal that increases in time;

Local carrier signal and reception signal multiplication so constitute a loop.

2. frequency offset estimating according to claim 1 and compensation method, wherein, remaining frequency offset signal

Estimation, be with after receiving signal and carrying out downlink frame synchronization gain used descending synchronous code s (n) and its position, will receive signal again and align with the complex conjugate of descending synchronous code s (n) and multiply each other, must y ⁰(n); Descending synchronous code s (n) is postponed to get s (n-1) behind the chip, and complex conjugate and reception signal multiplication with s (n-1) get y ¹(n); So obtain y ²(n), y ³(n) ..., y ^L-1(n); Wherein L is the delay length of multipath;

According to formula 1:

${\hat{R}}^i\left(k\right)=\frac{1}{N-K}\underset{n=k+1}{\overset{N}{\mathrm{\&Sigma;}}}{y}^i\left(n\right)y^{i^{*}}(n-k),$ I=0,1 ..., L-1 (formula 1)

Calculate each y ⁱ(n), i=0,1 ..., the delay of L-1 is relevant

K=1,2 ..., M;

M is a positive integer; N is the length of descending synchronous code;

With each

I=0,1 ..., the L-1 addition: $\hat{R}\left(k\right)=\widehat{R^0}\left(k\right)+\widehat{R^1}\left(k\right)+...+\widehat{R^{L-1}}\left(k\right),$ With formula 3

$\mathrm{\&Delta;}\hat{f}=\frac{1}{\mathrm{\&pi;}{T}_c(M+1)}\mathrm{Arg}\left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}\hat{R}\left(k\right)\right\}$ (formula 3)

In the formula 3, T _cBe chip period;

Calculate remaining frequency offset signal.

3. frequency offset estimating according to claim 2 and compensation method, wherein, M gets N/2.

4. frequency offset estimating according to claim 1 and compensation method, wherein, frequency offset signal is through getting into the carrier number controlled oscillator behind the low pass filter.

5. frequency offset estimating according to claim 1 and compensation method, wherein, when frequency offset signal was changed through the carrier number controlled oscillator, this carrier number controlled oscillator converted this frequency offset signal to local carrier increments signal through look-up table.

6. frequency offset estimating according to claim 5 and compensation method, wherein, the result after data in the carrier number controlled oscillator in the complex register and local carrier increment signal multiply each other deposits complex register at next clock.

7. frequency offset estimating according to claim 2 and compensation method wherein, receive signal and under the clock of 6MHz, sample;

Digital signal after the sampling is at first sent into an interpolater, and this interpolater spreading rate with four times under the control of hits controlled oscillator is exported; The carrier wave of output signal and the output of carrier number controlled oscillator multiplies each other through multiplier, sends into square root raised cosine filter then;

All with four times spreading rate work, the output one tunnel of square root raised cosine filter is sent into the timing offset testing circuit and is detected sampling clock deviation for this multiplier and square root raised cosine filter, forms the sampling clock track loop; Another road is extracted the output of square root raised cosine filter according to the time zero identical with the timing offset testing circuit, is drawn into sampling of a chip;

Frequency offset signal calculates through formula 3:

$\mathrm{\&Delta;}\hat{f}=\frac{1}{\mathrm{\&pi;}{T}_c(M+1)}\mathrm{Arg}\left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}\hat{R}\left(k\right)\right\}$ (formula 3)

T wherein _cBe chip period.

8. frequency offset estimating according to claim 7 and compensation method, wherein, sampling clock track loop and Frequency Estimation and track loop combine, and frequency offset estimating is accomplished in a digital signal processor.

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