CN101371268B - 存储卡以及存储卡的制造方法 - Google Patents

存储卡以及存储卡的制造方法 Download PDF

Info

Publication number
CN101371268B
CN101371268B CN2007800030594A CN200780003059A CN101371268B CN 101371268 B CN101371268 B CN 101371268B CN 2007800030594 A CN2007800030594 A CN 2007800030594A CN 200780003059 A CN200780003059 A CN 200780003059A CN 101371268 B CN101371268 B CN 101371268B
Authority
CN
China
Prior art keywords
semi
conductor chip
circuit substrate
resin layer
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007800030594A
Other languages
English (en)
Other versions
CN101371268A (zh
Inventor
西川英信
山田博之
武田修一
岩本笃信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN101371268A publication Critical patent/CN101371268A/zh
Application granted granted Critical
Publication of CN101371268B publication Critical patent/CN101371268B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

存储卡(1)具有：电路基板(2)；夹着突起(33)而安装在电路基板(2)上的第一半导体芯片(3)；与第一半导体芯片(3)之间设置小于等于1mm的间隙并夹着突起(53)而安装在电路基板上的第二半导体芯片(5)；覆盖突起(33)的周围，并介于第一半导体芯片(3)和电路基板(2)之间的第一密封树脂层(41)；覆盖突起(53)的周围，并介于第二半导体芯片(5)和电路基板(2)之间的第二密封树脂层(42)；在电路基板(2)的主面侧，覆盖第一半导体芯片(3)和第二半导体芯片(5)的盖部(7)。

Description

存储卡以及存储卡的制造方法
技术领域
本发明涉及一种存储卡及其制造方法。 
背景技术
近年来，作为存储信息的存储介质的一种，使用内置有存储芯片的存储卡。另外，由于在便携性方面的优势，存储卡作为便携式信息终端、及移动电话等便携式电子设备的存储介质而被广泛应用。而且，从提高便携性等观点出发，伴随着对这些便携式电子设备的小型化及薄型化的要求，希望存储卡也进一步小型化。而且，因为存储卡的形状、大小、厚度等都由规格确定，所以在满足规格的同时谋求实现其大容量化。 
因此，已公开了这样一种技术，即，在搭载于引线框上的存储芯片上错开层叠另一块存储芯片。而且，将两块存储芯片的电极及搭载于引线框上的控制芯片的电极通过金属线连接于引线框，从而使存储卡薄型化(例如，参照专利文献1)。 
但是，在专利文献1的存储卡中，由于层叠存储芯片而使其在薄型化方面受到限制，而且结构也变得复杂。另外，由于存储芯片和控制芯片对引线框的安装是通过引线接合法进行的，所以，在安装后，有必要将这些各芯片、金属线、引线框等通过热固化性树脂等密封。此时，由于需要充分覆盖存储芯片及金属线的厚度的密封层，因此，存储卡的小型化和薄型化受到限制。另外，由于除安装步骤外需另外的密封步骤，因此，在降低成本方面也受到限制。 
另一方面，作为存储芯片、控制芯片等半导体芯片的安装方法，已知一种夹着突起(bump)而对半导体芯片的电极和电路基板的电极进行接合 的倒装芯片安装的方法。倒装芯片安装是通过附着在电路基板的电极上的树脂将半导体芯片向电路基板按压，并在该状态下通过使树脂固化而将半导体芯片安装在电路基板上的方法。由此，可以不需要覆盖被安装的半导体芯片等的密封层，与专利文献1中的存储卡相比，能够实现小型化、薄型化。此时，为了实现存储卡的薄型化，要求将存储芯片和控制芯片等不层叠而是平面地配置在电路基板上，为了实现存储卡的小型化，要求将这些半导体芯片相互接近地配置。 
但是，在倒装芯片安装中，在将半导体芯片向电路基板上按压时，半导体芯片下方的树脂在半导体芯片的周围扩散，并在该状态下固化。因此，若将多个半导体芯片例如以小于等于1mm的距离接近配置，则一侧的半导体芯片的安装所使用的树脂会被挤出直到在其周围配置的其他的半导体芯片的安装预定区域并固化。另外，已经附着在其他的半导体芯片的安装预定区域的树脂层会在一侧的半导体芯片固化时变质。其结果就是，难以在安装预定区域中安装其他的半导体芯片。另一方面，如果为了避免树脂层的挤出、变质，而将多个半导体芯片以大于1mm的距离配置，就不能实现存储卡的小型化。这样，由于很难将半导体芯片接近到某种程度(例如1mm)以下进行安装，因此，在存储卡的小型化方面受到限制。 
专利文献1：日本特开2004-13738号公报 
发明内容
本发明的存储卡，具有：电路基板；夹着突起而安装在电路基板的主面上的第一半导体芯片；与第一半导体芯片之间设置有小于等于1mm的间隙、并夹着突起安装在电路基板的主面上的第二半导体芯片；覆盖与第一半导体芯片接合的突起周围，并介于第一半导体芯片和电路基板之间的第一密封树脂层；覆盖与第二半导体芯片接合的突起周围，并介于第二半导体芯片和电路基板之间的第二密封树脂层；在电路基板的所述主面一侧，覆盖第一半导体芯片和第二半导体芯片的盖部。 
通过该结构，能够使结构简略化，并能够实现小型且薄型的存储卡。 
另外，本发明的存储卡的制造方法，具有下述步骤：a)在电路基板的主面上形成第一密封树脂层的步骤，b)在电路基板的主面上形成第二密封树脂层的步骤，c)将第一半导体芯片经由第一密封树脂层向电路基板的主面按压，并夹着突起将第一半导体芯片电连接于电路基板，并使第一密封树脂层固化的步骤，d)与c)并行地将第二半导体芯片隔着第二密封树脂层向电路基板的主面按压，并夹着突起而将第二半导体芯片电连接于电路基板，并使第二密封树脂层固化的步骤，e)在电路基板的主面一侧通过盖部覆盖第一半导体芯片和第二半导体芯片的步骤。 
通过该方法，，能够容易地制造生产效率优良、可靠性高的小型且薄型的存储卡。 
附图说明
图1是表示本发明的第一实施方式所涉及的存储卡的构造的俯视图。 
图2是在图1的2-2线位置剖切的剖视图。 
图3是说明本发明的第一实施方式所涉及的存储卡的制造方法的流程图。 
图4A是说明本发明的第一实施方式所涉及的存储卡的制造方法的主要步骤的剖视图。 
图4B是说明本发明的第一实施方式所涉及的存储卡的制造方法的主要步骤的剖视图。 
图5是表示本发明的第二实施方式所涉及的存储卡的构造的俯视图。 
图6是在图5的6-6线位置剖切的剖视图。 
图7是表示本发明的第二实施方式所涉及的存储卡的其他的例子的俯视图。 
图8是表示本发明的第三实施方式所涉及的存储卡的构造的俯视图。 
图9是在图8的9-9线位置剖切的剖视图。 
图10是说明本发明的第三实施方式所涉及的存储卡的制造方法的流程图。 
图11是本发明的第四实施方式所涉及的存储卡的剖视图。 
符号说明 
1、1a、1c、1d存储卡         2电路基板 
3第一半导体芯片             4密封树脂层 
5第二半导体芯片             6芯片部件 
7盖部                       8第三半导体芯片 
21上面                      22下面 
23线状凸部                  24线状凹部 
33、53、83突起              41第一密封树脂层 
42第二密封树脂层            43第三密封树脂层 
71部                        91按压工具 
92热器                      211、212、213、214电极 
221外部电极 
具体实施方式
下面，对于本发明的实施方式，边参照附图边进行说明。此外，存在对同样的元件标注同样的符号，并省略说明的情况。 
(第一实施方式) 
图1是表示本发明的第一实施方式所涉及的存储卡1的构造的俯视图。图2是将存储卡1在图1的2-2线的位置剖切的剖视图。此外，在图1中，为了容于理解存储卡1的内部构造，关于盖部7，仅通过虚线表示其轮廓，关于下面的图5、图7及图8也一样。 
在本实施方式中，存储卡1是SD存储卡(Secure Digital memory card，安全数码卡)。通常，存储卡1的长度和宽度(图1中的左右方向和上下方向的大小)及厚度(图2中的上下方向的大小)分别大于等于14.9mm且小于等于15.1mm、大于等于10.9mm且小于等于11.1mm及大于等于0.9mm且小于等于1.1mm。另外，为了方便起见，将图2中的上侧及下侧分别作为存储卡1的上侧及下侧进行说明，下面各实施方式中也是相同的。 
如图1和图2所示，存储卡1具有：大致矩形的电路基板2；夹着球形突起33(即“钉头突起”，以下简称为“突起”)安装在电路基板2的上侧的主面(以下，记作“上面”)21上的第一半导体芯片3；夹着突起53而安装在电路基板2的上面21上的第二半导体芯片5；介于第一半导体芯片3、第二半导体芯片5及电路基板2之间的密封树脂层4；使用软钎料安装在电路基板2的上面21上的电阻等的微细的芯片部件6；在电路基板2的上面21一侧覆盖第一半导体芯片3、第二半导体芯片5、密封树脂层4和芯片部件6的盖部7。此外，存储卡1在安装有第一半导体芯片3和第2半导体芯片5的位置的存储卡1的厚度大于等于0.6mm且小于等于0.8mm。 
电路基板2是相当于FR-4.5的玻璃树脂基板，厚度大于等于0.1mm且小于等于0.4mm。如图2所示，电路基板2在上面21上具有接合有第一半导体芯片3的电极211、接合有第二半导体芯片5的电极212及接合有芯片部件6的电极213。而且，电路基板2在其下面22上具有用于与外部的电子设备连接的多个外部电极221。外部电极221经由从电路基板2的下面22连通到上面21的通孔(未图示)与设在上面21上的布线电连接。 
第一半导体芯片3和第二半导体芯片5是裸芯片，其厚度分别大于等于0.05mm且小于等于0.3mm。在这里，第一半导体芯片3是存储信息的存储芯片，第二半导体芯片5是控制第一半导体芯片3的控制芯片。而且，在电路基板2上，为了不使第二半导体芯片5和第一半导体芯片3重叠，将第一半导体芯片3和第二半导体芯片5以在其间设置例如大于0mm且小于等于1mm的间隙的方式配置。此时，在存储卡1的电路基板2上，仅安装有第一半导体芯片3和第二半导体芯片5。 
第一半导体芯片3具有形成于下面的电极上的突起33，突起33通过密封树脂层4与电路基板2的电极211连接。同样，第二半导体芯片5具有形成于下面的电极上的突起53，突起53通过密封树脂层4与电路基板2的电极212连接。 
在本实施方式中，密封树脂层4是通过将例如膜状的树脂材料等非导 电性树脂膜(NCF(Non-Conductive Film))贴付在电路基板2的上面21上而形成的。在下面的说明中，将密封树脂层4中的覆盖接合于第一半导体芯片3的突起33的周围并且介于第一半导体芯片3和电路基板2之间的部位记作“第一密封树脂层41”。另外，将覆盖接合于第二半导体芯片5的突起53的周围并且介于第二半导体芯片5和电路基板2之间的部位记作“第二密封树脂层42”。而且，在存储卡1中，作为第一密封树脂层41和第二密封树脂层42是由例如NCF等同一种树脂材料连续设置而形成的。 
盖部7具有例如是由通过环氧树脂等形成的成形部件构成的、收纳第一半导体芯片3、第二半导体芯片5、密封树脂层4和芯片部件6的凹部71。盖部7通过其凹部71的开口安装在电路基板2上。 
以下，使用附图3和图4A、图4B说明本发明第一实施方式所涉及的存储卡1的制造方法。图3是说明存储卡1的制造方法的流程图，图4A和图4B是说明存储卡1的制造方法的主要步骤的剖视图。此外，图4A和图4B与图2一样，表示将存储卡1在图1的2-2线位置剖切的剖视图。 
首先，如图4A所示，在第一半导体芯片3的下面的电极上形成突起33(步骤S11)。接下来，在第二半导体芯片5的下面的电极上形成突起53(步骤S12)。 
接下来，在电路基板2的上面21上，在安装第一半导体芯片3的含有预定的多个电极211的区域(以下，记作“第一安装区域”)和安装第二半导体芯片5的含有预定的多个电极212的区域(以下，记作“第二安装区域”)上贴付NC形成密封树脂层(步骤S13)。在这里，在电路基板2的上面21的第一安装区域上贴付NCF形成第一密封树脂层41，与其并行地，在第二密封区域上贴付与第一密封树脂层41同一种类的NCF形成第二密封树脂层42。即，密封树脂层4由第一密封树脂层41和第二密封树脂层42构成。 
接下来，通过安装装置(未图示)的芯片保持部，与电路基板2的上面21相对地保持第一半导体芯片3的下面。将芯片保持部相对于电路基板2移动从而调整第一半导体芯片3的位置。由此，突起33隔着第一密封树 脂层41(密封树脂层4)与电极211相对。而且，使芯片保持部下降，从而将第一半导体芯片3安装在电路基板2上。另外，通过同样的动作将第二半导体芯片5隔着第二密封树脂层42(密封树脂层4)安装在电路基板2上。 
之后，如图4B所示，通过按压工具91将第一半导体芯片3和第二半导体芯片5隔着对应的第一密封树脂层41和第二密封树脂层42朝向电路基板2的上面21按压。同时，在将第一半导体芯片3和第二半导体芯片5向电路基板2按压的状态下，通过设在按压工具91上的加热器92进行加热。 
由此，第一半导体芯片3夹着突起33与电路基板2电连接，并且，使第一密封树脂层41固化从而将第一半导体芯片3与电路基板2接合、安装。同时，与第一半导体芯片3的安装并行进行，第二半导体芯片5夹着突起53与电路基板2电连接，并且，使第二密封树脂层42固化从而将第二半导体芯片5与电路基板2接合、安装(步骤S14)。 
接下来，如图2所示，经由附着在电路基板2的上面21的电极213上的软钎料搭载芯片部件6并进行回流焊。由此，将芯片部件6的电极和电路基板2的电极213接合、安装(步骤S15)。 
接下来，将盖部7通过其凹部71的开口安装到电路基板2上。由此，在电路基板2的上面21侧，第一半导体芯片3、第二半导体芯片5、密封树脂层4和芯片部件6被盖部7覆盖，制成存储卡1(步骤S16)。 
如上述说明，根据本实施方式的存储卡1，将第一半导体芯片3和第二半导体芯片5夹着突起33、53隔着密封树脂层4，并行同时倒装芯片安装在电路基板2上。此时，能够将第一半导体芯片3和第二半导体芯片5以在其间设置例如大于0mm且小于等于1mm的间隙的方式配置。 
这样，由于能够使第一半导体芯片3和第二半导体芯片5相接近地在沿电路基板2的上面21的方向上并列安装，因此，能够得到结构简化、小型化且薄型的存储卡1。另外，在厚度等已标准化的存储卡1中，能够避免以往由于电路基板2、第一半导体芯片2和第二半导体芯片5的层叠所 必需的过度薄型化。其结果就是，提高了对抗变形等的机械强度，能够得到具有优良可靠性的存储卡。 
另一方面，在以往的存储卡中，在将半导体芯片例如通过引线接合法安装在电路基板上的情况下，在安装后，有必要设置将半导体芯片和电线通过例如粘度较低的热固化性树脂等进行密封的步骤。因此，有在电路基板的上面侧，由于覆盖半导体芯片等所进行的热固化型树脂的成形，一体形成存储卡的盖部的情况。 
与此相对，在本实施方式中，将第一半导体芯片3和第二半导体芯片5，夹着突起33、53倒装芯片安装在电路基板2上。因此，并非必须通过粘度较低的热固化性树脂等密封第一半导体芯片3和第二半导体芯片5等，或形成盖部。其结果就是，提高了对于盖部7的材料、形成方法的选择的自由度。另外，通过对第一半导体芯片3和第二半导体芯片5进行倒装芯片安装，与引线接合法安装相比，提高了安装时的连接的可靠性。而且因为通过由第一密封树脂层41和第二密封树脂层42构成的密封树脂层4将第一半导体芯片3和第二半导体芯片5安装在电路基板上，所以，可以省略另行密封两半导体芯片和电路基板2的电连接部的步骤，并能够简化存储卡1的制造。 
另外，在本实施方式中，因为第一密封树脂层41和第二密封树脂层42都是密封树脂层4的一部分，所以，能够使用同一种树脂材料相互连续地形成。由此，能够进一步简化存储卡1的制造方法。另外，因为能够通过将例如由膜状的树脂材料构成的NCF贴付在电路基板2的上面21上而形成密封树脂层4，所以，能够进一步简化存储卡1的制造。而且，通过设为由预先形成的成形部件构成的盖部7覆盖第一半导体芯片3和第二半导体芯片5等的构造，由此，与通过热固化性树脂、热可塑性树脂等密封而形成盖部的情况相比，能够更加简化存储卡1的制造。 
另外，根据本实施方式，因为并行同时安装第一半导体芯片3和第二半导体芯片5，所以，能够避免一侧的半导体芯片的安装对另一侧半导体芯片的安装的影响，能够将两个半导体芯片良好地安装在电路基板2上。 也就是说，能够将下述问题防患于未然，即在第一半导体芯片的安装后进行第二半导体芯片的安装的情况下，因为第一半导体芯片的第一密封树脂层向第二密封树脂层挤出并固化而导致的不能安装第二半导体芯片的问题。 
此外，在本实施方式中，以第一密封树脂层41和第二密封树脂层42是通过同一种树脂材料等相互连续形成的例子进行了说明，但是不限定于此。例如，也可以分别形成第一密封树脂层41和第二密封树脂层42。也就是说，与对电路基板2的第一安装区域形成第一密封树脂层41连续地、在电路基板2的上面21的第二安装区域贴附NCF，形成第二密封树脂层42。而且，也可以通过互不相同的树脂材料形成第一密封树脂层41和第二密封树脂层42。 
另外，在本实施方式中，在通过软钎料接合对第一半导体芯片3和第二半导体芯片5进行倒装芯片安装的情况下，也可以通过以下的方法进行安装。即，在将第一半导体芯片3和第二半导体芯片5通过软钎料接合在电路基板2上以后，在电路基板2和第一半导体芯片3及第二半导体芯片5之间并行同时注入密封树脂，可密封两半导体芯片和电路基板2的电连接部。由此，因为能够在其间设置小于等于1mm的间隙地对第一半导体芯片3和第二半导体芯片5进行安装，所以能够简化构造，得到小型且薄型的存储卡1。 
(第二实施方式) 
下面使用图5和图6说明本发明的第二实施方式所涉及的存储卡。 
图5是表示本发明第二实施方式所涉及的存储卡1a的构造的俯视图。图6是将存储卡1a在图5的6-6线的位置剖切后的剖视图。 
如图5和图6所示，存储卡1a在图1和图2所示的存储卡1的构成的基础上，还具有夹着突起83而安装在电路基板2的上面21上的、例如存储芯片等的第三半导体芯片8。其他的构造与图1和图2相同，附加相同的符号进行说明。 
如图5和图6所示，在存储卡1a中，第一半导体芯片3、第二半导体 芯片5和第三半导体芯片8沿电路基板2的上面21排列成直线状。而且，配置第三半导体芯片8，其与第一半导体芯片3之间设置例如小于等于1mm的间隙。而且，第三半导体芯片8具有在其下面的电极上所形成的突起83，该第三半导体芯片8经由突起83并通过密封树脂层4与电路基板2的电极214接合(包括保持接触的状态)。在以下的内容中，将密封树脂层4中的、覆盖接合于第三半导体芯片8的突起83的周围并且介于第三半导体芯片8和电路基板2之间的部分记作“第三密封树脂层43”。 
以下，与第一实施方式同样地参照图3说明本发明第二实施方式所涉及的存储卡1a的制造方法。 
首先，在第一半导体芯片3和第二半导体芯片5的下面的电极上形成突起33、53(步骤S11)。另外，在第三半导体芯片8的下面的电极上形成突起83(步骤S12)。 
接下来，在电路基板2的上面21上，将NCF贴附在第一安装区域、第二安装区域和安装有第三半导体芯片8且包含有预定的多个电极214的区域(以下记作“第三安装区域”)从而形成密封树脂层4(步骤S13)。 
接下来，通过安装装置(未图示)的芯片保持部对第一半导体芯片3进行保持并将其安装在电路基板2上。而且，通过芯片保持部将第二半导体芯片5和第三半导体芯片8也同样地顺次安装在电路基板2上。随后，通过按压工具将第一半导体芯片3、第二半导体芯片5和第三半导体芯片8经由密封树脂层4向电路基板2的上面21按压、加热。由此，将第一半导体芯片3和第二半导体芯片5同时安装在电路基板2上(步骤S14)。而且，与此同时，将第三半导体芯片8也安装在电路基板2上。通过上述各步骤，完成了三个半导体芯片的安装。 
然后，在将芯片部件6通过软钎料接合在电路基板2上后，将盖部7安装在电路基板2上。由此，在电路基板2的上面21侧，第一半导体芯片3、第二半导体芯片5、第三半导体芯片8、密封树脂层4和芯片部件6被盖部7覆盖，制成存储卡1a(步骤S15、S16)。 
如上述说明，本实施方式的存储卡1a，为了不使第一半导体芯片3和 第二半导体芯片5重叠而在两者之间设置例如大于0mm且小于等于1mm的间隙地配置。而且，为了不使第一半导体芯片3和第三半导体芯片8重叠而两者之间设置例如大于0mm且小于等于1mm的间隙地配置。由此，与第一实施方式相同地，在简化构造的同时，能够得到小型且薄型的存储卡1a。 
另外，在本实施方式中，因为第一密封树脂层41、第二密封树脂层42和第三密封树脂层43分别是密封树脂层4的一部分，所以，能够通过同一种类的树脂材料相互连续地形成。由此，能够简化存储卡1a的制造方法。另外，因为能够通过将例如膜状的树脂材料即NCF贴附在电路基板2的上面21上而形成密封树脂层4，所以，能够进一步简化存储卡1a的制造。而且，与第一实施方式同样地，作为盖部7使用成形部件，由此，能够进一步简化存储卡1a的制造。 
另外，根据本实施方式，因为将第一半导体芯片3、第二半导体芯片5和第三半导体芯片8并行地同时安装在电路基板2上，所以，能够避免一侧的半导体芯片的安装对另一侧的半导体芯片的安装施加的影响，并能够良好地将三个半导体芯片安装在电路基板2上。 
此外，在本实施方式中，以将第一半导体芯片3、第二半导体芯片5和第三半导体芯片8配置成直线状的例子进行说明，但是并不限定于此。例如，如图7其他的例子所示的存储卡1b，也可以将第三半导体芯片8与第一半导体芯片3并排配置，并将第二半导体芯片5相对于第三半导体芯片8和第一半导体芯片3以例如大于0mm且小于等于1mm的间隙接近配置。 
另外，在本实施方式中，以将三个半导体芯片安装在电路基板上的例子进行说明，但是不限定于此。例如，也可以将四个以上的半导体芯片安装在电路基板2的上面21上。即便在这种情况下，从存储卡1a的小型化的观点出发，优选，在相互接近的半导体芯片之间设置例如大于0mm且小于等于1mm的间隙进行配置。 
(第三实施方式) 
下面使用图8和图9说明本发明的第三实施方式所涉及的存储卡。 
图8是表示本发明第三实施方式所涉及的存储卡1c的构造的俯视图。图9是表示将存储卡1c在图8的9-9线的位置剖切的剖视图。 
如图8和图9所示，存储卡1c，在图1和图2所示的存储卡1的构造基础上，还具有设在第一半导体芯片3和第二半导体芯片5之间的、沿着电路基板2的上面21的线状的凸部(以下记作“线状凸部”)23。其他的构造与图1和图2相同，在下面的说明中附加相同的符号进行说明。此外，在存储卡1c中，第一密封树脂层41和第二密封树脂层42被线状凸部23分隔而不相互连续。 
下面，使用图10说明本发明的第三实施方式所涉及的存储卡1c的制造方法。图10是说明本发明的第三实施方式所涉及的存储卡1c的制造方法的流程图。 
首先，在第一半导体芯片3和第二半导体芯片5的下面的电极上形成突起33、53(步骤S21、S22)。 
接下来，在电路基板2的上面21的第一安装区域上贴附例如NCF以形成第一密封树脂层41(步骤S23)。 
接下来，通过安装装置(未图示)的芯片保持部对第一半导体芯片3进行保持并经由第一密封树脂层41将其安装在电路基板2上。然后，通过用按压工具将第一半导体芯片3向电路基板2的上面21按压、加热，由此，将第一半导体芯片3安装在电路基板2上(步骤S24)。此时，向第一半导体芯片3的周围挤出的第一安装区域上的第一密封树脂层4，被第一半导体芯片3和第二半导体芯片5之间的线状凸部23拦住，防止其向第二安装区域扩散。通过上述的步骤，完成了第一半导体芯片3的安装。 
接下来，独立于第一密封树脂层41的形成，在第二安装区域上贴附例如NCF而形成第二密封树脂层42(步骤S25)。然后，通过芯片保持部对第二半导体芯片5进行保持并将其经由第二密封树脂层42安装在电路基板2上。进而，通过用按压工具将第二半导体芯片5向电路基板2的上面21按压、加热，由此，独立于第一半导体芯片3的安装，进行第二半导体 芯片5的对电路基板2的安装(步骤S26)。通过上述的步骤，完成第二半导体芯片5的安装。 
然后，将芯片部件6接合在电路基板2上后，在电路基板2的上面21侧，第一半导体芯片3、第二半导体芯片5、第一密封树脂层41、第二密封树脂层42和芯片部件6被盖部7覆盖。由此，制成存储卡1c(步骤S27、S28)。 
如上述说明，本实施方式的存储卡1c，通过设置在第一半导体芯片3和第二半导体芯片5之间的线状凸部23，能够防止在安装第一半导体芯片3时第一密封树脂层41向第二安装区域扩散。另外，同样地，也能够防止在安装第二半导体芯片5时第二密封树脂层42向第一安装区域扩散。因此，与第一实施方式同样地，能够避免一侧的半导体芯片的安装对另一侧的半导体芯片的安装施加的影响，能够将两个半导体芯片良好地安装在电路基板2上。 
此外，在本实施方式中，以在第一半导体芯片3安装后形成第二密封树脂层42的例子进行说明，但是，并不限定于此。例如，也可以在形成第一密封树脂层41之后形成第二密封树脂层42。这种情况下，因为第一密封树脂层41和第二密封树脂层42不是连续的，所以，能够防止在第一半导体芯片3的安装时将施加给第一密封树脂层41的热量传递到第二密封树脂层42。由此，能够防止第二密封树脂层42在第一半导体芯片3安装时、也就是说在第二半导体芯片5安装前，固化。 
另外，在本实施方式中，以将第一半导体芯片3和第二半导体芯片5分别安装到电路基板2上的例子进行说明，但是并不限定于此。例如，在线状凸部23的从电路基板2的上面21起的高度比安装后的第一半导体芯片3和第二半导体芯片5从电路基板2的上面21起的高度低的情况下，也可以用一个按压工具将第一半导体芯片3和第二半导体芯片5同时按压、安装到电路基板2上。由此，能够提高存储卡的生产效率。 
(第四实施方式) 
以下使用附图11说明本发明第四实施方式所涉及的存储卡。 
图11是表示本发明的第四实施方式所涉及的存储卡1d的构造的剖视图。 
本实施方式中的存储卡1d，具有设在第一半导体芯片3和第二半导体芯片5之间的、沿电路基板2的上面21的线状的凹部(以下记作“线状凹部”)24，在这一点上与第三实施方式不同。而且，第一密封树脂层41和第二密封树脂层42被线状凹部分隔而互不连续。另外，其他的构造与图8和图9相同，附加相同的符号进行说明。另外，存储卡1d的制造方法与第三实施方式相同，故省略说明。 
如上述说明，根据本实施方式的存储卡1d，在第一半导体芯片3的安装时被挤出的第一密封树脂层41流入到线装凹部24中，由此，与第三实施方式同样地，能够防止第一密封树脂层41向第二安装区域扩散。同样地，也能够防止第二半导体芯片5的安装时第二密封树脂层42向第一安装区域扩散。因此，与第三实施方式同样，能够避免一侧的半导体芯片的安装对另一侧半导体芯片的安装施加的影响，能够良好地将两个半导体芯片安装在电路基板2上。 
以上，说明了本发明的各个实施方式，但是本发明并不限定于上述各实施方式，能够如下所示，进行各种变更。 
也就是说，在上述各实施方式中，以将第一半导体芯片3和第二半导体芯片5作为存储芯片和控制芯片为例进行了说明，但是不限定于此。例如，也可将ASIC等其他的裸芯片作为第一半导体芯片3和第二半导体芯片5使用。而且，也可以构成为将作为第一半导体芯片3和第二半导体芯片5的两个存储芯片层叠，通过安装在电路基板2的其他区域的控制芯片对该两个存储芯片进行控制的构造。另外，作为第二半导体芯片5，也可以在电路基板2上安装存储信息和控制其他的存储芯片的存储/控制两用芯片。此时，半导体芯片可以是部分地利用了半导体功能的芯片，不必是整体都具有半导体功能的芯片。 
另外，在上述各实施方式中，以将突起33、53、83形成在第一半导体芯片3的电极上、第二半导体芯片的电极上以及第三半导体芯片的电极上的例子进行说明，但是，也可以将它们形成在电路基板2的电极211、212、214上。而且，作为突起33、53，也可以使用除球形突起以外的镀敷突起或软钎料突起等。 
另外，在上述各实施方式中，作为密封树脂层，以NCF等的贴附为例进行了说明，但是不限定于此。例如，也可以使用非导电性树脂糊剂的涂敷、各向异性导电性树脂膜或各向异性导电性树脂糊剂形成密封树脂层。 
此时，在第一实施方式和第二实施方式中，在通过树脂糊剂形成密封树脂层的情况下，在通过涂敷机在第一安装区域涂敷树脂材料后，也可以连续地在第二安装区域涂敷树脂材料。而且，也可以通过使涂敷机在第一安装区域和第二安装区域上的往复移动，在第一安装区域和第二安装区域上同时呈线状地涂敷树脂材料。 
另外，在第一实施方式中，在通过树脂糊剂形成密封树脂层的情况下，也可以通过下面的方法安装第一半导体芯片3和第二半导体芯片5。即，首先将第一半导体芯片3载置于第一密封树脂层41上，使第一密封树脂层41暂时固化到一定程度。然后，将第二半导体芯片5载置在第二密封树脂层42上，并使第二密封树脂层42暂时固化到一定程度，随后，将第一半导体芯片3和第二半导体芯片5同时向电路基板2按压并进行加热。由此，因为能够同时安装第一半导体芯片3和第二半导体芯片5，所以，能够避免一侧的半导体芯片的安装对另一侧的半导体芯片的安装施加的影响，能够良好地将两个半导体芯片安装在电路基板2上。 
另外，在上述各实施方式中，作为盖部，以通过由树脂制成的成形部件所构成的盖部为例进行了说明，但是不限定于此。例如，也可以将热可塑性树脂或热固化性树脂等通过镶嵌成形形成盖部，使得其在电路基板2的上面21上覆盖第一半导体芯片3、第二半导体芯片5等。 
此外，本发明的存储卡，除SD卡以外，也可以作为例如IC卡等其他的卡片型存储介质加以利用。 
工业上的利用可能性 
本发明在存储信息、尤其是希望小型化、薄型化的存储卡等技术领域 具有实用价值。 

Claims (12)

1.一种存储卡，其特征在于，
具有：
电路基板；
第一半导体芯片，其夹着突起安装在所述电路基板的主面上；
第二半导体芯片，在其与所述第一半导体芯片之间设置有小于等于1mm的间隙、并夹着突起安装在所述电路基板的所述主面上；
第一密封树脂层，其覆盖与所述第一半导体芯片接合的所述突起周围，并介于所述第一半导体芯片和所述电路基板之间；
第二密封树脂层，其覆盖与所述第二半导体芯片接合的所述突起周围，并介于所述第二半导体芯片和所述电路基板之间；和
盖部，其在所述电路基板的所述主面侧，覆盖所述第一半导体芯片和所述第二半导体芯片，
所述电路基板在所述第一半导体芯片和所述第二半导体芯片之间具有沿所述主面的线状的凸部或线状的凹部。
2.如权利要求1所述的存储卡，其特征在于：
所述第一密封树脂层和所述第二密封树脂层由同一种树脂材料构成，并互相连续地设置。
3.如权利要求1所述的存储卡，其特征在于：
所述盖部，由具有收纳所述第一半导体芯片和所述第二半导体芯片的凹部并且通过所述凹部的开口安装在所述电路基板上的成型部件构成。
4.如权利要求1所述的存储卡，其特征在于：
所述第一密封树脂层和所述第二密封树脂层由贴附在所述电路基板的所述主面上的膜状的树脂材料构成。
5.如权利要求1所述的存储卡，其特征在于：
所述第一半导体芯片是存储信息的存储芯片，
所述第二半导体芯片是控制所述第一半导体芯片的控制芯片。
6.如权利要求1所述的存储卡，其特征在于，
还具有：第三半导体芯片，在其与所述第一半导体芯片之间设置有小于等于1mm的间隙、并夹着突起安装在所述电路基板的所述主面上；和
第三密封树脂层，其覆盖与所述第三半导体芯片接合的所述突起周围，并介于所述第三半导体芯片和所述电路基板之间。
7.一种存储卡的制造方法，其特征在于，
包括：
a)在电路基板的主面上形成第一密封树脂层的步骤，
b)在所述电路基板的所述主面上形成第二密封树脂层的步骤，
c)将第一半导体芯片隔着所述第一密封树脂层朝向所述电路基板的所述主面按压，并夹着突起将所述第一半导体芯片电连接在所述电路基板上，并且使所述第一密封树脂层固化的步骤，
d)与所述步骤c)同时并行而与所述第一半导体芯片之间空开了1mm以下的间隙地将第二半导体芯片经由所述第二密封树脂层朝向所述电路基板的所述主面按压，并夹着突起将所述第二半导体芯片电连接在所述电路基板上，并且使所述第二密封树脂层固化的步骤，
e)在所述电路基板的所述主面侧通过盖部覆盖所述第一半导体芯片和所述第二半导体芯片的步骤。
8.如权利要求7所述的存储卡的制造方法，其特征在于：
设置间隙地配置所述第一半导体芯片和所述第二半导体芯片。
9.如权利要求7所述的存储卡的制造方法，其特征在于：
所述第一密封树脂层和所述第二密封树脂层由同一种树脂材料构成，连续或相互并行地进行所述步骤a)和所述步骤b)。
10.如权利要求7所述的存储卡的制造方法，其特征在于：
所述盖部是具有凹部的成型部件，
在所述步骤e)中，在所述盖部的所述凹部的开口中收纳所述第一半导体芯片和所述第二半导体芯片，并且通过所述凹部的开口将所述盖部安装在所述电路基板上。
11.如权利要求7所述的存储卡的制造方法，其特征在于：
在所述步骤a)中，通过将膜状的树脂材料贴附在所述电路基板的所述主面上来形成所述第一密封树脂层，
在所述步骤b)中，通过将膜状的树脂材料贴附在所述电路基板的所述主面上来形成所述第二密封树脂层。
12.如权利要求7所述的存储卡的制造方法，其特征在于：
所述第一半导体芯片是存储信息的存储芯片，
所述第二半导体芯片是控制所述第一半导体芯片的控制芯片。
CN2007800030594A 2006-02-02 2007-01-31 存储卡以及存储卡的制造方法 Expired - Fee Related CN101371268B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006025444 2006-02-02
JP025444/2006 2006-02-02
PCT/JP2007/051541 WO2007088866A1 (ja) 2006-02-02 2007-01-31 メモリカードおよびメモリカードの製造方法

Publications (2)

Publication Number Publication Date
CN101371268A CN101371268A (zh) 2009-02-18
CN101371268B true CN101371268B (zh) 2012-05-09

Family

ID=38327437

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800030594A Expired - Fee Related CN101371268B (zh) 2006-02-02 2007-01-31 存储卡以及存储卡的制造方法

Country Status (4)

Country Link
US (1) US7939923B2 (zh)
JP (1) JP4766053B2 (zh)
CN (1) CN101371268B (zh)
WO (1) WO2007088866A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101689252A (zh) * 2007-06-15 2010-03-31 松下电器产业株式会社 存储卡及其制造方法
USD794644S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794643S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD795261S1 (en) * 2009-01-07 2017-08-22 Samsung Electronics Co., Ltd. Memory device
USD794642S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794034S1 (en) * 2009-01-07 2017-08-08 Samsung Electronics Co., Ltd. Memory device
USD795262S1 (en) * 2009-01-07 2017-08-22 Samsung Electronics Co., Ltd. Memory device
USD794641S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
CN106686932B (zh) * 2015-11-05 2019-12-13 精能医学股份有限公司 植入式电子装置的防水结构
US10068854B2 (en) * 2016-10-24 2018-09-04 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10923438B2 (en) 2019-04-26 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10849235B1 (en) * 2020-05-20 2020-11-24 Tactotek Oy Method of manufacture of a structure and structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1442902A (zh) * 2002-03-01 2003-09-17 株式会社日立制作所 半导体器件及其制造方法
CN1489108A (zh) * 2002-08-27 2004-04-14 ������������ʽ���� 外观保护盒和外观保护盒组件
JP2005166891A (ja) * 2003-12-02 2005-06-23 Kingpak Technology Inc 小型メモリカード

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01299094A (ja) * 1988-05-28 1989-12-01 Ibiden Co Ltd Ｉｃカード
JPH09297535A (ja) * 1996-04-30 1997-11-18 Toshiba Chem Corp 電子タグとその製造方法
US5838551A (en) * 1996-08-01 1998-11-17 Northern Telecom Limited Electronic package carrying an electronic component and assembly of mother board and electronic package
JP3929250B2 (ja) * 2001-03-08 2007-06-13 株式会社ルネサステクノロジ 半導体装置
JP4171246B2 (ja) 2002-06-10 2008-10-22 株式会社ルネサステクノロジ メモリカードおよびその製造方法
US7601563B2 (en) * 2005-06-10 2009-10-13 Kingston Technology Corporation Small form factor molded memory card and a method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1442902A (zh) * 2002-03-01 2003-09-17 株式会社日立制作所 半导体器件及其制造方法
CN1489108A (zh) * 2002-08-27 2004-04-14 ������������ʽ���� 外观保护盒和外观保护盒组件
JP2005166891A (ja) * 2003-12-02 2005-06-23 Kingpak Technology Inc 小型メモリカード

Also Published As

Publication number Publication date
WO2007088866A1 (ja) 2007-08-09
US7939923B2 (en) 2011-05-10
JP4766053B2 (ja) 2011-09-07
CN101371268A (zh) 2009-02-18
JPWO2007088866A1 (ja) 2009-06-25
US20100193927A1 (en) 2010-08-05

Similar Documents

Publication Publication Date Title
CN101371268B (zh) 存储卡以及存储卡的制造方法
KR100870374B1 (ko) Ｉｃ카드 및 그 제조방법
US8530278B2 (en) Semiconductor device and a manufacturing method of the same
KR100281836B1 (ko) Ic 카드용 모듈, ic 카드용 모듈의 제조 방법, 혼성 집적회로 모듈 및 그 제조 방법
CN100356510C (zh) 半导体器件及其制造方法
CN101221946B (zh) 半导体封装、及***级封装模块的制造方法
CN101375299B (zh) 存储卡及存储卡的制造方法
JP5337110B2 (ja) 半導体記憶装置
CN101405752B (zh) 存储卡
CN100414703C (zh) 一种制造半导体器件的方法
EP2043028B1 (en) RFID tag and manufacturing method thereof
CN101689252A (zh) 存储卡及其制造方法
CN101290920B (zh) 半导体装置
KR20080060160A (ko) 전자 부품 내장 기판
CN101341593A (zh) 多晶片集成电路封装
CN104241256B (zh) 电子组件模块和制造该电子组件模块的方法
CN103811355A (zh) 用于叠层封装器件的模制底部填充物
CN105789064A (zh) 指纹识别芯片的封装方法及封装结构
KR20180083789A (ko) 회로 부품의 제조 방법 및 회로 부품
JP5990894B2 (ja) 半導体モジュール、半導体モジュールの製造方法及びカード
JP2008103531A (ja) 半導体装置の製造方法
CN217690132U (zh) 指纹芯片的封装单元
CN100395918C (zh) 天线暨散热金属片的装置与制造方法
CN102412241A (zh) 半导体芯片封装件及其制造方法
CN105518852A (zh) 低剖面电子封装及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120509

Termination date: 20140131