CN101359956B - Repeater - Google Patents
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
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Abstract
The invention discloses a repeater station, comprising a receiving side radio frequency processing unit, a first digital down conversion (DDC) unit, a base band processing unit, a digital up conversion (DUC) unit, a transmitting side radio frequency processing unit and a power amplification processing unit. The repeater station serves as reference signals ref which are directly produced by the base band processing unit itself for the closed-loop control to echo elimination, namely, base band digital signals serve as the reference signals ref for participating in the processing of echo elimination, thereby simplifying the processing complexity of echo elimination: on the one hand, the system complexity is greatly reduced because a hardware circuit need not be added for processing the reference signals, and on the other hand, the echo elimination effect can be guaranteed. Moreover, the base band processing unit has rather small delay.
Description
Technical Field
The invention relates to a mobile multimedia technology, in particular to a repeater.
Background
The China Mobile Multimedia Broadcasting technology alliance, abbreviated as China Mobile Multimedia Broadcasting (CMMB), is a technical system serving China Mobile Multimedia Broadcasting and aims to develop Multimedia receiving technology and equipment suitable for Mobile applications.
In the networking of digital multimedia broadcasting, the requirements of expanding the signal coverage and filling the signal coverage blind area are frequently met, for example, due to the shadow effect of wireless transmission, the blind area of wireless broadcast signals is often formed at the back or in the middle of a high-rise building; or the coverage area needs to be increased on the premise that the power of the base station is limited. For these needs, it is extremely efficient to utilize repeaters.
The repeater has the main function of transmitting a received weak user signal after amplifying the weak user signal. And a directional antenna is adopted between a receiving antenna of the repeater and the base station, so that the problem of echo interference does not exist. However, because there is coupling between the transmitting antenna and the receiving antenna of the repeater, at the receiving side of the repeater, the repeater receives the echo signal coupled back by the transmitting antenna of the repeater, so as to form strong echo interference. In addition, in the application of covering blind areas, the delay expansion of a receiver system is increased due to the delay of the repeater.
At present, most of repeaters are realized by adopting a pure analog device mode, and the suppression capability is very limited aiming at strong echo interference under the CMMB application condition. In this case, in order to suppress echo interference better, higher isolation requirements are inevitably imposed on the installation of the project, and for example, a building is required to perform spatial physical isolation, and the receiving-side antenna and the transmitting-side antenna are spaced apart from each other, which not only increases the cost of manpower and material resources, but also has an undesirable effect of suppressing echo interference.
In the prior application of chinese patent application No. CN200610147225.5 entitled "multipath echo cancellation method for digital multimedia broadcasting repeater," in order to cancel echo interference generated by coupling between the transmitting antenna and the receiving antenna of the repeater, a radio frequency signal is sent back from the transmitting antenna of the repeater as a reference signal for closed-loop control of echo cancellation, which increases the complexity of the system undoubtedly, and the cancellation effect of echo is also weakened due to the addition of a hardware circuit for processing the reference signal. Moreover, there is no limitation to repeater delay issues involved in this prior application.
Disclosure of Invention
In view of the above, the present invention is directed to a repeater, which can effectively eliminate echo interference and has a short delay time.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a repeater, comprising: the device comprises a receiving side radio frequency processing unit, a first digital down-conversion unit DDC, a baseband processing unit, a digital up-conversion unit DUC, a sending side radio frequency processing unit and a power amplification processing unit; wherein,
the receiving side radio frequency processing unit is used for receiving a user signal through a receiving antenna, receiving an echo signal coupled back from a transmitting antenna of the repeater, processing the received radio frequency signal to obtain an analog intermediate frequency signal, converting the processed analog intermediate frequency signal into a digital intermediate frequency signal, and transmitting the digital intermediate frequency signal to the first DDC;
the first DDC is used for carrying out digital down-conversion processing on the received digital intermediate-frequency signal;
the baseband processing unit comprises an echo elimination module, and the echo elimination module is used for taking a baseband digital signal of a signal output by the baseband processing unit as a reference signal, carrying out echo elimination processing on a digital intermediate frequency signal from the first DDC and then sending the processed signal to the DUC;
the DUC is used for carrying out digital up-conversion processing on the digital intermediate frequency signals from the baseband processing unit;
the transmitting side radio frequency processing unit is used for converting the digital intermediate frequency signals from the DUC into analog intermediate frequency signals and obtaining analog radio frequency signals after processing;
the power amplification processing unit is used for amplifying the analog radio-frequency signal subjected to amplification pretreatment and then transmitting the amplified analog radio-frequency signal through a transmitting antenna;
wherein the echo cancellation module comprises: training sequence generator, switch k, training sequence detector, variable delayer, echo channel estimator, FIR filter and adder;
the input end of the selector switch k is connected to the training sequence generator, and the echo cancellation module enters a channel pre-estimation stage; the switch k outputs training sequences which are sent out from the training sequence generator and are irrelevant to user signals to the training sequence detector, the variable delayer and the linear/nonlinear processing module respectively; the training sequence detector estimates the delay parameter of the echo channel according to the digital intermediate frequency signal from the first DDC and the training sequence, sends the delay parameter to the variable delayer, and sends an enabling signal for starting working to the echo channel estimator;
the echo channel estimator starts working under the trigger of the enabling signal, and the echo eliminating module enters an open loop training stage; the variable delayer delays the training sequence for the time corresponding to the delay parameter to obtain a reference signal ref _ d and then respectively sends the reference signal ref _ d to the FIR filter and the echo channel estimator; the FIR filter filters a reference signal ref _ d from the variable delayer to obtain an expected echo signal and sends the expected echo signal to the adder; the other path of input of the adder is a digital intermediate frequency signal from the first DDC, the adder subtracts the expected echo signal from the digital intermediate frequency signal from the first DDC to obtain an echo-eliminated digital intermediate frequency signal, and the echo-eliminated digital intermediate frequency signal is sent to an echo channel estimator as an echo estimation error signal e; the echo channel estimator performs channel estimation according to a reference signal ref _ d and an error signal e to obtain an estimator coefficient, adjusts an FIR filter coefficient according to the estimator coefficient, and sends a switching signal to a switch when the estimator coefficient is converged;
the input end of the selector switch is switched to the adder according to the switching signal, and the echo cancellation module enters a closed-loop training stage; the echo cancellation module begins outputting the echo cancelled digital intermediate frequency signal output by the summer to the linear/nonlinear processing module.
The repeater further comprises: a feedback processing unit, and a second DDC, wherein,
the feedback processing unit is used for processing the radio-frequency signal coupled from the transmitting antenna to obtain an analog intermediate-frequency signal, converting the processed analog intermediate-frequency signal into a digital intermediate-frequency signal and then transmitting the digital intermediate-frequency signal to the second DDC;
the second DDC is used for carrying out digital down-conversion processing on the received digital intermediate-frequency signal; the baseband processing unit further comprises a linear/nonlinear processing module, configured to perform linear and nonlinear processing on the echo-cancelled digital intermediate frequency signal according to the digital intermediate frequency signal from the second DDC, and then send the processed digital intermediate frequency signal to the DUC.
The echo cancellation module includes: training sequence generator, switch k, training sequence detector, variable delayer, echo channel estimator, FIR filter and adder;
the input end of the selector switch k is connected to the training sequence generator, and the echo cancellation module enters a channel pre-estimation stage; the switch k outputs training sequences which are sent out from the training sequence generator and are irrelevant to user signals to the training sequence detector, the variable delayer and the linear/nonlinear processing module respectively; the training sequence detector estimates the delay parameter of the echo channel according to the digital intermediate frequency signal from the first DDC and the training sequence, sends the delay parameter to the variable delayer, and sends an enabling signal for starting working to the echo channel estimator;
the echo channel estimator starts working under the trigger of the enabling signal, and the echo eliminating module enters an open loop training stage; the variable delayer delays the training sequence for the time corresponding to the delay parameter to obtain a reference signal ref _ d and then respectively sends the reference signal ref _ d to the FIR filter and the echo channel estimator; the FIR filter filters a reference signal ref _ d from the variable delayer to obtain an expected echo signal and sends the expected echo signal to the adder; the other path of input of the adder is a digital intermediate frequency signal from the first DDC, the adder subtracts the expected echo signal from the digital intermediate frequency signal from the first DDC to obtain an echo-eliminated digital intermediate frequency signal, and the echo-eliminated digital intermediate frequency signal is sent to an echo channel estimator as an echo estimation error signal e; the echo channel estimator performs channel estimation according to a reference signal ref _ d and an error signal e to obtain an estimator coefficient, adjusts an FIR filter coefficient according to the estimator coefficient, and sends a switching signal to a switch when the estimator coefficient is converged;
the input end of the selector switch is switched to the adder according to the switching signal, and the echo cancellation module enters a closed-loop training stage; the echo cancellation module begins outputting the echo cancelled digital intermediate frequency signal output by the summer to the linear/nonlinear processing module.
And the training sequence detector is used for estimating the delay parameters of all paths of the echo channel according to the digital intermediate frequency signal from the first DDC and the training sequence, and estimating the delay parameters of the echo channel according to the estimated delay parameters of all paths of the echo channel.
And the training sequence detector is used for taking the delay parameter of the first path of the echo channel as the estimated delay parameter of the echo channel.
The echo channel estimator is used for calculating the sum of absolute values of all estimator coefficients obtained by performing echo channel estimation for the time after the echo channel estimation for the time is performed, and judging that the estimator coefficients are converged when the variation amplitude of the sum of absolute values calculated in a preset time period from the current time is within a preset amplitude or the variation amplitude of the sum of absolute values calculated in a preset number of times before the echo channel estimation for the time is within a preset amplitude and the sum of absolute values is not zero.
The echo channel estimator includes: a minimum mean square error estimator, and/or a recursive minimum variance estimator.
The linear/nonlinear processing module comprises an 18-order FIR filter for linear processing.
The linear/nonlinear processing module comprises a 9-order multiply-accumulator for nonlinear processing, or a structure adopting a lookup table method, or a structure based on a wiener model method, or a structure based on a hammerstein model method.
The baseband processing unit is realized by adopting a programmable logic device.
The programmable logic device is a field programmable gate array FPGA or a complex programmable logic device CPLD.
The receiving side radio frequency processing unit includes: a low pass filter LPF, a low noise amplifier LNA, a radio frequency filter RF SW, a band pass filter BPF and its corresponding second voltage controlled tuner UHF2Tuning, an attenuator ATT, a mixer, an intermediate frequency filter SAW, an amplifier AMP, a voltage controlled automatic gain control VGC and an analog to digital converter a/D.
The receiving side radio frequency processing unit further includes: a high pass filter HPF and a corresponding first voltage controlled tuner UHF1 Tuning.
The transmitting side radio frequency processing unit includes: digital-to-analog converter D/A, baseband low-pass filter BB LPF, mixer, band-pass filter BPF, attenuator ATT and amplification preprocessor PRE _ PA.
The feedback processing unit mainly comprises a mixer, an amplifier AMP, an intermediate frequency filter SAW and an analog-to-digital converter A/D.
It can be seen from the above technical solutions that the reference signal ref used as the closed-loop control for echo cancellation in the present invention is directly generated by the baseband processing unit itself, that is, the baseband digital signal is used as the reference signal ref to participate in the echo cancellation processing, which simplifies the processing complexity of echo cancellation: on one hand, the system complexity is greatly reduced because a hardware circuit for processing the reference signal is not required to be added, and on the other hand, the effect of eliminating the echo is also ensured. Moreover, from the above implementation, the delay of the baseband processing unit of the present invention is rather small.
Drawings
FIG. 1 is a schematic diagram of the structure of a repeater according to the present invention;
FIG. 2 is a block diagram of a baseband processing unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure of a receiving side RF processing unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a component structure of an embodiment of a transmitting-side RF processing unit according to the present invention;
FIG. 5 is a schematic diagram of the structure of a feedback processing unit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an echo cancellation module in a baseband processing unit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
FIG. 1 is a schematic diagram of a composition structure of a repeater according to the present invention, as shown in FIG. 1, the repeater according to the present invention includes: the device comprises a receiving side radio frequency processing unit, a first digital down-conversion unit (DDC), a baseband processing unit, a digital up-conversion unit (DUC), a transmitting side radio frequency processing unit, a power amplification processing unit, a second DDC and a feedback processing unit. Wherein,
the receiving side radio frequency processing unit is used for receiving a user signal such as a radio frequency signal transmitted by a base station, a transmitting tower or a transmitting station through a receiving antenna, receiving an echo signal (radio frequency signal) coupled back from a transmitting antenna of the repeater, performing filtering, amplification, frequency mixing, attenuation and other processing on the received radio frequency signal to obtain an analog intermediate frequency signal, converting the processed analog intermediate frequency signal into a digital intermediate frequency signal, and transmitting the digital intermediate frequency signal to the first DDC.
And the first DDC is used for carrying out digital down-conversion processing on the received digital intermediate frequency signal. The specific implementation of DDC is well known to those skilled in the art and will not be described further herein.
A baseband processing unit, configured to perform echo cancellation processing on the digital intermediate frequency signal from the first DDC by using a baseband digital signal as a reference signal ref; according to the digital intermediate frequency signal from the second DDC, the echo-cancelled digital intermediate frequency signal is subjected to linear/nonlinear processing and then transmitted to the DUC.
And the DUC is used for performing digital up-conversion processing on the digital intermediate frequency signal from the baseband processing unit. The specific implementation of a DUC is well known to those skilled in the art and will not be described in detail herein.
And the transmitting side radio frequency processing unit is used for converting the digital intermediate frequency signals from the DUC into analog intermediate frequency signals, and obtaining analog radio frequency signals after frequency mixing, attenuation, amplification pretreatment and the like.
The power amplification processing unit is configured to amplify the analog radio frequency signal after the amplification preprocessing and transmit the amplified analog radio frequency signal through a transmitting antenna, and the specific implementation of the power amplification processing unit belongs to the technologies known by those skilled in the art and will not be described in detail here.
The feedback processing unit is used for performing frequency mixing, amplification, filtering and other processing on the radio-frequency signal coupled from the transmitting antenna to obtain an analog intermediate-frequency signal, converting the processed analog intermediate-frequency signal into a digital intermediate-frequency signal and then transmitting the digital intermediate-frequency signal to the second DDC; and the second DDC is used for carrying out digital down-conversion processing on the received digital intermediate frequency signal.
In fig. 1, the baseband processing unit includes an echo cancellation module and a linear/nonlinear processing module, as shown in fig. 2, fig. 2 is a schematic diagram of a composition structure of an embodiment of the baseband processing unit of the present invention. Wherein,
the echo cancellation module takes an output signal of the echo cancellation module as a reference signal ref and is used for carrying out echo processing on the digital intermediate frequency signal from the first DDC according to the reference signal ref;
and the linear/nonlinear processing module is used for carrying out linear/nonlinear processing on the digital intermediate frequency signal subjected to the echo cancellation processing according to the digital intermediate frequency signal from the second DDC and then sending the processed digital intermediate frequency signal to the DUC. The linear processing part can preferably adopt a filter with 18-order FIR structure, the delay time of which is less than 1.8 microseconds (us), or, under the condition of allowing the delay time to be increased, the higher the order is, the better the linear processing performance is; the nonlinear processing part can be realized by adopting a 9-order multiply-accumulate device, the time delay of which is less than 0.6us, or the structure of the existing method adopting a lookup table, or the structure of the existing method completely based on a wiener model, a hammerstein model and the like.
The baseband processing unit may be implemented using a programmable logic device, such as a Field Programmable Gate Array (FPGA), or a Complex Programmable Logic Device (CPLD).
From the realization of the baseband processing unit of the present invention, the reference signal ref of the present invention, which is used as the closed-loop control for echo cancellation, is directly generated by the baseband processing unit itself, i.e. the baseband digital signal is used as the reference signal ref to participate in the echo cancellation processing, thereby simplifying the processing complexity of echo cancellation: on one hand, the system complexity is greatly reduced because a hardware circuit for processing the reference signal is not required to be added, and on the other hand, the effect of eliminating the echo is also ensured. Moreover, from the above implementation, the delay of the baseband processing unit of the present invention is rather small.
It should be noted that the linear/nonlinear module shown in fig. 1 may be omitted to improve the utilization rate of the power amplifier, and the feedback processing unit and the second DDC may also be omitted, in which case, the baseband processing unit may directly send the processed signal to the DUC after the echo cancellation processing is completed.
The following describes the components of the repeater of the present invention in detail.
Fig. 3 is a schematic structural diagram of an embodiment of a receiving-side RF processing unit according to the present invention, as shown in fig. 3, when an RF signal from a receiving antenna is a single frequency signal, such as a repeater is applied in a CMMB, the receiving-side RF processing unit may be composed of a Low Pass Filter (LPF), a Low Noise Amplifier (LNA), an RF filter (RF SW), a Band Pass Filter (BPF) and a second voltage-controlled tuner (UHF2 Tuning), an Attenuator (ATT), a mixer, an intermediate frequency filter (SAW), an Amplifier (AMP), a voltage-controlled automatic gain control (VGC), and an analog-to-digital converter (a/D), and its working process is as follows: the radio frequency signal from the receiving antenna enters BPF after being processed by LBP, LNA1 and RF SW1 in sequence, and then is processed by UHF2Tuning, RF SW2, LNA2 and ATT in sequence; the radio frequency signal after ATT is subjected to two-stage mixing (SAW 1 is arranged between the two-stage mixing) to obtain an intermediate frequency analog signal, the intermediate frequency analog signal is subjected to AMP, SAW2 and VGC in sequence to obtain an analog intermediate frequency voltage signal, and the analog intermediate frequency voltage signal is subjected to A/D to obtain a digital intermediate frequency signal.
When the rf signal from the receiving antenna is a full frequency signal, the receiving side rf processing unit includes a High Pass Filter (HPF) and a corresponding first voltage control tuner (UHF1Tuning), in addition to the above-mentioned parts, the HPF and the corresponding UHF1Tuning are sequentially connected in series and are connected in parallel with the BPF and the corresponding UHF2Tuning, which are sequentially connected in series, and fig. 3 illustrates an example in which the rf signal from the receiving antenna is a full frequency signal.
It should be noted that the specific implementation of each part constituting the receiving-side rf processing unit belongs to the conventional technical means of those skilled in the art, and is not described herein again.
Fig. 4 is a schematic structural diagram of a transmitting side rf processing unit according to an embodiment of the present invention, and as shown in fig. 4, the transmitting side rf processing unit includes: digital-to-analog converter (D/A), baseband low pass filter (BBLPF), mixer, BPF, ATT and amplify the preprocessor (PRE _ PA), its working process roughly includes: the digital intermediate frequency signal from the DUC is converted into an analog intermediate frequency signal, and the analog intermediate frequency signal is obtained after the digital intermediate frequency signal is processed by BBLPF, two stages of mixers (BPF is arranged between the two stages of mixers), ATT and PRE _ PA in sequence. The number of BB LPFs depends on the number of D/a converted channels, and only needs to satisfy the requirement of performing BB LPF processing on each channel of analog intermediate frequency signal, and fig. 4 illustrates that the number of BB LPFs is 2.
It should be noted that the specific implementation of each part constituting the receiving-side rf processing unit belongs to the conventional technical means of those skilled in the art, and is not described herein again.
Fig. 5 is a schematic diagram of a composition structure of an embodiment of the feedback processing unit of the present invention, and as shown in fig. 5, the feedback processing unit mainly includes a mixer, an AMP, a SAW, and an a/D, and its working process is approximately: the method comprises the steps of mixing radio frequency signals coupled from a sending antenna, then carrying out AMP, SAW and AMP in sequence to obtain analog intermediate frequency signals, and finally converting the processed analog intermediate frequency signals into digital intermediate frequency signals.
It should be noted that the specific implementation of each part constituting the receiving-side rf processing unit belongs to the conventional technical means of those skilled in the art, and is not described herein again.
Fig. 6 is a schematic structural diagram of an echo cancellation module in a baseband processing unit according to an embodiment of the present invention, where as shown in fig. 6, the echo cancellation module includes: training sequence generator, change over switch k, training sequence detector, variable delayer, echo channel estimator, FIR filter and adder, in addition, echo cancellation module can also include: and AGC. The working principle of the echo cancellation module is as follows:
firstly, the input end of a selector switch k is connected to a training sequence generator, and at the moment, an echo cancellation module enters a channel pre-estimation stage; the selector switch k divides the training sequence which is sent from the training sequence generator and is irrelevant to the user signal into three paths: one path of the signal is output to a linear/nonlinear processing module, the other path of the signal is output to a training sequence detector, and the other path of the signal is output to a variable delayer; the training sequence detector estimates a delay parameter of an echo channel according to a digital intermediate frequency signal from the first DDC and a training sequence from a selector switch k, sends the delay parameter to the variable delayer, and sends an enabling signal for starting working to the echo channel estimator; the digital intermediate frequency signal from the first DDC is a sum of a user signal and an echo signal corresponding to the training sequence output to the outside.
Then, the echo channel estimator starts working under the trigger of the enabling signal, and the echo eliminating module enters an open loop training stage; the variable delayer delays the training sequence for the time corresponding to the delay parameter to obtain a reference signal ref _ d and then respectively sends the reference signal ref _ d to the FIR filter and the echo channel estimator; the FIR filter filters a reference signal ref _ d from the variable delayer to obtain an expected echo signal and sends the expected echo signal to the adder; the other path of input of the adder is a digital intermediate frequency signal from the first DDC, the adder subtracts the expected echo signal from the digital intermediate frequency signal from the first DDC to obtain an echo-eliminated digital intermediate frequency signal, and the digital intermediate frequency signal from the first DDC mainly comprises a user signal and also comprises a weak residual echo signal, so that the adder sends the echo-eliminated digital intermediate frequency signal to an echo channel estimator as an echo estimation error signal e; the echo channel estimator performs channel estimation according to a reference signal ref _ d and an error signal e to obtain an estimator coefficient, adjusts an FIR filter coefficient according to the estimator coefficient, and sends a switching signal to a switch when the estimator coefficient is converged;
the input end of the selector switch is switched to the adder according to the switching signal, and at the moment, the echo elimination module enters a closed-loop training stage; the echo cancellation module starts to output the echo-cancelled digital intermediate frequency signal output by the adder to the outside. Thereafter, the adder replaces the training sequence generator in the second stage, and the signal output from the adder is sent to the corresponding module by the switch for echo cancellation processing.
Preferably, the midamble detector shown in fig. 6 is configured to estimate the delay parameter of each path of the echo channel according to the digital if signal from the first DDC and the midamble, and to estimate the delay parameter of the echo channel according to the estimated delay parameter of each path of the echo channel.
When the delay parameter of the echo channel is estimated according to the estimated delay parameter of each path of the echo channel, various modes can be adopted. For example: the delay parameter of the signal with the first power not lower than a certain preset power threshold value can be used as the delay parameter of the echo channel; the delay parameter of the first path can also be used as the delay parameter of the echo channel.
The echo channel estimator shown in fig. 6 has a function of determining whether the estimator coefficient converges, and transmitting a switching signal to the switch at the time of convergence. In practical applications, the function may be implemented by a separate module, or the function may be implemented in a control module. There are many methods for determining whether the estimator coefficients converge, and for example, the following method may be used:
and calculating the sum of absolute values of all estimator coefficients obtained by performing the echo channel estimation at the current time once after the echo channel estimation is performed, wherein when the variation amplitude of the sum of the absolute values calculated in a preset time period from the current time to the previous time is within a preset amplitude or the variation amplitude of the sum of the absolute values calculated in a preset time number from the current echo channel estimation to the previous time is within a preset amplitude, and when the sum of the absolute values is not zero, the estimator coefficients are judged to be converged.
Further, an AGC may be further included in fig. 6, which is disposed between the adder and the switch, and is used for implementing gain control on the output signal of the adder.
The training sequence irrelevant to the user signal can be: PN sequences, CAZAC sequences, etc. The echo channel estimator of the present invention may be: a Least Mean Square (LMS) estimator, and/or a Recursive Least Square (RLS) estimator, etc.
In the echo cancellation module provided by the invention, firstly, the input end of a selector switch k is connected to a training sequence generator, a training sequence detector estimates a delay parameter of an echo channel according to a training sequence which is sent by the training sequence generator and is irrelevant to a user signal, then an echo channel estimator starts to work, estimates the echo channel according to a digital intermediate frequency signal from a first DDC, the training sequence and the delay parameter, adjusts an estimator coefficient, when the estimator coefficient is converged, the input end of the selector switch is switched to an adder, and then the echo cancellation module stops outputting the training sequence outwards and starts to output the user signal subjected to echo cancellation outwards.
The input end of the switch is always connected with the training sequence generator before the coefficient of the estimator converges, so that the training sequence signal which is not interfered by the echo is always output from the echo cancellation module, the echo cancellation module is in a stable open loop state, and the radio frequency link is not saturated due to positive feedback, thereby ensuring the coefficient of the estimator of the echo channel estimator to converge quickly and enabling the echo cancellation module to enter a stable working state as soon as possible. And after the estimator coefficient is converged, the input end of the switch is switched to the adder, and at the moment, the echo cancellation module does not output the training sequence outwards any more, so that on one hand, data resources are saved, and on the other hand, the interference caused by the transmission of the training sequence to the user signal is avoided.
In addition, the echo elimination module of the invention uses a variable delayer, the delay parameter of which can be set according to the result of the echo channel pre-estimation, which can ensure that the echo elimination window covers the time range of the echo multipath signal as much as possible, thereby eliminating the echo signal as much as possible.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A repeater, comprising: the device comprises a receiving side radio frequency processing unit, a first digital down-conversion unit DDC, a baseband processing unit, a digital up-conversion unit DUC, a sending side radio frequency processing unit and a power amplification processing unit; wherein,
the receiving side radio frequency processing unit is used for receiving a user signal through a receiving antenna, receiving an echo signal coupled back from a transmitting antenna of the repeater, processing the received radio frequency signal to obtain an analog intermediate frequency signal, converting the processed analog intermediate frequency signal into a digital intermediate frequency signal, and transmitting the digital intermediate frequency signal to the first DDC;
the first DDC is used for carrying out digital down-conversion processing on the received digital intermediate-frequency signal;
the baseband processing unit comprises an echo elimination module, and the echo elimination module is used for taking a baseband digital signal of a signal output by the baseband processing unit as a reference signal, carrying out echo elimination processing on a digital intermediate frequency signal from the first DDC and then sending the processed signal to the DUC;
the DUC is used for carrying out digital up-conversion processing on the digital intermediate frequency signals from the baseband processing unit;
the transmitting side radio frequency processing unit is used for converting the digital intermediate frequency signals from the DUC into analog intermediate frequency signals and obtaining analog radio frequency signals after processing;
the power amplification processing unit is used for amplifying the analog radio-frequency signal subjected to amplification pretreatment and then transmitting the amplified analog radio-frequency signal through a transmitting antenna;
wherein the echo cancellation module comprises: training sequence generator, switch k, training sequence detector, variable delayer, echo channel estimator, FIR filter and adder;
the input end of the selector switch k is connected to the training sequence generator, and the echo cancellation module enters a channel pre-estimation stage; the switch k outputs training sequences which are sent out from the training sequence generator and are irrelevant to user signals to the training sequence detector, the variable delayer and the linear/nonlinear processing module respectively; the training sequence detector estimates the delay parameter of the echo channel according to the digital intermediate frequency signal from the first DDC and the training sequence, sends the delay parameter to the variable delayer, and sends an enabling signal for starting working to the echo channel estimator;
the echo channel estimator starts working under the trigger of the enabling signal, and the echo eliminating module enters an open loop training stage; the variable delayer delays the training sequence for the time corresponding to the delay parameter to obtain a reference signal ref _ d and then respectively sends the reference signal ref _ d to the FIR filter and the echo channel estimator; the FIR filter filters a reference signal ref _ d from the variable delayer to obtain an expected echo signal and sends the expected echo signal to the adder; the other path of input of the adder is a digital intermediate frequency signal from the first DDC, the adder subtracts the expected echo signal from the digital intermediate frequency signal from the first DDC to obtain an echo-eliminated digital intermediate frequency signal, and the echo-eliminated digital intermediate frequency signal is sent to an echo channel estimator as an echo estimation error signal e; the echo channel estimator performs channel estimation according to a reference signal ref _ d and an error signal e to obtain an estimator coefficient, adjusts an FIR filter coefficient according to the estimator coefficient, and sends a switching signal to a switch when the estimator coefficient is converged;
the input end of the selector switch is switched to the adder according to the switching signal, and the echo cancellation module enters a closed-loop training stage; the echo cancellation module begins outputting the echo cancelled digital intermediate frequency signal output by the summer to the linear/nonlinear processing module.
2. The repeater according to claim 1, further comprising: a feedback processing unit, and a second DDC, wherein,
the feedback processing unit is used for processing the radio-frequency signal coupled from the transmitting antenna to obtain an analog intermediate-frequency signal, converting the processed analog intermediate-frequency signal into a digital intermediate-frequency signal and then transmitting the digital intermediate-frequency signal to the second DDC;
the second DDC is used for carrying out digital down-conversion processing on the received digital intermediate-frequency signal;
the baseband processing unit further comprises a linear/nonlinear processing module, configured to perform linear and nonlinear processing on the echo-cancelled digital intermediate frequency signal according to the digital intermediate frequency signal from the second DDC, and then send the processed digital intermediate frequency signal to the DUC.
3. The repeater according to claim 1, wherein the training sequence detector is configured to estimate the delay parameter of each path of the echo channel according to the digital intermediate frequency signal from the first DDC and the training sequence, and to estimate the delay parameter of the echo channel according to the estimated delay parameter of each path of the echo channel.
4. The repeater according to claim 1, wherein the training sequence detector is configured to use the delay parameter of the first path of the echo channel as the delay parameter of the estimated echo channel.
5. The repeater according to claim 1, wherein the echo channel estimator is configured to calculate a sum of absolute values of all estimator coefficients obtained by performing echo channel estimation this time once after performing echo channel estimation this time, and determine that the estimator coefficients converge when a variation range of a sum of absolute values calculated within a preset time period from a current time point onward is within a preset range or a variation range of a sum of absolute values calculated within a preset number of times onward from echo channel estimation this time is within a preset range, and the sum of absolute values is not zero.
6. The repeater according to claim 1, wherein the echo channel estimator comprises: a minimum mean square error estimator, and/or a recursive minimum variance estimator.
7. The repeater according to claim 2, wherein the linear/non-linear processing module comprises an 18-order FIR structure filter for linear processing.
8. The repeater according to claim 2, wherein the linear/nonlinear processing module comprises a multiply-accumulate unit of 9 th order for nonlinear processing, or a structure of a method using a lookup table, or a structure of a method based on wiener model, or a structure of a method based on hammerstein model.
9. The repeater according to claim 1 or 2, wherein the baseband processing unit is implemented by a programmable logic device.
10. The repeater according to claim 9, wherein the programmable logic device is a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).
11. The repeater according to claim 1 or 2, wherein the receiving side radio frequency processing unit comprises: a low pass filter LPF, a low noise amplifier LNA, a radio frequency filter RF SW, a band pass filter BPF and its corresponding second voltage controlled tuner UHF2Tuning, an attenuator ATT, a mixer, an intermediate frequency filter SAW, an amplifier AMP, a voltage controlled automatic gain control VGC and an analog to digital converter a/D.
12. The repeater according to claim 1 or 2, wherein the receiving side radio frequency processing unit further comprises: a high pass filter HPF and a corresponding first voltage controlled tuner UHF1 Tuning.
13. The repeater according to claim 1 or 2, wherein the transmitting side radio frequency processing unit comprises: digital-to-analog converter D/A, baseband low-pass filter BB LPF, mixer, band-pass filter BPF, attenuator ATT and amplification preprocessor PRE _ PA.
14. The repeater according to claim 2, wherein the feedback processing unit mainly comprises a mixer, an amplifier AMP, an intermediate frequency filter SAW and an analog-to-digital converter A/D.
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| CN101820699B (en) * | 2009-02-27 | 2013-02-20 | 京信通信***（中国）有限公司 | Wideband signal digital frequency selecting system with self-adaptive bandwidth adjustment and signal processing method |
| US8583035B2 (en) * | 2010-02-02 | 2013-11-12 | Blackberry Limited | Multiple input multiple output user equipment radio frequency assistant system |
| US8744340B2 (en) * | 2010-09-13 | 2014-06-03 | Qualcomm Incorporated | Method and apparatus of obtaining timing in a repeater |
| CN102792742B (en) * | 2011-10-31 | 2016-05-25 | 苏州全波通信技术有限公司 | The self-adaptation control method of repeater output signal and device thereof and system |
| CN103856423B (en) * | 2012-11-29 | 2017-11-17 | 华为技术有限公司 | Communication terminal and self interference signal clearing method |
| CN103916148B (en) * | 2013-01-05 | 2016-08-03 | 华为技术有限公司 | A kind of adaptive RF Interference Cancellation device, method, receiver and communication system |
| CN103199880A (en) * | 2013-02-28 | 2013-07-10 | 北京国泰半球科技有限公司 | Self-adaptation zero-setting antenna system |
| CN103856424B (en) * | 2014-03-04 | 2017-01-04 | 华普特科技（深圳）股份有限公司 | A kind of repeater echo interference elimination method and device |
| EP3288182B1 (en) * | 2016-08-25 | 2020-07-01 | Cisco Technology, Inc. | System architecture for supporting digital pre-distortion and full duplex in cable network environments |
| CN106656283A (en) * | 2016-12-21 | 2017-05-10 | 三维通信股份有限公司 | Method for realizing intelligent distributed antenna |
| CN109245815B (en) * | 2018-08-02 | 2021-08-10 | 中山大学 | Method and system for determining transmitting signal of repeater |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996783A (en) * | 2006-12-14 | 2007-07-11 | 上海交通大学 | Multi-path echo elimination method of the digital multi-media broadcast direct broadcast station |
| CN201087945Y (en) * | 2007-09-29 | 2008-07-16 | 上海广电（集团）有限公司中央研究院 | Device for eliminating multipath echo |
-
2008
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996783A (en) * | 2006-12-14 | 2007-07-11 | 上海交通大学 | Multi-path echo elimination method of the digital multi-media broadcast direct broadcast station |
| CN201087945Y (en) * | 2007-09-29 | 2008-07-16 | 上海广电（集团）有限公司中央研究院 | Device for eliminating multipath echo |
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