CN101359136A - TFT LCD array substrate structure and method for manufacturing same - Google Patents
TFT LCD array substrate structure and method for manufacturing same Download PDFInfo
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- CN101359136A CN101359136A CNA2007101197835A CN200710119783A CN101359136A CN 101359136 A CN101359136 A CN 101359136A CN A2007101197835 A CNA2007101197835 A CN A2007101197835A CN 200710119783 A CN200710119783 A CN 200710119783A CN 101359136 A CN101359136 A CN 101359136A
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Abstract
The invention discloses a TFT LCD array substrate structure, comprising a substrate, gate electrode scan lines arranged in a horizontal folded line form, a gate electrode insulation layer, data scan lines which is arranged in a vertical folded line form and defines a polygon pixel unit together with the gate electrode scan lines arranged in a horizontal folded line form, a film transistor formed at the overlapped arrangement position between the gate electrode scan lines and the data scan lines which serve as the source electrodes, a passivation layer, and a pixel electrode which is connected with a drain electrode of the film transistor. The invention also discloses a manufacturing method of the TFT LCD array substrate structure. By arranging the data lines on the gate electrode scan lines to serve as source electrodes, the invention eliminates the metal gate electrodes and increases the aperture ratio to the maximum extent; the non-horizontal arranged gate electrode scan lines and the public electrodes are used as the public composing structure for the three adjacent pixels so as to make full use of the substrate space and enable the number of pixels to reach the maximum.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD (TFT-LCD), relate in particular to TFT-LCD array substrate structure and manufacture method thereof.
Background technology
In flat panel display, therefore the characteristics that TFT-LCD has is low in energy consumption, manufacturing cost is relatively low and radiationless have occupied leading position in flat panel display market.The TFT-LCD device is formed box by array glass substrate and color film glass substrate.Shown in Fig. 1, Fig. 1 a and Fig. 1 b, be the single pixel vertical view of non-crystalline silicon tft (thin film transistor (TFT)) structure of present main flow and the schematic cross-section at A-A and B-B position thereof.It is the bottom grating structure that adopts the corrosion of back of the body raceway groove.Shown in Fig. 1, Fig. 1 a and Fig. 1 b, this array structure comprises: one group of gate electrode sweep trace 1 and one group of vertical with it data scanning line 5, adjacent gate electrode sweep trace and data scanning line have defined pixel region.Each pixel packets contains a TFT switching device, pixel electrode 10 and part public electrode 11.The TFT device is made up of gate electrode 2, grid electrode insulating layer 4, semiconductor active layer 3 and source electrode 6 and drain electrode 7, as Fig. 1 b.Passivation layer 8 covers on the above-mentioned each several part, and forms transpassivation layer via hole 9 above drain electrode 7.Pixel electrode 10 is connected with the drain electrode 7 of TFT by the via hole 9 of passivation layer.Pixel electrode 10 parts and gate electrode sweep trace 1 form memory capacitance 13 together.In order further to reduce the light leak in the pixel behind the box, the both sides that are parallel to data line in pixel form shield bars 12.This kind TFT device can lower the photic leakage current in the raceway groove.Shield bars uses and the gate electrode same material, finishes making in same Mask (photoetching) operation.
5-Mask (photoetching) technology is the typical process technology of making TFT at present.Its main technique step was divided into for five steps:
1, forms gate electrode and lead-in wire thereof;
2, form grid electrode insulating layer and amorphous silicon semiconductor layer;
3, form source electrode, drain electrode and data lead;
4, form the passivation protection layer;
5, form pixel electrode.
In the above-mentioned technology, each step comprises that all thin film deposition, exposure and pattern form and corrode three main technique.Aforesaid is a kind of typical 5-Mask technology.By changing Mask design and processes flow process, other 5-Mask technology is arranged also.Because the existence of gate electrode and adopted pixel central authorities " H " type public electrode structure is so aperture opening ratio descends to some extent.And traditional TFT pixel is a rectangular configuration, and this just makes that under certain area, the utilization factor of pixel is limited, and number of pixels is restricted.
Summary of the invention
The objective of the invention is in order to overcome the defective of prior art, a kind of TFT LCD array base-plate structure and manufacture method thereof are provided, by using the cellular TFT-LCD board structure of hexagon, data line is arranged in serves as the source electrode on the gate electrode sweep trace, cancel metal gate electrode, increased aperture opening ratio to the full extent; Using non-gate electrode sweep trace of laterally arranging and public electrode is the public composition structures of adjacent three pixels, can make full use of substrate space, makes number of pixels reach maximum.
To achieve these goals, the invention provides a kind of TFT LCD array base-plate structure, comprising:
One substrate;
The gate electrode sweep trace that one transverse crease lines type is arranged is formed on the described substrate;
One grid electrode insulating layer is formed on described gate electrode sweep trace and gate electrode and the substrate;
The data scanning line that one longitudinal broken line type is arranged is formed on the described grid electrode insulating layer, and the common definition of the gate electrode sweep trace of arranging with described transverse crease lines type one polygonal pixel cell;
One thin film transistor (TFT) is formed on the overlapping place that arranges of described gate electrode sweep trace and data scanning line, and the data scanning line serves as the source electrode;
One passivation layer is formed on described grid electrode insulating layer, data scanning line and the thin film transistor (TFT), and forms passivation layer via hole or groove on the drain electrode of described thin film transistor (TFT);
One pixel electrode is formed on the described passivation layer, and is connected with the drain electrode of described thin film transistor (TFT) by described passivation layer via hole or groove.
In the such scheme, comprise that further the public electrode of a transverse crease lines type is formed on the substrate, be positioned at a side of described polygonal pixel cell, the gate electrode sweep trace of arranging with described transverse crease lines type is relative status.A further described pixel electrode part is positioned on the public electrode, forms memory capacitance.Further described polygonal pixel cell is specially hexagonal pixel cell.The drain electrode of described gate electrode sweep trace, data scanning line, thin film transistor (TFT) or public electrode are individual layer or the lamination layer structure that one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel etc. or combination in any constitute.The material of described grid electrode insulating layer is silicon nitride, silicon dioxide or aluminium oxide etc.The material of described pixel electrode is tin indium oxide, indium zinc oxide or aluminum zinc oxide etc.
To achieve these goals, the invention provides a kind of manufacture method of TFT LCD array base-plate structure, comprising:
In the above-mentioned manufacture method, when forming the gate electrode sweep trace that the transverse crease lines type arranges in the described step 1, form the public electrode that the transverse crease lines type is arranged, the public electrode that gate electrode sweep trace that the transverse crease lines type arranges and transverse crease lines type are arranged lays respectively at the both sides of described polygon pixel cell.A pixel electrode part that forms in the described step 5 is positioned on the public electrode, forms memory capacitance.Definition one polygonal pixel cell is specially definition one hexagonal pixel cell in the described step 3.
Compare with prior art, the present invention adopts and forms the cellular dot structure of hexagon jointly by gate electrode sweep trace, public electrode and data scanning line.She Ji sharpest edges are like this, data line is arranged in serves as the source electrode on the gate electrode sweep trace, have cancelled metal gate electrode, can greatly increase aperture opening ratio; Simultaneously, it is the public composition structures of adjacent three pixels that the present invention uses non-gate electrode sweep trace of laterally arranging and public electrode, can make full use of substrate space, makes number of pixels reach maximum.
Description of drawings
Fig. 1 is TFT LCD device of the prior art single pixel vertical view on array base palte;
Fig. 1 a is an A-A partial cross sectional view among Fig. 1;
Fig. 1 b is a B-B partial cross sectional view among Fig. 1;
Fig. 2 is TFT LCD device of the present invention single pixel vertical view on array base palte;
Fig. 2 a is a C-C partial cross sectional view among Fig. 2;
Fig. 2 b is a D-D partial cross sectional view among Fig. 2;
Fig. 2 c is an E-E partial cross sectional view among Fig. 2.
Mark among the figure: 1, gate electrode sweep trace; 2, gate electrode; 3, active layer; 4, grid electrode insulating layer; 5, data scanning line; 6, source electrode; 7, drain electrode; 8, passivation layer; 9, passivation layer via hole; 10, pixel electrode; 11, public electrode; 12, shield bars; 13, memory capacitance.
Embodiment
Below in conjunction with description of drawings and first-selected specific embodiment, the present invention is further elaborated:
As shown in Figure 2, one group of transverse crease lines shape gate electrode sweep trace 1, public electrode 11 and one group of longitudinal broken line graphic data sweep trace 5 are arranged on the array base palte of this TFT-LCD.Gate electrode sweep trace, public electrode and data scanning line have defined the cellular dot structure of hexagon jointly.A pixel packets contains a TFT switching device, pixel electrode 10 and part public electrode 11.Shown in Fig. 3 a, the TFT device is made up of grid electrode insulating layer 4, semiconductor active layer 3 and data scanning line 5 and drain electrode 7.Pixel electrode 10 is connected with the drain electrode 7 of TFT by the via hole 9 of passivation layer.Identical with top with a kind of TFT dot structure of prior art.TFT-LCD dot structure difference of the present invention is, adopts and forms the cellular dot structure of hexagon jointly by gate electrode sweep trace, public electrode and data scanning line.She Ji sharpest edges are like this, have cancelled metal gate electrode, use the data scanning line to serve as the source electrode, have greatly increased aperture opening ratio.Simultaneously, using non-gate electrode sweep trace of laterally arranging and public electrode is the public composition structures of adjacent three pixels, can make full use of substrate space, reaches maximum thereby make number of pixels surpass traditional rectangular pixel design number.
As shown in Figure 2, pixel of the present invention adopts and forms the cellular dot structure of hexagon jointly by gate electrode sweep trace, public electrode and data scanning line, and public electrode 11 and gate electrode sweep trace 1 adopt metal of the same race, are forming with in a photoetching process.The cross-sectional view of Fig. 2 a to Fig. 2 c can further specify TFT dot structure of the present invention.Comparison diagram 2c and Fig. 1 a, TFT dot structure of the present invention and pixel of the prior art are at the difference at TFT switching device place, do not adopt on the gate electrode structure of structure source electrode and drain electrode, but with arrange with the gate electrode sweep trace on the data scanning line serve as the source electrode.Such structure has been cancelled gate electrode and the source electrode in the traditional structure, obtains bigger aperture opening ratio.
In addition, in the foregoing description, the drain electrode 7 of described gate electrode sweep trace 1, data scanning line 5, thin film transistor (TFT) and public electrode 11 materials can be one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any, and structure can be individual layer or lamination layer structure.Described gate electrode sweep trace 1 and public electrode 11 are for finishing the same material part of making in same plated film, mask lithography and chemical etching technology.Grid electrode insulating layer 4 material are silicon nitride or aluminium oxide etc.Described pixel electrode 10 materials can tin indium oxide, indium zinc oxide or aluminum zinc oxide etc.
Above-mentioned dot structure is a kind of typical structure of the present invention, obviously can carry out various forms of accommodations, as polygonized structure of only the hexagon honeycomb structure being changed to other form etc., serve as the source electrode on the gate electrode sweep trace so long as use data line to be arranged in, the dot structure of other shape and pattern also can be arranged, meet the scope of the invention.
TFT-LCD structure of the present invention can be by following method manufacturing:
At first, use magnetically controlled sputter method, on glass substrate preparation one layer thickness 1000 ' to 7000 ' the grid metallic film.The grid metal material can adopt metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually.Also can use the unitized construction of above-mentioned different materials film.By exposure technology and chemical etching technology, on certain zone of glass substrate, form gate electrode sweep trace 1 and public electrode 11 patterns with the gate electrode mask.
Then, utilize chemical vapor deposition method successive sedimentation 1000 on array base palte ' to 6000 ' grid electrode insulating layer film 4 and 1000 ' to 6000 ' amorphous silicon membrane (active layer 3).The grid electrode insulating layer material is silicon nitride normally, also can use monox and silicon oxynitride etc.With the mask of the active layer back of exposing amorphous silicon is carried out dry etching, form the silicon isolated island.And the insulation course between grid metal and the amorphous silicon plays the effect that stops etching.
Next, adopt and the similar method of preparation gate electrode sweep trace, the thickness that deposition one deck is similar to the grid metal on array base palte 1000 ' to 7000 ' metallic film.Mask by source-drain electrode forms data scanning line 5 and drain electrode 7 in certain zone.Wherein data scanning line and drain electrode have the angle of gradient after identical thickness and the corrosion.Partial data sweep trace and drain electrode contact with the two ends of active layer respectively.
Subsequently, adopt grid electrode insulating layer and the similar method of active layer, on whole array base palte deposition one layer thickness 1000 ' to 6000 ' passivation layer 8, its material is silicon nitride or silicon dioxide normally.Covering grid electrode insulation course 4 and passivation layers 8 above this moment gate electrode sweep trace 1 and the public electrode 11, and be coated with the passivation layer 8 of same thickness above the data scanning line 5, by the mask of passivation layer, utilize exposure and etching technics to form drain electrode passivation layer via hole 9 partly, shown in Fig. 2 c.
At last, adopt grid electrode insulating layer and the similar method of active layer, deposition one deck pixel electrode layer on whole glass substrate, the mask of use transparency electrode by identical processing step, finally forms pixel electrode 10 and memory capacitance 13.Transparency electrode commonly used is ITO or IZO, thickness 100 ' to 1000 ' between.
The above embodiment that proposes is a kind of implementation method, also can be by increasing or reducing exposure frequency and select different materials or combination of materials to realize the present invention.On have the array base palte of polygonized structure, the TFT device architecture obviously can have various modifications and variations.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (11)
1, a kind of TFT LCD array base-plate structure is characterized in that, comprising:
One substrate;
The gate electrode sweep trace that one transverse crease lines type is arranged is formed on the described substrate;
One grid electrode insulating layer is formed on described gate electrode sweep trace and gate electrode and the substrate;
The data scanning line that one longitudinal broken line type is arranged is formed on the described grid electrode insulating layer, and the common definition of the gate electrode sweep trace of arranging with described transverse crease lines type one polygonal pixel cell;
One thin film transistor (TFT) is formed on the overlapping place that arranges of described gate electrode sweep trace and data scanning line, and the data scanning line serves as the source electrode;
One passivation layer is formed on described grid electrode insulating layer, data scanning line and the thin film transistor (TFT), and forms passivation layer via hole or groove on the drain electrode of described thin film transistor (TFT);
One pixel electrode is formed on the described passivation layer, and is connected with the drain electrode of described thin film transistor (TFT) by described passivation layer via hole or groove.
2, array base-plate structure according to claim 1, it is characterized in that: the public electrode that also comprises a transverse crease lines type is formed on the substrate, be positioned at a side of described polygonal pixel cell, the gate electrode sweep trace of arranging with described transverse crease lines type is relative status.
3, array base-plate structure according to claim 1 is characterized in that: a described pixel electrode part is positioned on the public electrode.
4, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: described polygonal pixel cell is specially hexagonal pixel cell.
5, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: the drain electrode of described gate electrode sweep trace, data scanning line, thin film transistor (TFT) or public electrode are individual layer or the lamination layer structure that one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any constitute.
6, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: the material of described grid electrode insulating layer is silicon nitride, silicon dioxide or aluminium oxide.
7, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: the material of described pixel electrode is tin indium oxide, indium zinc oxide or aluminum zinc oxide.
8, a kind of manufacture method of TFT LCD array base-plate structure is characterized in that, comprising:
Step 1, depositing metal films on substrate by photoetching process and chemical etching technology, forms the gate electrode sweep trace that the transverse crease lines type is arranged;
Step 2, successive sedimentation grid electrode insulating layer film and amorphous silicon membrane on the substrate of completing steps 1, by photoetching process and chemical etching technology, form on the described gate electrode active layer and above raceway groove;
Step 3, depositing metal films on the substrate of completing steps 2, by photoetching process and chemical etching technology, form data scanning line and drain electrode that the longitudinal broken line type is arranged, wherein partial data sweep trace and part drain electrode are overlapped on the described active layer, and the transverse crease lines type that forms in longitudinal broken line type data scanning line of arranging and the step 1 common definition of the gate electrode sweep trace one polygonal pixel cell of arranging;
Step 4, deposit passivation layer film on the substrate of completing steps 3 by photoetching process and chemical etching technology, forms the passivation layer via hole of drain electrode part;
Step 5, pixel deposition electrode layer on the substrate of completing steps 4 by photoetching process and chemical etching technology, forms pixel electrode, and forms being connected of pixel electrode and drain electrode.
9, manufacture method according to claim 8, it is characterized in that: when forming the gate electrode sweep trace that the transverse crease lines type arranges in the described step 1, form the public electrode that the transverse crease lines type is arranged, the public electrode that gate electrode sweep trace that the transverse crease lines type arranges and transverse crease lines type are arranged lays respectively at the both sides of described polygon pixel cell.
10, manufacture method according to claim 8 is characterized in that: a pixel electrode part that forms in the described step 5 is positioned on the public electrode, forms memory capacitance.
11, according to Claim 8 to 10 arbitrary described manufacture methods, it is characterized in that: definition one polygonal pixel cell is specially definition one hexagonal pixel cell in the described step 3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710119783A CN100595660C (en) | 2007-07-31 | 2007-07-31 | Thin film transistor liquid crystal display array basal plate structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710119783A CN100595660C (en) | 2007-07-31 | 2007-07-31 | Thin film transistor liquid crystal display array basal plate structure and manufacturing method thereof |
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| CN101359136A true CN101359136A (en) | 2009-02-04 |
| CN100595660C CN100595660C (en) | 2010-03-24 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110262138A (en) * | 2019-06-05 | 2019-09-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of dot structure and liquid crystal display panel |
| CN110867457A (en) * | 2019-11-19 | 2020-03-06 | 福建华佳彩有限公司 | Array substrate with high-capacitance structure and manufacturing method |
| WO2023097506A1 (en) * | 2021-11-30 | 2023-06-08 | 京东方科技集团股份有限公司 | Display apparatus, and display panel and manufacturing method therefor |
| WO2024124560A1 (en) * | 2022-12-16 | 2024-06-20 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
-
2007
- 2007-07-31 CN CN200710119783A patent/CN100595660C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110262138A (en) * | 2019-06-05 | 2019-09-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of dot structure and liquid crystal display panel |
| US11392001B2 (en) | 2019-06-05 | 2022-07-19 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Pixel structure and liquid crystal display panel |
| CN110867457A (en) * | 2019-11-19 | 2020-03-06 | 福建华佳彩有限公司 | Array substrate with high-capacitance structure and manufacturing method |
| WO2023097506A1 (en) * | 2021-11-30 | 2023-06-08 | 京东方科技集团股份有限公司 | Display apparatus, and display panel and manufacturing method therefor |
| WO2024124560A1 (en) * | 2022-12-16 | 2024-06-20 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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| Publication number | Publication date |
|---|---|
| CN100595660C (en) | 2010-03-24 |
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Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20141208 Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20141208 |
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Effective date of registration: 20141208 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing economic and Technological Development Zone, West Central Road, No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |