CN101325223A - Nanometer silicon variable capacitance diode and method of processing the same - Google Patents
Nanometer silicon variable capacitance diode and method of processing the same Download PDFInfo
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- CN101325223A CN101325223A CNA2008100242039A CN200810024203A CN101325223A CN 101325223 A CN101325223 A CN 101325223A CN A2008100242039 A CNA2008100242039 A CN A2008100242039A CN 200810024203 A CN200810024203 A CN 200810024203A CN 101325223 A CN101325223 A CN 101325223A
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- capacitance diode
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- variable capacitance
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Abstract
The invention relates to a nano-crystalline silicon variable-capacitance diode, which adopts quantum tunneling as main the conduction mechanism and has excellent temperature stability. The reverse leakage current Ir of the nanometer silicon variable-capacitance diode has a magnitude of nanoampere (nA). The invention also provides a processing method of the variable-capacitance diode. The nano-crystalline silicon variable-capacitance diode comprises a single-crystal silicon substrate and an electrode, wherein an epitaxial layer is covered on the upper surface of the substrate, a back electrode is arranged on the lower surface of the substrate, and a SiO2 layer is covered outside the epitaxial layer. The variable-capacitance diode is characterized in that windows are arranged on the SiO2 layer and cover a doped nano-crystalline silicon film used an operational layer, and the electrode is arranged in the operational layer. The processing method comprises selecting a P-type or N-type low-resistance single-crystal silicon as the substrate, allowing the epitaxial layer to grow on the substrate, allowing the SiO2 layer to grow on the epitaxial layer by thermal oxidization using semiconductor planar technology, making rows of orderly arranged small windows on the SiO2 layer by using photoetching technique of the planar technology, allowing the doped nano-crystalline silicon film to grow on the windows of the SiO2 layer as the operational layer of a device, forming the electrode on the nano-crystalline silicon layer by using sputtering or evaporation method, making an electrode pattern by using the photoetching technique, making an upper surface passivation film, slicing, and packaging to obtain the final product.
Description
(1) technical field
The present invention relates to nanometer silicon variable capacitance diode, the invention still further relates to the processing method of nanometer silicon variable capacitance diode.
(2) background technology
Existing common variable capacitance diode is to utilize the homogeneity of monocrystalline (C-Si) or single GaAs (C-GaAs) material or lead the matter junction structure to constitute, its technology mostly is to form under the high temperature about 1000 ℃, reverse leakage is several microamperes (μ A) or milliampere (mA) magnitude, operating temperature range is lower than 150 ℃, major part is gradual structure, and its current transfer mechanism is thermal excitation or space charge (SCLC) mechanism.
(3) summary of the invention
At the problems referred to above, the invention provides a kind of nanometer silicon variable capacitance diode, it is main transmission mechanism with quantum tunneling mechanism, reverse leakage current Ir has fabulous temperature stability for receiving peace (nA) magnitude.
The technical scheme of nanometer silicon variable capacitance diode:
It comprises monocrystalline silicon substrate, electrode, and described substrate upper surface is coated with epitaxial loayer, and described substrate lower surface is a back electrode, and the outside of described epitaxial loayer covers SiO
2Layer is characterized in that: described SiO
2Layer is provided with window, and described window covers the working lining of dopen Nano silicon thin film, and described electrode is arranged at described working lining.
It is further characterized in that: the doping content of described epitaxial loayer is (8.2～8.8) * 10
15Individual/cm
3The thickness of described epitaxial loayer is 8 μ m～10 μ m; The resistivity of described monocrystalline silicon substrate is 1 * 10
-2Ω cm～5 * 10
-3Ω cm; Described SiO
2Layer thickness is 0.8 μ m.
The processing method of nanometer silicon variable capacitance diode:
With P type or N type low resistance monocrystalline silicon is substrate, and the about 8 μ m of growth one deck～thick doped epitaxial layer of 10 μ m on substrate adopts semiconductor planar technology on epitaxial loayer, the thick SiO of the thermal oxidation method growth about 0.8 μ m of one deck
2Layer is at SiO
2Re-use the planar technique photoetching technique on the layer and make several rows of neat wicket, at SiO
2Window on growth one deck dopen Nano silicon thin film as the working lining of device, on the nanometer silicon layer, form electrode then with sputtering method or evaporation, adopt photoetching technique to stay electrode pattern again, do the upper surface passivating film then, section encapsulation at last forms product.
Diode by above-mentioned craftwork manufacture of the present invention, because thin nanoparticle has the quantum dot feature in the Nano thin film, its transmission mechanism belongs to a kind of and leads matter knot amount worker and put tunnelling mechanism, so its product of making is subjected to Temperature Influence less, has superior volt one peace characteristic, puncture voltage is complete hard breakdown, electrical quantity is little with the probability of temperature drift, and can in 250 ℃ high temperature range, normally use, and obey the steep junction capacitance formula that holds, its knot with homalographic holds, and nanometer silicon variable capacitance diode is bigger 2～3 times than common transfiguration two electrode capacitances.
(4) description of drawings
The structural representation that Fig. 1 analyses and observe for the present invention.
(5) embodiment
See Fig. 1, the present invention includes monocrystalline silicon substrate 1, substrate 1 upper surface is coated with epitaxial loayer 5, and substrate 1 lower surface is a back electrode 7, and epitaxial loayer 5 covers SiO
2Layer 6, SiO
2Layer 6 is provided with window, and window covers the working lining 2 of dopen Nano silicon thin film, and it is surface passivated membrane that working lining 2 is provided with electrode 3,4.Epitaxial loayer 5 doping contents are (8.2～8.8) * 10
15Individual impurity cluster/cm
3, the thickness of epitaxial loayer is 8 μ m～10 μ m; The resistivity of monocrystalline silicon substrate is 1 * 10
-2Ω cm～5 * 10
-3Ω cm; SiO
2Layer thickness is 0.8 μ m.
Below in conjunction with accompanying drawing 1 course of processing of the present invention is described:
With P type or the low electric cloudy monocrystalline silicon of N type is substrate 1, and growth one deck doped epitaxial layer 5 that about 8 μ m～10 μ m are thick adopts semiconductor planar technology on epitaxial loayer 5 on substrate 1, the thick SiO of the thermal oxidation method growth about 0.8 μ m of one deck
2Layer 6 is at SiO
2Re-use the planar technique photoetching technique on the layer 6 and make several rows of neat wicket, area is decided by the different cultivars design, at SiO
2Window on growth one deck dopen Nano silicon thin film as the working lining 2 of device, on nanometer silicon layer 2, form electrode 3 then with sputtering method or evaporation, adopt photoetching technique to stay electrode pattern again, do upper surface passivating film 4 then, section encapsulation at last forms product.
Claims (6)
1, nanometer silicon variable capacitance diode, it comprises monocrystalline silicon substrate, electrode, and described substrate upper surface is coated with epitaxial loayer, and described substrate lower surface is a back electrode, and the outside of described epitaxial loayer covers SiO
2Layer is characterized in that: described SiO
2Layer is provided with window, and described window covers the working lining of dopen Nano silicon thin film, and described electrode is arranged at described working lining.
2, according to the described nanometer silicon variable capacitance diode of claim 1, it is characterized in that: the doping content of described epitaxial loayer is (8.2～8.8) * 10
15Individual/cm
3
3, according to the described nanometer silicon variable capacitance diode of claim 1, it is characterized in that: the thickness of described epitaxial loayer is 8 μ m～10 μ m.
4, according to the described nanometer silicon variable capacitance diode of claim 1, it is characterized in that: the resistivity of described monocrystalline silicon substrate is 1 * 10
-2Ω cm～5 * 10
-3Ω cm.
5, according to the described nanometer silicon variable capacitance diode of claim 1, it is characterized in that: described SiO
2Layer thickness is 0.8 μ m.
6, the processing method of nanometer silicon variable capacitance diode, it is characterized in that: it may further comprise the steps, with P type or N type low resistance monocrystalline silicon is substrate, the about 8 μ m of growth one deck～thick doped epitaxial layer of 10 μ m on substrate, on epitaxial loayer, adopt semiconductor planar technology, the thick SiO of the thermal oxidation method growth about 0.8 μ m of one deck
2Layer is at SiO
2Re-use the planar technique photoetching technique on the layer and make several rows of neat wicket, at SiO
2Window on growth one deck dopen Nano silicon thin film as the working lining of device, on the nanometer silicon layer, form electrode then with sputtering method or evaporation, adopt photoetching technique to stay electrode pattern again, do the upper surface passivating film then, section encapsulation at last forms product.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100242039A CN101325223A (en) | 2008-05-20 | 2008-05-20 | Nanometer silicon variable capacitance diode and method of processing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100242039A CN101325223A (en) | 2008-05-20 | 2008-05-20 | Nanometer silicon variable capacitance diode and method of processing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101325223A true CN101325223A (en) | 2008-12-17 |
Family
ID=40188649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100242039A Pending CN101325223A (en) | 2008-05-20 | 2008-05-20 | Nanometer silicon variable capacitance diode and method of processing the same |
Country Status (1)
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| CN (1) | CN101325223A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872723A (en) * | 2010-05-24 | 2010-10-27 | 无锡汉咏微电子有限公司 | Germanium tunnelling diode and preparation method thereof |
| CN104538300A (en) * | 2014-12-19 | 2015-04-22 | 扬州国宇电子有限公司 | Technological method for adjusting barrier height of Schottky diode by doping silicon dioxide film |
-
2008
- 2008-05-20 CN CNA2008100242039A patent/CN101325223A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872723A (en) * | 2010-05-24 | 2010-10-27 | 无锡汉咏微电子有限公司 | Germanium tunnelling diode and preparation method thereof |
| CN101872723B (en) * | 2010-05-24 | 2014-10-08 | 无锡汉咏微电子股份有限公司 | Germanium tunnelling diode and preparation method thereof |
| CN104538300A (en) * | 2014-12-19 | 2015-04-22 | 扬州国宇电子有限公司 | Technological method for adjusting barrier height of Schottky diode by doping silicon dioxide film |
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Open date: 20081217 |