CN101320696A - Stack type packaging structure and its manufacturing method - Google Patents
Stack type packaging structure and its manufacturing method Download PDFInfo
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- CN101320696A CN101320696A CNA2007101089169A CN200710108916A CN101320696A CN 101320696 A CN101320696 A CN 101320696A CN A2007101089169 A CNA2007101089169 A CN A2007101089169A CN 200710108916 A CN200710108916 A CN 200710108916A CN 101320696 A CN101320696 A CN 101320696A
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- semiconductor package
- package part
- conductive projection
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- soldered ball
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention discloses a stacked package structure and a manufacturing method thereof. A substrate with multiple stacked pads on a surface thereof is provided. At least one semiconductor chip is connected to the substrate electrically, and a package rubber is formed to cover the semiconductor chip and expose these stacked pads, so as to form lower layer semiconductor package piece. A conductive projection is formed on at least one stacked pad through a wire manner, so that at least one upper layer semiconductor package piece is connected to the conductive projection of the lower layer semiconductor package piece and the stacked pads through a solder ball that has a stacked height with the conductive projection greater than height of the lower layer semiconductor package piece, so as to form a stacked package structure; when the stacked package piece or the upper, lower layer semiconductor package pieces have shape distortion caused by stress during manufacturing, the conductive projection is applied to compensate height shortness of collapse of the solder ball, so that the solder ball is wet on the substrate of the lower layer semiconductor package piece in effective contact.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, particularly relate to a kind of stack encapsulation structure and method for making thereof.
Background technology
Electronic product develops towards direction multi-functional, electrically high and high-speed cruising now, and for cooperating this developing direction, the semiconductor dealer there's no one who doesn't or isn't actively researches and develops the semiconductor device that can be integrated with a plurality of chips or packaging part, uses the demand that meets electronic product.
See also Fig. 1, United States Patent (USP) the 5th, 222, No. 014 a kind of stack encapsulation structure is disclosed, ball grid array (BGA) substrate 11 that it provides a upper surface to be provided with weld pad 110, on this ball grid array base plate 11, connect and put semiconductor chip 10 and form the packing colloid 13 that coats this semiconductor chip 10, to form first semiconductor package part 101, and then another second semiconductor package part 102 of finishing encapsulation utilized the reflow operation and connect on substrate 11 weld pads 110 of putting and be electrically connected to this first semiconductor package part 101 by soldered ball 14, use forming the stacked type encapsulating structure.
In the aforesaid stack encapsulation structure, place on first semiconductor package part 101 for effectively connecing by soldered ball 14 for second semiconductor package part 102, the packing colloid 13 that must control this first semiconductor package part 101 is highly unsuitable too high, be because this tradition soldered ball 14 is being that its sphere diameter is about 0.5mm under the 1mm situation apart from (pitch) to each other, and with these soldered ball 14 reflows to substrate 11 time, highly become 0.4mm after its crumple (collapse), so the packing colloid 13 of this first semiconductor package part 101 highly should not surpass 0.3mm.
But when electrically being applied to the semiconductor package part on fine rule road (fine pitch) for promoting, when the spacing of soldered ball must be contracted to 0.65mm or 0.5mm, employed soldered ball sphere diameter also must be reduced to 0.3mm thereupon, so highly be about 0.24mm after this soldered ball crumple, be significantly less than the packing colloid height (0.3mm) of first semiconductor package part, so will cause second semiconductor package part can't be effectively by this soldered ball contact and moistening (wetting) to the substrate of this first semiconductor package part, cause the failure that is electrically connected to each other.
In addition, under the processing procedure stress, during as the substrate generation warpage (warpage) of first or second semiconductor package part, with the tangible gap of generation between the soldered ball of the substrate peripheral zone that makes first semiconductor package part and second semiconductor package part, aforementioned moistening undesirable condition can be caused equally, and the good pad (solder joint) of generation between this soldered ball and substrate weld pad can't be made.
In view of this, see also Fig. 2, United States Patent (USP) the 6th, 987, No. 314 another kind of stack encapsulation structure is disclosed, it is to have set in advance pre-scolding tin (pre-solder) material 22 on the substrate weld pad of first semiconductor package part 201 comprehensively, connects by soldered ball 24 for second semiconductor package part 202 and puts also reflow in this pre-soldering tin material 22, so that this second semiconductor package part 202 is positioned on this first semiconductor package part 201.
But this kind mode needs on the substrate weld pad of first semiconductor package part pre-soldering tin material to be set, and not only increases manufacturing cost, also improves the complexity of processing procedure simultaneously; Moreover, carry out the Encapsulation Moulds compacting journey of chip and when forming the packing colloid of coating chip, because of this substrate surface is provided with pre-soldering tin material, easily cause the clamping of encapsulating mould bad, or the packed mould of this pre-soldering tin material is damaged in this first semiconductor package part; In addition,, will increase a reflow operation, cause the rising of manufacturing cost as behind Chip Packaging mold pressing processing procedure, pre-soldering tin material being set again.
Therefore, how a kind of stack encapsulation structure and method for making thereof are provided, on avoiding, utilize soldered ball to electrically connect when piling up between lower floor's semiconductor package part, because of the ball height deficiency of fine rule road semiconductor package part or the substrate warp of semiconductor package part, cause the soldered ball of upper strata semiconductor package part can't effectively contact and moistening substrate problem to lower floor's semiconductor package part, and because of default manufacturing cost that pre-soldering tin material causes on the substrate weld pad of lower floor's semiconductor package part and complexity increase, and the easy packed mould of the bad and pre-soldering tin material of the clamping of encapsulating mould institute damage problem, really be the required problem of urgently facing on the association area.
Summary of the invention
The shortcoming of background technology in view of the above, a purpose of the present invention provides a kind of applicable to the stack encapsulation structure and the method for making thereof of piling up fine rule road semiconductor package part.
A further object of the present invention provides a kind of stack encapsulation structure and method for making thereof, thereby can avoid utilizing between the upper and lower layer semiconductor package part soldered ball to electrically connect when piling up, because of the ball height deficiency of fine rule road semiconductor package part or the substrate warp of semiconductor package part, cause the soldered ball of upper strata semiconductor package part can't effectively contact and moistening substrate problem to lower floor's semiconductor package part.
A time purpose of the present invention provides and a kind ofly pre-soldering tin material need not be set can be applicable to the stack encapsulation structure and the method for making thereof of piling up fine rule road semiconductor package part.
Another object of the present invention provides a kind of stack encapsulation structure and method for making thereof, avoids prior art that problems such as cost of manufacture that pre-soldering tin material causes and complexity increase are set.
For reaching above-mentioned purpose and other purpose, the invention provides a kind of method for making of stack encapsulation structure, comprise: provide a surface to be provided with a plurality of substrates that pile up weld pad, on this substrate, to be electrically connected to few semiconductor chip, and formation coats the packing colloid of this semiconductor chip, and make those pile up weld pad and expose outside this packing colloid, to constitute lower floor's semiconductor package part; Utilize the routing mode to form conductive projection (Au stud bump) on the weld pad at least one piling up; And provide at least one upper strata semiconductor sealing, and make this upper strata semiconductor package part connect the conductive projection that places this lower floor's semiconductor package part and pile up on the weld pad by soldered ball, wherein the stacks as high of this soldered ball and this conductive projection is greater than the packing colloid height of lower floor's semiconductor package part, thereby constitutes stack encapsulation structure.
The present invention also provides a kind of stack encapsulation structure, comprise: lower floor's semiconductor package part, this lower floor's semiconductor package part include substrate, be electrically connected to the semiconductor chip of this substrate, be formed on this substrate in order to the packing colloid that coats this semiconductor chip, and a plurality of weld pads that pile up of being located at this substrate surface and exposing outside this packing colloid; Be located at least one conductive projection that piles up on the weld pad in the routing mode; And at least one connecing by soldered ball place this conductive projection and pile up upper strata semiconductor package part on the weld pad, and wherein the stacks as high of this soldered ball and this conductive projection is greater than the packing colloid height of lower floor's semiconductor package part.
In an embodiment, when the upper strata semiconductor package part is the semiconductor package part on fine rule road (fine pitch), for height after the soldered ball crumple of avoiding this upper strata semiconductor package part less than the packing colloid height of this lower floor's semiconductor package part, this conductive projection is that the substrate of comprehensively being located at this lower floor's semiconductor package part piles up on the weld pad, connect when placing this lower floor semiconductor package part by soldered ball for the upper strata semiconductor package part, be able to fill up the deficiency place of height after the soldered ball crumple, and this soldered ball effectively contacted and moistening on the substrate of this lower floor's semiconductor package part by this conductive projection.
In another embodiment, when warpage takes place because of processing procedure stress in upper and lower layer semiconductor package part, this conductive projection is that piling up on the weld pad of substrate peripheral is located in selection, pile up between weld pad because of the gap that warpage was produced with the soldered ball of filling up upper and lower semiconductor package part outer peripheral areas by the setting of this conductive projection and substrate, and soldered ball is effectively contacted and moistening on the substrate of this lower floor's semiconductor package part.
In addition, this conductive projection is the golden projection (stud bump) that utilizes wire bonder to set, and this conductive projection can on a pile stitch welding pad, be provided with single, also can be a plurality of in the planar alignment of a pile stitch welding pad, vertical stacking is a plurality of also or on a pile stitch welding pad.
Because in stack encapsulation structure of the present invention and the method for making thereof, be to form conductive projection on the weld pad at least one piling up of the substrate surface of lower floor's semiconductor package part, with when upper and lower layer semiconductor package part engages by relative soldered ball, avoid because the shortcoming of the failure welding that application causes of prior art warpage issues or fine rule road semiconductor package part overcomes prior art simultaneously problems such as cost of manufacture that pre-soldering tin material causes and complexity increase are set because of the bed hedgehopping effect of conductive projection.
Description of drawings
Fig. 1 is the stack encapsulation structure generalized section that shows No. the 5th, 222,014, existing United States Patent (USP);
Fig. 2 is the stack encapsulation structure generalized section that shows No. the 6th, 987,314, United States Patent (USP);
Fig. 3 A to Fig. 3 D is the generalized section that shows stack encapsulation structure of the present invention and method for making first embodiment thereof;
Fig. 4 A to Fig. 4 C is the generalized section that shows stack encapsulation structure of the present invention and method for making second embodiment thereof; And
Fig. 5 A to Fig. 5 C is the schematic diagram that shows the different embodiment of conductive projection in stack encapsulation structure of the present invention and the method for making thereof.
The component symbol simple declaration
10 semiconductor chips, 101 first semiconductor package parts
102 second semiconductor package parts, 11 substrates
110 weld pads, 12 second ball grid array base plates
13 packing colloids, 14 soldered balls
201 first semiconductor package parts, 202 second semiconductor package parts
22 pre-soldering tin material 24 soldered balls
30 semiconductor chips, 301 lower floor's semiconductor package parts
302 upper strata semiconductor sealing 31 substrates
31a first surface 31b second surface
311 pile up weld pad 312 solder ball pads
32 bonding wires, 33 packing colloids
341 conductive projections, 342 soldered balls
35 soldered balls, 40 semiconductor chips
401 lower floor's semiconductor package parts, 402 upper strata semiconductor package parts
41 substrate 41a first surfaces
41b second surface 411 piles up weld pad
412 solder ball pads, 43 packing colloids
441 conductive projections, 442 soldered balls
511 pile up weld pad 541 conductive projections
Embodiment
Below conjunction with figs. illustrates specific embodiments of the invention now, so that those skilled in the art can understand technical characterictic of the present invention easily and reach effect.
First embodiment
See also Fig. 3 A to Fig. 3 D, be the generalized section of stack encapsulation structure of the present invention and method for making first embodiment thereof.
Shown in Fig. 3 A and Fig. 3 B, the substrate 31 of tool opposite first 31a and second surface 31b at first is provided, this substrate for example is a ball grid array base plate, and its first surface 31a is provided with a plurality of weld pads 311 that pile up, and second surface is provided with a plurality of solder ball pads 312.
Then on this substrate 31 first surface 31a, connect and put and electrically connect semiconductor chip 30 at least, the bonding wire 32 of this semiconductor chip 30 by accompanying drawing also or cover crystal type (not shown) and be electrically connected to this substrate 31, and formation coats the packing colloid 33 of this semiconductor chip 30, and make those pile up weld pad 311 and expose outside this packing colloid 33, to constitute lower floor's semiconductor package part 301.
Shown in Fig. 3 C, pile up the conductive projection 341 that forms on the weld pad 311 as golden projection (stud bump) in those in the routing mode by wire bonder comprehensively.
Shown in Fig. 3 D, the upper strata semiconductor sealing 302 on one tool fine rule road is provided, and make this upper strata semiconductor package part 302 connect the conductive projection 341 that places this lower floor's semiconductor package part 301 and pile up on the weld pad 311 by soldered ball 342, wherein the stacks as high of this soldered ball 342 and this conductive projection 341 is greater than packing colloid 33 height of lower floor's semiconductor package part 301, thereby constitutes stack encapsulation structure.
Other has planted soldered ball 35 again on the solder ball pad 312 of substrate 31 second surfaces of this lower floor's semiconductor package part 301, be electrically connected to external device (ED) for this stack encapsulation structure.
That is, when the upper strata semiconductor package part is the semiconductor package part on fine rule road (fine pitch), for height after the soldered ball crumple of avoiding this upper strata semiconductor package part less than the packing colloid height of this lower floor's semiconductor package part, the substrate that this moment, this conductive projection promptly was located at this lower floor's semiconductor package part comprehensively piles up on the weld pad, connect when placing this lower floor semiconductor package part by soldered ball for the upper strata semiconductor package part, be able to fill up the deficiency place of height after the soldered ball crumple, and this soldered ball effectively contacted and moistening on the substrate of this lower floor's semiconductor package part by this conductive projection.
By aforementioned method for making, the present invention also provides a kind of stack encapsulation structure, comprise: lower floor's semiconductor package part 301, this lower floor's semiconductor package part 301 include substrate 31, be electrically connected to the semiconductor chip 30 of this substrate 31, be formed on this substrate 31 in order to the packing colloid 33 that coats this semiconductor chip 30, and a plurality of be located at these substrate 31 surfaces and expose outside this packing colloid 33 pile up weld pad 311; Be located at least one conductive projection 341 that piles up on the weld pad 311 in the routing mode; And at least one connecing by soldered ball 342 place this conductive projection 341 and pile up upper strata semiconductor package part 302 on the weld pad 311, and wherein the stacks as high of this soldered ball 342 and this conductive projection 341 is greater than packing colloid 33 height of lower floor's semiconductor package part 301.
Second embodiment
See also Fig. 4 A to Fig. 4 C, be the generalized section of stack encapsulation structure of the present invention and method for making second embodiment thereof.
Shown in Fig. 4 A, the substrate 41 of tool opposite first 41a and second surface 41b at first is provided, this substrate for example is a ball grid array base plate, and its first surface 41a is provided with a plurality of weld pads 411 that pile up, and second surface is provided with a plurality of solder ball pads 412.
Then on the first surface 41a of this substrate 41, connect and put and electrically connect semiconductor chip 40 at least, and formation coats the packing colloid 43 of this semiconductor chip 40, and make those pile up weld pad 411 and expose outside this packing colloid 43, to constitute lower floor's semiconductor package part 401.
Shown in Fig. 4 B, utilize the routing mode to pile up the conductive projection 441 that forms on the weld pad 411 as golden projection (stud bump) in the part of these substrate 41 peripheries.
Shown in Fig. 4 C, the upper strata semiconductor package part 402 of one warpage is connect the conductive projection 441 that places this lower floor's semiconductor package part 401 by soldered ball 442 and pile up on the weld pad 411, wherein the stacks as high of this soldered ball 442 and this conductive projection 441 is greater than packing colloid 43 height of lower floor's semiconductor package part 401, thereby constitutes stack encapsulation structure.
That is, when upper strata semiconductor package part (also or lower floor's semiconductor package part) when warpage taking place because of processing procedure stress, this conductive projection is that piling up on the weld pad of substrate peripheral is located in selection, pile up between weld pad because of the gap that warpage was produced with the soldered ball of filling up upper and lower semiconductor package part outer peripheral areas by the setting of this conductive projection and substrate, and soldered ball is effectively contacted and moistening on the substrate of this lower floor's semiconductor package part.
In addition, other sees also Fig. 5 A to Fig. 5 C, in stack encapsulation structure of the present invention and the method for making thereof single conductive projection 541 (shown in Fig. 5 A) can be set on a pile stitch welding pad 511, also can be in a plurality of conductive projections 541 of the planar alignment of a pile stitch welding pad 511 (shown in Fig. 5 B), a plurality of conductive projections 541 of vertical stacking (shown in Fig. 5 C) also or on a pile stitch welding pad 511.The visual actual processing procedure of the design variation of aforementioned various conductive projection 541 needs, and selecting enough Area of bearing or height, thereby keeps supplying the effectively contact and moistening on the substrate of lower floor's semiconductor package part of soldered ball of layer semiconductor package part.
Therefore, stack encapsulation structure of the present invention and method for making thereof, be to form conductive projection on the weld pad at least one piling up of the substrate surface of lower floor's semiconductor package part, with when upper and lower layer semiconductor package part engages by relative soldered ball, avoid because the shortcoming of the failure welding that application causes of prior art warpage issues or fine rule road semiconductor package part overcomes prior art simultaneously problems such as cost of manufacture that pre-soldering tin material causes and complexity increase are set because of the bed hedgehopping effect of conductive projection.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims.
Claims (14)
1. the method for making of a stack encapsulation structure comprises:
Provide a surface to be provided with a plurality of substrates that pile up weld pad, on this substrate, to be electrically connected to few semiconductor chip, and form to coat the packing colloid of this semiconductor chip, and make those pile up weld pad exposing outside this packing colloid, to constitute lower floor's semiconductor package part;
Utilize the routing mode to form conductive projection on the weld pad at least one piling up; And
At least one upper strata semiconductor sealing is provided, and make this upper strata semiconductor package part connect the conductive projection that places this lower floor's semiconductor package part and pile up on the weld pad by soldered ball, wherein the stacks as high of this soldered ball and this conductive projection is greater than the packing colloid height of lower floor's semiconductor package part, thereby constitutes stack encapsulation structure.
2. the method for making of stack encapsulation structure according to claim 1, wherein, this substrate is a ball grid array base plate, it has opposite first and second surface, this first surface is provided with a plurality of weld pads that pile up, and second surface is provided with a plurality of solder ball pads, for planting soldered ball.
3. the method for making of stack encapsulation structure according to claim 1, wherein, this conductive projection is for utilizing wire bonder with the formed golden projection of routing mode.
4. the method for making of stack encapsulation structure according to claim 1, wherein, this upper strata semiconductor sealing is the semiconductor package part on tool fine rule road, height is less than the packing colloid height of this lower floor's semiconductor package part after the soldered ball crumple of this upper strata semiconductor package part, the substrate that this conductive projection promptly is located at this lower floor's semiconductor package part comprehensively piles up on the weld pad, connect when placing this lower floor semiconductor package part by soldered ball for the upper strata semiconductor package part, fill up the deficiency of height after the soldered ball crumple by this conductive projection.
5. the method for making of stack encapsulation structure according to claim 1, wherein, this upper strata semiconductor package part produces warpage because of processing procedure stress, this conductive projection is to select to be located at the piling up on the weld pad of substrate peripheral, piles up between weld pad gap because of warpage was produced with the soldered ball of filling up upper and lower semiconductor package part outer peripheral areas by the setting of this conductive projection and substrate.
6. the method for making of stack encapsulation structure according to claim 1, wherein, this lower floor's semiconductor package part produces warpage because of processing procedure stress, this conductive projection is to select to be located at the piling up on the weld pad of substrate peripheral, piles up between weld pad gap because of warpage was produced with the soldered ball of filling up upper and lower semiconductor package part outer peripheral areas by the setting of this conductive projection and substrate.
7. the method for making of stack encapsulation structure according to claim 1, wherein, this conductive projection in the setting on a pile stitch welding pad be chosen as in be provided with on a pile stitch welding pad single conductive projection, in a plurality of conductive projections of planar alignment of a pile stitch welding pad or on a pile stitch welding pad a plurality of conductive projections of vertical stacking wherein one.
8. stack encapsulation structure comprises:
One lower floor's semiconductor package part, this lower floor's semiconductor package part include substrate, be electrically connected to the semiconductor chip of this substrate, be formed on this substrate in order to the packing colloid that coats this semiconductor chip, and a plurality of weld pads that pile up of being located at this substrate surface and exposing outside this packing colloid;
Be located at least one conductive projection that piles up on the weld pad in the routing mode; And
At least one connecing by soldered ball places this conductive projection and piles up upper strata semiconductor package part on the weld pad, and wherein the stacks as high of this soldered ball and this conductive projection is greater than the packing colloid height of lower floor's semiconductor package part.
9. stack encapsulation structure according to claim 8, wherein, this substrate is a ball grid array base plate, it has opposite first and second surface, this first surface is provided with a plurality of weld pads that pile up, and second surface is provided with a plurality of solder ball pads, for planting soldered ball.
10. stack encapsulation structure according to claim 8, wherein, this conductive projection is for utilizing wire bonder with the formed golden projection of routing mode.
11. stack encapsulation structure according to claim 8, wherein, this upper strata semiconductor sealing is the semiconductor package part on tool fine rule road, height is less than the packing colloid height of this lower floor's semiconductor package part after the soldered ball crumple of this upper strata semiconductor package part, the substrate that this conductive projection promptly is located at this lower floor's semiconductor package part comprehensively piles up on the weld pad, connect when placing this lower floor semiconductor package part by soldered ball for the upper strata semiconductor package part, fill up the deficiency of height after the soldered ball crumple by this conductive projection.
12. stack encapsulation structure according to claim 8, wherein, this upper strata semiconductor package part produces warpage because of processing procedure stress, this conductive projection selects to be located at piling up on the weld pad of substrate peripheral, piles up between weld pad gap because of warpage was produced with the soldered ball of filling up upper and lower semiconductor package part outer peripheral areas by the setting of this conductive projection and substrate.
13. stack encapsulation structure according to claim 8, wherein, this lower floor's semiconductor package part produces warpage because of processing procedure stress, this conductive projection selects to be located at piling up on the weld pad of substrate peripheral, piles up between weld pad gap because of warpage was produced with the soldered ball of filling up upper and lower semiconductor package part outer peripheral areas by the setting of this conductive projection and substrate.
14. stack encapsulation structure according to claim 8, wherein, this conductive projection in the setting on a pile stitch welding pad be chosen as in be provided with on a pile stitch welding pad single conductive projection, in a plurality of conductive projections of planar alignment of a pile stitch welding pad or on a pile stitch welding pad a plurality of conductive projections of vertical stacking wherein one.
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| CNA2007101089169A CN101320696A (en) | 2007-06-04 | 2007-06-04 | Stack type packaging structure and its manufacturing method |
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| CNA2007101089169A CN101320696A (en) | 2007-06-04 | 2007-06-04 | Stack type packaging structure and its manufacturing method |
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| CN102064162A (en) * | 2010-11-09 | 2011-05-18 | 日月光半导体制造股份有限公司 | Stacked package structure, package structure thereof and manufacture method of the package structure |
| CN102728957A (en) * | 2009-02-23 | 2012-10-17 | 韩美半导体株式会社 | Method for generating laser beam irradiation trajectory |
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| CN102064162B (en) * | 2010-11-09 | 2013-01-02 | 日月光半导体制造股份有限公司 | Stacked package structure, package structure thereof and manufacture method of the package structure |
| CN102064162A (en) * | 2010-11-09 | 2011-05-18 | 日月光半导体制造股份有限公司 | Stacked package structure, package structure thereof and manufacture method of the package structure |
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| CN103296005B (en) * | 2012-02-27 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of redundant interconnections structure for interconnecting between silicon |
| CN103296005A (en) * | 2012-02-27 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Redundancy interconnection structure for interconnection among silicon chips |
| CN103378037B (en) * | 2012-04-20 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Methods and apparatus for solder connections |
| CN103378037A (en) * | 2012-04-20 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Methods and apparatus for solder connections |
| CN111048468A (en) * | 2018-10-12 | 2020-04-21 | Tdk株式会社 | Laminate of electronic elements and method for manufacturing the same |
| CN111048468B (en) * | 2018-10-12 | 2023-09-05 | Tdk株式会社 | Laminate of electronic component and method for manufacturing the same |
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| CN111128908A (en) * | 2019-11-22 | 2020-05-08 | 中国电子科技集团公司第十三研究所 | Three-dimensional stacked circuit structure and preparation method thereof |
| CN111128908B (en) * | 2019-11-22 | 2024-04-16 | 中国电子科技集团公司第十三研究所 | Three-dimensional stacked circuit structure and preparation method thereof |
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