CN101315889A - Silicon film dry etching method - Google Patents

Silicon film dry etching method Download PDF

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Publication number
CN101315889A
CN101315889A CNA2008100998563A CN200810099856A CN101315889A CN 101315889 A CN101315889 A CN 101315889A CN A2008100998563 A CNA2008100998563 A CN A2008100998563A CN 200810099856 A CN200810099856 A CN 200810099856A CN 101315889 A CN101315889 A CN 101315889A
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dry etching
silicon fiml
etching method
film
silicon
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登坂久雄
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention is related to a dry etching method of a silicon film, characterized in involving the following steps of: preparing the to-be-processed material with the silicon film stacking on the upper side of a substrate; moving the to-be-processed material into a parallel-plate type dry etching equipment wherein a high-frequency electrode and an opposed electrode are parallelly configurated, and placing the substrate of the to-be-processed material on either one of the high-frequency electrode and the opposed electrode; decompressing the dry etching equipment where fluorine and chlorin gas are then directed; imposing high frequency on the high-frequency electrode to etch the silicon film.

Description

The dry etching method of silicon fiml
Technical field
The present invention relates to the dry etching method of silicon fiml.
Background technology
For example, thin-film transistor in the past has reverse-staggered thin-film transistor (for example, with reference to patent documentation 1).In this thin-film transistor, be provided with gate electrode at the upper surface of substrate.Be provided with gate insulating film comprising the upper surface of gate electrode at interior substrate.The upper surface of the gate insulating film on gate electrode is provided with the semiconductive thin film that is made of intrinsic amorphous silicon.Be provided with the ohmic contact layer that constitutes by n type amorphous silicon in the upper surface both sides of semiconductive thin film.Upper surface at each ohmic contact layer is provided with source electrode and drain electrode.
Patent documentation 1: TOHKEMY 2007-79342 communique (Fig. 5)
; in the ohmic contact layer in above-mentioned thin-film transistor in the past and the formation method of semiconductive thin film, the intrinsic amorphous silicon film (semiconductive thin film forms and use film) and the n type amorphous silicon film (ohmic contact layer formation film) of the upper surface that is formed on gate insulating film carried out dry etching continuously.In such cases, adopt SF as etching gas 6(sulphur hexafluoride) gas (patent documentation 1 the 130th section).
SF as so employed etching gas of dry etching method 6Be regarded as problem as a factor of global warming in recent years, therefore replace its replacement gas be selected to important problem.
Summary of the invention
Therefore, main purpose of the present invention is that a kind of SF that do not adopt is provided 6Deng the gas of a factor that becomes global warming, also can carry out the dry etching method of the silicon fiml of dry etching well to silicon fimls such as amorphous silicons.
Preferred scheme of the present invention is the dry etching method of silicon fiml, it is characterized in that, the dry etching of parallel plate-type that contains the mist of fluorine gas (fluorine gas) and chlorine (chlorine gas) by employing comes silicon fiml is carried out dry etching.
In addition, one of preferred scheme of the present invention is the dry etching method of silicon fiml, it is characterized in that, prepares to be laminated with on substrate the machined object of silicon fiml; Machined object is moved into high-frequency electrode and opposite electrode by in the Drycorrosion apparatus of the parallel plate-type of configured in parallel, in described high-frequency electrode or opposite electrode either party of the substrate-placing of described machined object; With described Drycorrosion apparatus decompression, in described Drycorrosion apparatus, import fluorine gas and chlorine; Described high-frequency electrode is applied high frequency, thus the described silicon fiml of etching.
Description of drawings
Fig. 1 is the cutaway view that utilizes an example of the thin-film transistor display panel that the manufacture method comprise dry etching method of the present invention makes.
Fig. 2 is the cutaway view of operation initial in an example of the manufacture method of thin-film transistor display panel shown in Figure 1.
Fig. 3 is the cutaway view of the operation after Fig. 2.
Fig. 4 is the cutaway view of the operation after Fig. 3.
Fig. 5 is the cutaway view of the operation after Fig. 4.
Fig. 6 is the cutaway view of the operation after Fig. 5.
Fig. 7 is the summary pie graph of an example of Drycorrosion apparatus.
Fig. 8 is the summary pie graph of another example of Drycorrosion apparatus.
Fig. 9 is the diagram that is used to illustrate transistor characteristic.
Embodiment
Fig. 1 is the cutaway view that utilizes an example of the thin-film transistor display panel that the manufacture method comprise dry etching method of the present invention makes.This thin-film transistor display panel possesses glass substrate 1.On the regulation position of the upper surface of glass substrate 1, be provided with the gate electrode 2 that constitutes by chromium etc.Be provided with the gate insulating film 3 that constitutes by silicon nitride comprising the upper surface of gate electrode 2 at interior glass substrate 1.
On the regulation position of the upper surface of the gate insulating film on the gate electrode 23, be provided with the semiconductive thin film 4 that constitutes by intrinsic amorphous silicon.On the regulation position of the upper surface of semiconductive thin film 4, be provided with the channel protection film 5 that constitutes by silicon nitride.In the upper surface both sides of channel protection film 5 and the upper surface of the semiconductive thin film 4 of both sides be provided with the ohmic contact layer 6,7 that constitutes by n type amorphous silicon.Upper surface separately at ohmic contact layer 6,7 is provided with source electrode 8 and the drain electrode 9 that is made of chromium etc.
Constitute thin-film transistor 10 reverse-staggered, the channel protection film type by gate electrode 2, gate insulating film 3, semiconductive thin film 4, channel protection film 5, ohmic contact layer 6,7, source electrode 8 and drain electrode 9 herein.
Be provided with the cover that constitutes by silicon nitride and film 11 comprising the upper surface of thin-film transistor 10 at interior gate insulating film 3.Film at the cover on the part corresponding and to be provided with contact hole 12 on 11 with the regulation position of source electrode 8.Be provided with the pixel electrode 13 that is made of ITO on cover is filmed the regulation position of 11 upper surface, it is connected with source electrode 8 via contact hole 12.
Then, an example to the manufacture method of this thin-film transistor display panel describes.At first, as shown in Figure 2,, by the metal film that is made of chromium etc. that is formed by sputtering method being carried out Butut processing (patterning), thereby form gate electrode 2 with photoetch method at the regulation position of the upper surface of glass substrate 1.
Then; comprising gate electrode 2 on the upper surface of interior glass substrate 1, the gate insulating film 3, intrinsic amorphous silicon film (semiconductive thin film forms and uses film) 21 and the silicon nitride film (channel protection film forms and uses film) 22 that utilize plasma CVD method to form continuously to constitute by silicon nitride.Then, form the zone, by the resist film that forms with coatings such as print processes being carried out Butut processing, thereby form resist film 23 with photoetch method at the channel protection film of the upper surface of silicon nitride film 22.
Then, when with resist film 23 as mask, silicon nitride film 22 is carried out dry etching, then the silicon nitride film 22 on the zones beyond the resist film 23 times can be removed, thereby as shown in Figure 3, form channel protection film 5 23 times at resist film.Then, peel off resist film 23.
Then, as shown in Figure 4, comprising the upper surface of channel protection film 5, utilizing plasma CVD method to form n type amorphous silicon film (ohmic contact layer forms and uses film) 24 in interior intrinsic amorphous silicon film 21.Then, at the upper surface of n type amorphous silicon film 24, utilize sputtering method to form the source electrode and the drain electrode that constitute by chromium etc. and forms usefulness film 25.
Then, form at source electrode and drain electrode that source electrode with the upper surface of film 25 forms the zone and drain electrode forms the zone, process by the resist film that is formed by coatings such as print processes being carried out Butut with photoetch method, thus formation resist film 26,27.
Then, when with resist film 26,27 as mask, source electrode and drain electrode are formed with film 25 etching that wets, then source electrode on 26,27 times zones in addition of resist film and drain electrode formation can be removed with film 25, thereby as shown in Figure 5, form source electrode 8 and drain electrode 9 26,27 times at resist film.
Then; when with resist film 26,27 and channel protection film 5 as mask; n type amorphous silicon film 24 and intrinsic amorphous silicon film 21 are carried out such as described later dry etching continuously; then the n type amorphous silicon film 24 on 26,27 times zones in addition of resist film can be removed; and; intrinsic amorphous silicon film 21 on resist film 26,27 and 5 times zones in addition of channel protection film can be removed; thereby as shown in Figure 6; form ohmic contact layer 6,79 times at source electrode 8 and drain electrode, and form semiconductive thin film 45 times at ohmic contact layer 6,7 and channel protection film.Then, peel off resist film 26,27.
Then, as shown in Figure 1, comprising the upper surface of thin-film transistor 10, utilizing plasma CVD method to form the cover that constitutes by silicon nitride and film 11 at interior gate insulating film 3.Then, on filming 11 regulation position, cover utilize photoetch method to form contact hole 12.
Then, on cover was filmed the regulation position of 11 upper surface, by with photoetch method the ITO film that is formed by sputtering method being carried out Butut processing to form pixel electrode 13, it was connected with source electrode 8 via contact hole 12.Obtain thin-film transistor display panel shown in Figure 1 thus.
Then, an example to the Drycorrosion apparatus that is used to carry out dry etching in the above-mentioned manufacture method describes with reference to summary pie graph shown in Figure 7.This Drycorrosion apparatus is a parallel plate-type, and it possesses reaction vessel 31.Bottom in reaction vessel 31 is provided with lower electrode 32, and top is provided with upper electrode 33.In such cases, lower electrode 32 is connected with high frequency electric source 34, upper electrode 33 ground connection.Upper surface mounting at lower electrode 32 has machined object 35.The regulation position of the bottom of reaction vessel 31 is connected with vacuum pump 37 via pipe arrangement 36.
Be provided with gas introduction tube 38 in the center upper portion portion of reaction vessel 31 in the mode of the central portion that connects upper electrode 33.Gas introduction tube 38 is connected with shared pipe arrangement 39.On shared pipe arrangement 39, be connected with the 1st pipe arrangement the 40, the 2nd pipe arrangement 41.The 1st electromagnetically operated valve 42 and the 2nd electromagnetically operated valve 43 and the 1st mass flow controller 44 and the 2nd mass flow controller 45 are housed in the 1st pipe arrangement 40 and the 2nd pipe arrangement 41.The fluorine gas supply source 46 and the chlorine supply source 47 that are made of high pressure tank etc. are connected with the 1st pipe arrangement 40 each top ends with the 2nd pipe arrangement 41.
Then, to adopting the Drycorrosion apparatus of above-mentioned formation, make the machined object 35 on the upper surface that is positioned in lower electrode 32 be in state shown in Figure 5, and the situation when carrying out dry etching continuously on n type amorphous silicon film 24 on the gate insulating film 3 that is made of silicon nitride and the intrinsic amorphous silicon film 21 describe.At first,, discharge the gas in the reaction vessel 31, make the pressure in the reaction vessel 31 reach 10Pa by driving vacuum pump 37.
Then, open the 1st electromagnetically operated valve 42 and the 2nd electromagnetically operated valve 43, will import in the reaction vessels 31 from gas introduction tube 38 from the fluorine gas of fluorine gas supply source 46 and 47 supplies of chlorine supply source and the mist of chlorine.At this moment, the flow separately by the 1st mass flow controller 44 and the 2nd mass flow controller 45 adjusting fluorine gas and chlorine makes the flow of fluorine gas reach 100sccm, makes the flow of chlorine reach 100～1000sccm.In addition, apply the High frequency power 700W of 13.56MHz from high frequency electric source 34.
So n type amorphous silicon film 24 on the zones beyond resist film 27,28 and the channel protection film 5 times and intrinsic amorphous silicon film 21 are removed by dry etching continuously, its etch rate is about 1500
Figure A20081009985600081
/ min.In such cases, when intrinsic amorphous silicon film 21 is removed fully, then the gate insulating film 3 that is made of silicon nitride of substrate exposes, though this gate insulating film that exposes 3 is removed by dry etching to a certain degree, its etch rate is about 400
Figure A20081009985600082
/ min.Therefore, the selection of this moment is 4 times than approximately, can be practical.And the coefficient that warms of fluorine gas is zero, the discharge capacity of gas (greenhouse gas) that help very much to suppress to warm.
Moreover, as fluorine gas supply source 46, also can supply with dilution fluorine gas with the dilution of any or multiple gases in the inert gases (being also referred to as inactive gas) such as nitrogen, helium, neon, argon.For example, can will be 500sccm (only the flow of fluorine gas is 100sccm) by the flow set of the dilution fluorine gas of 20vol% dilution also with nitrogen, be 100～1000sccm with the flow set of chlorine.
In addition, except that fluorine gas supply source 46, also the inert gas supply source can be set in addition.In addition, under above-mentioned all situations, though the flow-rate ratio of chlorine and fluorine gas all is 1～10, as long as in 1～20 scope, just can.In addition, the pressure in the reaction vessel 31 is as long as just can in the scope of 1～100Pa.
; for Drycorrosion apparatus shown in Figure 7; there is the lower electrode 32 of machined object 35 to apply high frequency to mounting; upper electrode 33 sides that ground connection is taken place easily are the negative electrode drop-out voltage of cathode side; the ion of discharge generation is used for reaction; being called as reactive ion etching (RIE), is to utilize cathode coupled dry etching.
Utilize in the cathode coupled dry etching at this, can carry out the few anisotropic etching of side etching.But in utilizing cathode coupled dry etching, the ionic bombardment of the negative electrode drop-out voltage of cathode side formation sometimes impacts transistor characteristic.Therefore, below, the situation that can reduce ion dam age is described.
Fig. 8 represents the summary pie graph of another example of Drycorrosion apparatus.In this Drycorrosion apparatus, the places different with Drycorrosion apparatus shown in Figure 7 are, make lower electrode 32 ground connection, and upper electrode 33 is connected on the high frequency electric source 34.Therefore, in this Drycorrosion apparatus, utilize the dry etching of anode coupling, compare, can reduce ion dam age with utilizing cathode coupled dry etching.
And, the transistor characteristic (Vg (gate voltage)-Id (leakage current) characteristic) when having studied the dry etching that utilizes anode coupling and having utilized cathode coupled dry etching, the result obtains result shown in Figure 9.As can be seen from Figure 9, when the anode coupling of representing with solid line, compare when being coupled with the negative electrode that dots, the projection that erects part disappears, and transistor characteristic is modified.
; in this Drycorrosion apparatus; etching condition is set at identical with above-mentioned situation; that is to say; pressure in the reaction vessel 31 are set at 10Pa, are 100sccm with the flow set of fluorine gas, are 100～1000sccm with the flow set of chlorine; apply the High frequency power 700W of 13.56MHz from high frequency electric source 34, then the etch rate of n type amorphous silicon film 24 and intrinsic amorphous silicon film 21 is about 1500
Figure A20081009985600091
/ min, the etch rate of the gate insulating film 3 that is made of silicon nitride of substrate is about 500
Figure A20081009985600092
/ min.Therefore, the selection ratio of this moment is about 3 times, can be practical.
Moreover, in the above-described embodiment, to in adopting the thin-film transistor of amorphous silicon, the situation that the intrinsic amorphous silicon film 21 that will form at the upper surface of the gate insulating film 3 that is made of silicon nitride and n type amorphous silicon film 24 are carried out dry etching is illustrated, but also is not limited to this.
For example, in the thin-film transistor that adopts polysilicon, also the polysilicon film that the upper surface at silicon nitride film can be formed carries out dry etching.In addition, in the thin film diode (TED:Thin FilmDiode) that adopts silicon, also the silicon fiml that the upper surface at silicon nitride film can be formed carries out dry etching.
In addition, the present invention is not limited to above embodiment, can advance row change freely in the scope that does not break away from aim of the present invention, improve.

Claims (16)

1, a kind of dry etching method of silicon fiml is characterized in that, the dry etching of parallel plate-type that contains the mist of fluorine gas and chlorine by employing comes silicon fiml is carried out dry etching.
2, the dry etching method of silicon fiml according to claim 1 is characterized in that, described dry etching is to utilize cathode coupled dry etching.
3, the dry etching method of silicon fiml according to claim 1 is characterized in that, described dry etching is the dry etching that utilizes the anode coupling.
4, the dry etching method of silicon fiml according to claim 1 is characterized in that, described silicon fiml is formed on the silicon nitride film.
5, the dry etching method of silicon fiml according to claim 1 is characterized in that, described mist also contains inert gas.
6, the dry etching method of silicon fiml according to claim 1 is characterized in that, the flow-rate ratio of described chlorine and described fluorine gas is 1～10.
7, the dry etching method of silicon fiml according to claim 1 is characterized in that, the flow-rate ratio of described chlorine and described fluorine gas is 1～20.
8, the dry etching method of silicon fiml according to claim 1 is characterized in that, described dry etching carries out under the vacuum atmosphere of 1～100Pa.
9, a kind of dry etching method of silicon fiml is characterized in that, it comprises following operation:
Preparation is laminated with the machined object of silicon fiml on substrate;
Machined object is moved into high-frequency electrode and opposite electrode by in the Drycorrosion apparatus of the parallel plate-type of configured in parallel, in described high-frequency electrode or opposite electrode either party of the substrate-placing of described machined object;
With described Drycorrosion apparatus decompression, in described Drycorrosion apparatus, import fluorine gas and chlorine;
Described high-frequency electrode is applied high frequency, thus the described silicon fiml of etching.
10, the dry etching method of silicon fiml according to claim 9, it is characterized in that, preparation comprises in the operation of the machined object that is laminated with silicon fiml on the substrate: form silicon nitride film on described substrate, form the machined object that is made of described silicon fiml on described silicon nitride film.
11, the dry etching method of silicon fiml according to claim 9 is characterized in that, described etching is to utilize cathode coupled dry etching.
12, the dry etching method of silicon fiml according to claim 9 is characterized in that, described etching is to utilize the dry etching of anode coupling.
13, the dry etching method of silicon fiml according to claim 9 is characterized in that, described fluorine gas uses after with inert gas dilution.
14, the dry etching method of silicon fiml according to claim 9 is characterized in that, the flow-rate ratio of described chlorine and described fluorine gas is 1～10.
15, the dry etching method of silicon fiml according to claim 9 is characterized in that, the flow-rate ratio of described chlorine and described fluorine gas is 1～20.
16, the dry etching method of silicon fiml according to claim 9 is characterized in that, carries out under the described vacuum atmosphere that is etched in 1～100Pa.
CNA2008100998563A 2007-05-30 2008-05-30 Silicon film dry etching method Pending CN101315889A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102891075A (en) * 2011-07-22 2013-01-23 东京毅力科创株式会社 Method and apparatus for forming amorphous silicon film
CN102918635A (en) * 2010-05-27 2013-02-06 应用材料公司 Selective etch for silicon films

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JP6772820B2 (en) 2016-12-22 2020-10-21 日亜化学工業株式会社 Manufacturing method of recycled circuit board and manufacturing method of light emitting element

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JP2558995B2 (en) * 1992-07-14 1996-11-27 松下電器産業株式会社 Method for manufacturing thin film transistor
JP2002190470A (en) * 2000-12-22 2002-07-05 Shibaura Mechatronics Corp Etching apparatus
JP2004098245A (en) * 2002-09-11 2004-04-02 Tokyo Electron Ltd Substrate treatment method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102918635A (en) * 2010-05-27 2013-02-06 应用材料公司 Selective etch for silicon films
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9754800B2 (en) 2010-05-27 2017-09-05 Applied Materials, Inc. Selective etch for silicon films
CN102891075A (en) * 2011-07-22 2013-01-23 东京毅力科创株式会社 Method and apparatus for forming amorphous silicon film
CN102891075B (en) * 2011-07-22 2015-11-18 东京毅力科创株式会社 The film build method of amorphous silicon film and film formation device

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