CN101300679A - 制造半导体器件的方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910045601 alloy Inorganic materials 0.000 claims description 19
- 239000000956 alloy Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 abstract description 16
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract 3
- 239000010410 layer Substances 0.000 abstract 1
- 125000004429 atom Chemical group 0.000 description 10
- 230000012010 growth Effects 0.000 description 10
- 238000002955 isolation Methods 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010790 dilution Methods 0.000 description 4
- 239000012895 dilution Substances 0.000 description 4
- 125000004437 phosphorous atom Chemical group 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000005516 deep trap Effects 0.000 description 3
- 101000830956 Homo sapiens Three-prime repair exonuclease 1 Proteins 0.000 description 2
- 102100024855 Three-prime repair exonuclease 1 Human genes 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000003723 Smelting Methods 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
本发明的方法公开了一种制造诸如横向高电压场效应(HV-FET)晶体管之类的半导体器件的更加便宜的方法。该方法包括:第一导电类型(1)的衬底,-注入第一掺杂物,从而在衬底中形成第二导电类型的第一区域(2),(并对其进行扩散),-形成第一导电类型的第二区域(3),第一区域(2)和第二区域(3)形成pn结。第二区域(3)是通过在衬底的表面(4)注入第二掺杂物而形成的表面层。-随后,表面层由在表面层(3)上形成的第一导电类型的第一外延层(5)覆盖。在对布置在彼此顶部的一个或多个区域进行制造时,可避免使用昂贵的高能量注入机(MeV),从而使成本降低。
Description
技术领域
本发明涉及一种制造半导体器件的方法,其包括:
-具有一个表面的第一导电类型的衬底,
a)注入第一掺杂物,从而在衬底中形成第二导电类型的第一区域,
b)在第一区域中注入第二掺杂物,从而形成第一导电类型的第二区域,第一区域和第二区域形成pn结。
背景技术
在US 4,754,310(图6,7)中示出了一种横向HV-FET,其在漂移区具有多个交替的p-n层。高电压FET是利用交替导电类型的多个外延层制成的。交替导电类型的第一和第二区域的交错结构形成了高电压晶体管内的漂移区,其承载了出现在耗尽的漂移区的高电压。这样,多个并行通道有助于漂移区的电流流过并且使漂移区的导通电阻变小,同时,如果电荷平衡正确,那么Resurf原理允许高的击穿电压。该方法的缺点在于,从上表面到深入的各个层的访问有些困难,对此,在应用中使用了V形凹槽。另一个缺点就是,由于外延的使用,不能精确地控制漂移区中各层的掺杂物的相当关键的剂量。
在US 6,509,220中,公开了一种用于制造在漂移区具有一个或多个导电沟道的高电压绝缘栅场效应晶体管的方法。在这种应用中,通过在第二导电类型的深阱或者外延层中进行第一导电类型的掺杂物的连续的深度注入,以便形成布置在不同垂直深度的第一多掩埋层,通过此方法形成了延伸的漏极中的导电沟道。第二导电类型的深阱或外延层被形成在第一导电类型的衬底中或在其上。可在深阱或第一外延层上形成第二导电类型的第二外延层,并且对第一导电类型的深度注入进行重复以形成堆叠的第二多掩埋层,第二多掩埋层与第一多掩埋层为并行关系。延伸的漏极中的堆叠的p-n层形成了HVFET的漂移区。当HVFET处于ON模式,漂移电流在源极和漏极之间流动。如果所述漂移区处于OFF模式,那么漂移区被耗尽。
已知方法的缺点是,对于布置在不同垂直深度的第一导电类型的层的形成,需要高能量的注入机。MeV范围的高能量注入机是十分贵的,并且它们在半导体生产线上并不常见。此外,由于高能量离子引起的注入破坏会产生可靠性问题。
发明内容
本发明的目的尤其是提供比现有技术便宜的在第一段中提到的类型的器件的制造方法。
根据本发明的方法的目的是这样实现的,第一导电类型的第二区域是通过在衬底的表面注入第二掺杂物而形成的表面层。随后,表面层被表面层上的第一导电类型的外延层覆盖。
本发明基于这样的想法,第一导电类型的第二区域是通过在表面进行相对较低能量的注入而形成的,随后在该表面层上进行同样的第一导电类型的外延层的外延生长。表面上的注入和外延生长的结合避免了若干MeV的高能量注入的使用。实现了每个晶片成本的降低。通过省略MeV范围的高能量注入,该方法可以应用在传统的晶片制造工厂中。这在灵活性上具有显著的优势,于是可以在全世界范围不同的晶片制造工厂中进行半导体器件制造。
此外,由于不需要高能量注入来在衬底的垂直方向上的不同深度形成一个或多个层,所以减少了注入破坏。于是可以获得更可靠的器件。
此外,第一导电类型的外延层的使用使对第一导电类型的其它层的深入访问以及对衬底的深入访问变得更容易。
在现有技术US 4,754,310中,漂移区中的p-n层仅由外延生长形成。在已知方法中,外延生长期间的掺杂物浓度不能被很好地控制,特别是在基于RESURF(降低表面电场)原理的高电压器件中使用的相对较低的掺杂物浓度。
在根据本发明的方法中,用第三掺杂物对第一导电类型的第一外延层进行注入,从而在第一外延层中形成第二导电类型的第三区域,第三区域和第二区域形成pn结。通过以注入(例如n型)的方式来超出(过掺杂)第一外延层的(相对低的)掺杂浓度(例如p型),可以改进对掺杂浓度的控制。该方法可以对用于RESURF目的的p-n层中的掺杂原子进行严格的控制。在过早的内部击穿发生之前,如果反向偏置电压下的p-n层被完全耗尽,那么就可获得RESURF。耗尽区对这些层的p和n两部分的掺杂浓度均很敏感。所以,为了获取完全耗尽的p-n层,并同时不会超出适于击穿的电场的关键值,对掺杂浓度的良好控制是很重要的。
在本发明的适合于RESURF的特定优选实施例中,第一外延层是高欧姆的。这就意味着,在外延生长期间,引入了相对较低的掺杂原子浓度。高欧姆的外延层可与相反导电类型的控制良好的离子注入以及随后的可选扩散一起使用。由于在高欧姆外延层中的掺杂物浓度仅仅是很小的,所以不需要许多掺杂原子来补偿这些微量。这样,可以在低浓度范围中对很低的掺杂浓度进行非常好的控制。特别地,可以轻易地获得具有很好控制的低于5×1016at/cm3的掺杂浓度。另一方面,第一外延层的一些掺杂对于器件隔离和与体/衬底之间的接触是很有用的,如下文中所示。
以与外延生长结合的表面注入,以及随后用相反导电类型的掺杂物进行的外延层的过掺杂的方式来进行的交替p-n层的形成过程可以被重复一次或多次。这样就可以在衬底上形成多个堆叠的p-n层。通过在HVFET的延伸漏极中应用这些堆叠的p-n层,优势是很显著的:通过增加第二类型的层的数目,可降低导通电阻(Ron)。
优选地,第一导电类型是p型。与p型外延层结合的p型衬底的使用使电绝缘n型晶体管的制造变得容易。结隔离比深沟槽隔离更容易且更便宜。当p型衬底与n型外延层结合时(如现有技术公开的那样),可选地采用深沟槽隔离。
优选地,第一和其它外延层的厚度小于4.5微米。通过选择不太厚的外延层,将相反导电类型的掺杂物原子扩散至第一外延层内从而对该外延层中的掺杂物浓度进行过掺杂,这仅仅需要有限的温度预算。外延层越薄,那么在外延层中进行掺杂物原子扩散所需要的热预算越小,并且在过掺杂的外延层中对掺杂浓度的控制更好。如同已经提到的那样,在RESURF器件中对掺杂浓度的良好控制是很重要的。
第一和其它外延层的生长优选地在低于1150℃的温度下完成。第一外延层在第一导电类型的高度掺杂表面层上生长。为了限制掺杂原子在第一外延层的外延生长工艺开始时从表面层偏聚或蒸发,温度优选地低于1150℃。降低掺杂物原子(尤其是硼原子)的偏聚的替换方式是加速EPI反应器,并且省略所有通常所完成的其它温度步骤,例如H2烘烤或熔炉退化步骤。
为了形成表面层,第二掺杂物的注入能量优选地低于350keV。
上述制造方法可以有利地用于高电压横向MOSFET或双扩散MOS(LDMOS)晶体管中。在LDMOS中,源极被体区围绕,两者都与多晶硅栅极自对准。延伸的漏极包括多个布置在彼此顶部的p-n层。为了具有允许电流流经第二类型的所有漂移层的漂移电流通道,还希望通过对源极和漏极侧的所有其它垂直布置的第一导电类型的层进行掩模来阻挡。例如,在第二区域(例如p型的)留下开口,从而使第一区域与第三区域连接起来并与源极和漏极连接。与LDMOS晶体管的源极和漏极区域的良好连接对于流经沟道的最佳电流是很重要的,并且对于获取低导通电阻也是很重要的。
对于高电压应用,横向HV-FET或HV-LDMOS晶体管可以具有互相交叉的指状结构。如果在整个手指宽度上形成第一导电类型的第二区域(和/或更高级别)与衬底或MOS阱或体区之间的局部接触,那么就可以获得特定优选实施例。这个局部接触允许快速切换时的更快的充电和放电。
在其它优选实施例中,漂移区域中的第一导电类型的第二区域(和/或更高级别)可在源极下面延续,从而经由第一导电类型的一个或多个外延层使阱或者体区与衬底局部接触。
由于外延之后的体工艺,以及需要第二类型的层之间的垂直连接,所以在产生了p-n Resurf层之间的非常多的掺杂补偿的外延之后需要一个合理的热预算。所以,在不存在对第一导电类型的第二区域进行补偿的位置,需要在源极和漏极的n连接区域中使用掩模稀释的掺杂。所以,第一区域在横向方向上可包括彼此分开的多个范围,这在下文中将进行说明。
附图说明
参考下文中描述的实施例,本发明的这些和其它方面将得到说明并变得明显。
附图中:
图1示出了根据本发明的通过利用p型外延形成第一和第二区域来制造半导体器件的方法的第一实施例(图1a)。第一和第二区形成之后形成第三区域(例如,在HVFET的延伸的漏极漂移区中实现),如图1b所示。
图2示出了具有由第二导电类型的第一和第三区域形成的两个漂移电流通道(双通道)的延伸漏极HVFET的示意截面图。
图3示出了图2中的HV-FET的截面图,其中,第一区域在横向方向上包括多个范围。不存在用以补偿第一区域的掺杂浓度的第二区域。
图4示出了对于图3所示的HV-FET,作为深度函数的漂移区中的仿真电流。
图5示出了图3所示的HVFET击穿时的仿真电势分布。
图6示出了根据本发明的用于制造漂移区的方法的另一实施例,此处是用于制造具有3个并行通道(三通道)的延伸漏极漂移区。
图7示出了具有三个漂移电流通道(三通道)的延伸漏极LDMOST的示意截面图,其在衬底中具有交替类型的5个区域。
图8示出了图7中的HV-FET的截面图,其现在具有第一和第三区域的优选掩模稀释,不存在用于补偿的第二区域。
图9示出了垂直方向上的图8中的器件的仿真对应掺杂物分布。
图10示出了对于图8中的LD-MOSFET,作为深度的函数的漂移区中的仿真电流。
图11示出了图8所示的LDMOST击穿时的仿真电势分布。
图12示出了源极和漏极与各种n型区域连接的三通道LDMOST的截面图(图12a)。图12b示出了第一导电类型的交替层(RP和RP2)经由第一和第二外延层与衬底和体区接触的同一个三通道LDMOST的截面图。
具体实施方式
图1示出了根据本发明的方法的第一优选实施例。P型Si衬底1被n型掺杂物原子掩模注入以形成第一区域2。在该示例中,采用了具有注入能量为100keV的P原子,并且剂量大约为6×1016at/cm2。对于RESURF,注入剂量优选地处于1×1012和1×1013at/cm2之间的范围。1150℃下的540分钟的高温扩散步骤使得n型掺杂原子更深进入衬底,从而形成了深n型区域2(在此标为深Resurf n,DRN,参见图1A)。
通过在衬底1的表面4(图1B)上采用掩模来注入诸如硼或铟之类的p型掺杂物,从而形成第二区域3。此处,硼是在100-180keV的能量下注入的,并且其剂量大约为6×1012at/cm2。对于Resurf,注入剂量优选地处于1×1012和1×1013at/cm2之间的范围。因此,表面4上形成了p型层。作为选择,硼掺杂原子可被扩散,或者在下一步的外延生长期间被激活。p型第二区域3的掺杂分布在此表示为Resurf p,RP。
在表面4上,厚度为2至4μm的p型Si外延层5在1150℃下外延地生长(图1C)。
接下来,利用100至300keV的剂量大约为1.4×1012at/cm2的P原子对该层进行注入,并且可选择地对其进行扩散以提供具有n型掺杂物的第三区域6(在此标为DRN2)(图1D)。在工艺完成之后,DRN和RP层中的净剂量均约为2×1012at/cm2,在DRN2层中约为1×1012at/cm2。那么第三区域(DRN2)的处理后的薄层电阻大约为6kOhm/square。优选地,用于第三区域的注入剂量在0.5×1012和1×1013at/cm2之间的范围。
根据本发明的方法并不限于Si衬底。可以使用任何半导体衬底,例如SiC、Ge、SiGe、InP、GaAs、GaN等。只要pn结能在半导体衬底中形成,那么就可以适用RESURF的原理。
深Resurf N(DRN)和Resurf P层(RP)(顶部具有p型外延层,随后进行n型注入(形成DRN2))的形成可有利地用于诸如双极晶体管、IGBT、横向MOSFET和DMOSFET之类的多种半导体器件的制造。
图2示出了在p衬底1上具有延伸的漏极的横向双扩散MOSFET的特定优选示例的示意截面,其在源极(S)和漏极(D)之间包括两个具有中间p层3(RP)的n型漂移电流通道2(DRN)和6(DRN2)。
在形成如图1b所示的3层(1(n)、2(p)、3(n))以后,横向HV-MOSFET工艺继续。形成局部场氧化物20,其优选地具有厚度约为1μm的Locos(区域性硅片氧化);形成栅极氧化物21和n+掺杂的多晶硅栅极22,其在源极侧23具有场板,可选的在漏极侧24也有场板。通过注入(优选地与多晶硅栅极自对准)和随后扩散形成p型体和横向沟道区(优选地为DMOS类型)25,随后注入n+源极26(优选地与多晶硅栅极自对准),并注入n+漏极27(优选地与Locos场氧化物自对准)。通过沉积形成金属间电介质层,优选地通过约为1μm厚的TEOS或LTO氧化物形成,随后为具有场板28的源极、栅极(未示出)和具有场板29的漏极进行开接触窗口、沉积和金属化刻蚀。这由同样能提高HV稳定性的电介质划痕保护所覆盖,其中制备了用于键合焊盘的开口。
在导通状态,电子从源极和MOS沟道经由两个n沟道漂移区(双通道)流向漏极。现在,HV-MOSFET的总导通电阻(Ron)由并联的两个电阻组成;这就大大降低了器件的导通电阻。HV DMOS晶体管在HV电源中被用作开关。该开关允许在100至500kHz下的功率转换。对于这些功率开关,导通电阻(Ron)和击穿电压(BVds)值是非常主要的参数。
优选地,源极和漏极侧的n连接被设计成具有通过掩模图案而获得较低的掺杂浓度,如图3所示(DRN-2a、DRN-2b)。由于两个n区域(没有补偿p区域)的掺杂都相当高,所以将第一区域2分成多个范围12是需要的。
外延生长之后,第一外延层5最初是p型的。在P原子扩散以后,形成了作为n阱6(DRN2)的第三区域。该n阱在第二区域3和第一外延层5的上表面之间延伸。该n阱与第二区域(RP)形成了一个pn结。第一区域(DRN)的n型P原子补偿了第二区域(RP)的一定量(大量)的p型浓度。在本示例中,DRN和RP层的约65%的掺杂浓度被补偿。在用作RESURF时,p-n层的掺杂浓度是很关键的。所以,考虑到热预算,B和P两者的注入剂量是很关键的。
第一导电类型的外延的使用有利于源极下直至体区的适当的器件隔离。注意,n区域是相对较深的,而p区是相对较浅的。如在现有技术US 6,509,220中所公开的,对于具有较浅的体扩散的第二导电类型的外延区,更难实现较浅的RP层。这同样适用于使用较多交替层(参见下文)的情况。
图2的具有延伸的漏极的HV LDMOST包括第一区域N层(DRN)、第二区域P层(RP),其上存在n阱(DRN2),这个HV LDMOST可利用上述方法进行制造。
图3示出了图2的器件的截面图,没有第二区域14的地方上,在靠近源级并优选地位于漏极16的第一区域中具有较低的掺杂。虚线表示外部扩散边缘。所以,第一区域2在横向上被分成多个范围12。
图4示出作为通过图3所示的LDMOS晶体管的深度的函数的仿真电流。该仿真电流线是在Vds=0.1V时计算出来的。
流过LDMOS的电流取决于各层的薄层电阻的比值。对于NW2,计算出来的薄层电阻为6.20kOhm/sq;对于BN层,计算出来的薄层电阻为3.37kOhm/sq。于是,35%的电流流经NW2,而65%的电流流经BN层。对于55微米的Locos长度(或者漂移长度),可以获得典型数值Ron*A=9Ohm.mm2,其中,A是器件的有效面积。
在图5中示出了,在漂移长度为55微米时,仿真出来的击穿电压BVds是692V。因此,仿真出来的LDMOS很适合高压应用。通过增大漂移长度(例如增大至65μm),击穿电压也增大了。当然,代价是增大了导通电阻,于是导致Ron*A=12.4Ohm.mm2。
图6示出了利用根据本发明方法的漂移区的第二优选实施例,现在是针对制造具有3个并行通道的延伸漏极漂移区域。使用掩模形成第一n型区域2(DRN)和第二p型区域3(RP),随后在界面4上形成现在稍微较厚的p型外延5和采用更多能量和扩散进行掩模注入形成第三n型区域6(图6D,DRN2),之后,掩模注入形成p型第四区域7(图6E,RP2)。此后,在界面8上,生长出第二p型外延层9(图6F),其注入了覆盖的n型层(10),从而获取了n型第五区域(图6G,DRN3)。
图7中的LDMOS晶体管的示意图示出了根据本发明的方法是如何在三通道LDMOS器件中应用的。同样,在源级和漏极的n层之间的垂直连接的位置,且没有补偿p层的地方,需要通过掩模图案进行的n剂量的一些稀释,如图中所示(DRN-2a,DRNN-2b;DRN2-6a、DRN2-6b)。现在,对于适当的器件隔离以及交替的p型层接地,p型外延的使用允许RP-3a、RP2-7a和体/衬底之间更容易的连接。
在导通状态,现在存在三个n型漂移电流通道(DRN,DRN2,DRN3)。这三个n型区域被两个p型区域(RP和RP2)分开。
图8示出了图7的器件的截面图,其在没有第二区域的位置上的第一区域中(靠近源级并且优选地位于漏极)具有降低的掺杂。虚线表示外部扩散边缘。
图9示出了作为图8的三通道LDMOS的深度的函数的仿真掺杂浓度。点线示出了活性磷浓度(n型),虚线示出了活性硼浓度(p型)。实线指的是作为深度的函数的净掺杂浓度。
图10示出了作为深度的函数的三通道LDMOS中的仿真电流。在Vds=0.1V时显示了良好的电流分布。n型层的特定薄层电阻为:NW2=6k/sq,NW=3.5k/sq,以及BN=3.62k/sq。流经这些n型层的电流取决于薄层电阻的值。流经NW2的电流百分比为20%,流经NW的电流百分比为40%,并且流经BN的电流百分比为40%。在Vds=0.1V、Vgs=14V时提取出来的针对三通道LDMOST的导通电阻为Ron*A=5.7Ohm.mm2。
图11示出了相应的击穿电压的仿真。对于55μm的漂移长度,计算出来的击穿电压为652V。通过将BN中的电场线不太快地移动至漏极,击穿电压还可能进一步增大。因此,BN注入剂量(在此为6.5×1012at/cm2)被稍微调整以获得大约为720V的击穿电压BVds。
图12示出了三通道LDMOST的实施例,其被布置成适合于快速切换。三通道LDMOST(图12a)具有指状结构。“源极的N连接”包括DRN和DRN2层中的稀释的n区域14,如图8所示。
在手指的整个宽度上,RP/RP2通过“源极的N连接”局部地延续(图12b)。所以,在漂移区域的RP/RP2层和体/衬底之间形成了局部接触。局部接触在快速切换时允许更快的充电和放电。局部接触仅仅降低了有效功率(单位W)的1-2%。
通过采取一个或多个下述措施,可以获得LDMOST的进一步改进实施例:
在源极指尖(“头部”),n层可被些许缩回和/或掩模稀释,并且p层保持存在更多,从而使掺杂过渡和结曲率的效应更平滑。这些源极指尖不是有效的(不是源极),并且S至D的距离较大。
同样,在漏极指尖(“头部”),S至D的距离可较大,并且场板被拉伸。漏极指尖周围没有源极,从而限制了该指尖处的电流浓度。
在集成电路上,根据本发明的方法可以和其它晶体管的制造相结合。上述LDMOST可以与HV-NJFET结合,可以与CMOS电路和/或HV-PMOS结合。可能需要对LDMOST进行少许修改。
例如,在漏极指尖可包括HV-NJFET,这对于低电压(LV)控制部分或芯片的启动电流尤其有用。
还可以集成CMOS电路。在这种情况下,围绕源极的体区可由在应用多晶栅之前通过注入和扩散形成的P阱代替,该P阱还可用于LV NMOS和CMOS。
同样,集成的HV-PMOS器件也是可行的。例如,这可用于感测在未隔离的主要(切换)侧的隔离的输出(次要)。
应该注意的是,上述实施例说明了而不是限制了本发明,并且本领域技术人员将能在不脱离所附权利要求的范围的情况下设计出多种替换实施例。在权利要求中,括号中的任何标号都不应该被解释为限制权利要求。动词“包括”及其词性变化的使用并不排除除权利要求中所陈述的元素和步骤之外其它元素和步骤的存在。单个元素前的“一个”和“一种”的使用并不排除多个该元素的存在。事实仅仅在于,在相互不同的从属权利要求中陈述的某些方法并不表示这些方法的结合不能用作优选实施例。
Claims (11)
1.一种制造半导体器件的方法,其包括:
-具有一个表面(4)的第一导电类型(1)的衬底,
a)注入第一掺杂物,从而在所述衬底中形成第二导电类型的第一区域(2),
b)在所述第一区域中注入第二掺杂物,从而形成所述第一导电类型的第二区域(3),所述第一区域(2)和所述第二区域(3)形成pn结,
其特征在于,所述第二区域(3)是通过在所述衬底的所述表面(4)注入所述第二掺杂物而形成的表面层,并且随后所述表面层通过以下步骤被覆盖
c)在所述表面层(3)上形成所述第一导电类型的第一外延层(5)。
2.如权利要求1所述的方法,其特征在于,d)所述第一外延层被注入第三掺杂物,从而在所述第一外延层(5)中形成所述第二导电类型的第三区域(6),在所述第三掺杂物扩散之后所述第三区域贯穿所述第一外延层(5),于是所述第三区域与所述第二区域(3)形成pn结。
3.如权利要求2所述的方法,其特征在于,e)第四掺杂物被注入所述第三区域以形成所述第一导电类型的第四区域(7),所述第三区域(6)和所述第四区域(7)形成pn结。
4.如权利要求1、2或3所述的方法,其特征在于,通过将步骤c)、d)和e)再重复n次,在所述衬底上形成了多个堆叠的pn结,其中n为整数,于是所述第一外延区被更新了n次,所述第三区域被更新了n+1次,并且所述第四区域被更新了n+2次。
5.如上述权利要求任一所述的方法,其特征在于,所述第一导电类型为p型,并且所述第二导电类型为n型。
6.如权利要求1和4所述的方法,其特征在于,所述外延层的厚度小于4.5μm。
7.如权利要求1、4或6所述的方法,其特征在于,所述外延层在低于1150℃的温度下生长。
8.如权利要求1所述的方法,其特征在于,所述掺杂物的注入能量低于350keV。
9.如上述权利要求任一所述的方法,其特征在于,所述半导体器件是FET,并且源极区域(S)被形成为所述第二导电类型,漏极区域(D)被形成为所述第二导电类型,并且在注入所述第一掺杂物和所述第二掺杂物以形成所述第一区域(2)和所述第二区域(3)期间使用了掩模,所述第一区域和所述第二区域被定位在所述源极区域和所述漏极区域之间,形成了延伸的漏极区域。
10.如权利要求9所述的方法,其中所述第一区域(2)包括在横向上彼此分开的多个范围(12)。
11.如权利要求9或10所述的方法,其特征在于,所述半导体器件是高电压FET,所述第一导电类型的体区(9)在所述源极区域周围形成,所述体区(9)经由与所述第一导电类型的所述第二区域(2)的局部连接(20)与所述衬底(1)连接。
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EP1946378A1 (en) | 2008-07-23 |
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EP1946378B1 (en) | 2012-12-12 |
JP2009515332A (ja) | 2009-04-09 |
US20080093641A1 (en) | 2008-04-24 |
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