CN101299609B - Phase discriminator, phase demodulation method and phase-locked loop - Google Patents
Phase discriminator, phase demodulation method and phase-locked loop Download PDFInfo
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Abstract
The invention discloses a phase discriminator for receiving the reference clock signal and the local pulse clock signal, including a frequency division module for performing the two divided-frequency to the received reference clock signal and outputting the two divided-frequency signal; a time delay module, for delaying the two divided-frequency signal and outputting the time delay signal, wherein the delay time is a local pulse clock period; a phase discrimination module for receiving the two divided-frequency signal and the time delay signal using the local pulse clock signal as the count clock, counting the local pulse clock signal in the time slot of the high level pulse width or the low level pulse width and starting counting again. The invention also discloses a phase discrimination method and a locking ring. The phase discriminator and the phase discrimination method have no specific requirement on the input signal frequency, directly judge the correctness of the phase discrimination result, with strong phase locked loop generality.
Description
Technical field
The present invention relates to the satellite simultaneous techniques of the communications field, relate to a kind of phase discriminator, phase detecting method and phase-locked loop especially.
Background technology
At present, digital communication network is according to user's needs, can provide from general service to intelligent value-added service, from the speech business to data, the multiple different application business of image synthesis business etc., along with the increase of all kinds business, multiple business and the requirement of depositing system synchronization just seem more strict.
Owing to use synchronous satellite system to have as timing reference input that relative cost is low, the precision advantages of higher, thus at present with various satellite synchro systems as timing reference input extract clock carry out phase-locked, thereby it is more common to reach the method that system synchronization requires.But, but there is different requirements in each country to the satellite of system synchronization at present, for example, the U.S. wishes to use global positioning system (Global Positioning System, GPS) satellite reception technique, Russia wishes to use GLONASS (Global Navigation Satellite System, GLONASS) technology, and China has " Big Dipper " satellite simultaneous techniques, thus, for equipment manufacturers, just require the equipment end clock system can the compatible complicated circuit that designs according to different satellite systems, also want can prevent to switch between different satellite systems the phase place kick that causes, this will cause the phase-locked loop circuit design complicated, the cost and the design cycle of improving product.
In the prior art, the phase-locked loop circuit theory diagram that from the satellite synchro system, extracts clock as shown in Figure 1, phase place degeneration factor, wherein a f that it is made up of phase discriminator, loop filter and voltage controlled oscillator
0Be the clock signal of satellite synchro system input, f
1Be the signal behind N frequency division of voltage controlled oscillator output signal frequency process, this phase-locked loop can be realized reference clock frequency f
0With VCXO output frequency f
1Unanimity.
In foregoing circuit, phase discriminator is the important component part of phase-locked loop, and its effect is the phase difference of determining between two input signals.The characteristic of phase discriminator can be used Mathematical Modeling u
d(t)=k
dF[θ
e(t)] represent k in the formula
dBe the gain coefficient of phase discriminator, θ
e(t)=θ
1(t)-θ
2(t), represent the phase difference between two input signals, function f [] expression phase characteristic, the output voltage u of its reflection phase discriminator
d(t) with the relation of phase difference.
Development along with digital circuit technique, digital phase discriminator is because it not only has advantages such as reliability height, volume is little, price is low, and the direct current null offset, the device that have overcome the simulation phase discriminator are saturated and be subject to shortcomings such as power supply and variation of ambient temperature, also has processing capability in real time to discrete sample value, thereby range of application more and more widely, become the direction of Phase Lock Technique development at present.
In the prior art, digital phase discriminator mainly contains Fig. 2, type and phase frequency detector (Phase-Frequency Detector shown in Figure 3, PFD), XOR gate (Exclusive OR, XOR) phase discriminator or JK flip-flop phase discriminator, but in the above-mentioned phase discriminator, first three plants phase discriminator needs the frequency input signal just can phase demodulation when 1KHz is above, and back two kinds of phase discriminators have strict demand to the duty ratio of frequency input signal, have only duty ratio be 50% o'clock identified result just correctly; And above-mentioned all phase discriminators all require two frequency source frequencies importing identical.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of phase discriminator, phase detecting method and phase-locked loop, makes phase discriminator not have specific (special) requirements to the frequency of input signal, and phase-locked loop can be applicable to any satellite synchro system.
For this reason, the invention provides a kind of phase discriminator, receive reference clock signal and local pulse clock signal, this phase discriminator comprises:
Frequency division module carries out 2 frequency divisions to the described reference clock signal that receives, and exports 2 fractional frequency signals;
Time delay module is delayed time described 2 fractional frequency signals, the output time delayed signal, and be a described local pulse clock cycle time of delay;
The phase demodulation module comprises first judge module, second judge module, the 3rd judge module, the 4th judge module, high level counting module and low level counting module, wherein:
First judge module receives described 2 fractional frequency signals, judges the level state of described 2 fractional frequency signals, and with judged result as the level state gating signal, send to described second judge module and the 3rd judge module;
Second judge module when to receive the level state gating signal be high, when current high level counts value during greater than predetermined high level number of times higher limit, then sends the higher limit asserts signal to the high level counting module; When current high level counts value is less than or equal to predetermined high level number of times higher limit, send the high level count signal to the high level counting module;
The high level counting module, receive the high level count signal after, carry out the high level counts and add 1 counting, and store current high level counts value; When receiving the higher limit asserts signal, current high level counts value is set to high level number of times higher limit;
The 3rd judge module receives the level state gating signal when low, when current low level counts value during less than predetermined low level number of times lower limit, then sends the lower limit asserts signal to the low level counting module; When current low level counts value is greater than or equal to predetermined low level number of times lower limit, send the low level count signal to the low level counting module;
The low level counting module, receive the low level count signal after, carry out the low level counts and add 1 counting, and store current low level counts; When receiving the lower limit asserts signal, current low level counts is set to low level number of times lower limit.
Further, this phase discriminator also comprises:
Phase demodulation value memory cell is used for the phase demodulation value of described phase demodulation module output is stored as current phase demodulation value.
This phase discriminator also comprises:
Whether effectively whether the 5th judge module, the phase demodulation value that is used to judge described phase demodulation module output in the scope of setting, and according to judged result output phase demodulation value index signal.
In the described phase demodulation module, set the counts threshold value further, when current counts value was not in the threshold value scope of setting, current counts value was set to predetermined value.
Described local pulse clock signal is the required drive clock output signal of external circuit.
The present invention also provides a kind of phase detecting method, comprising:
A. the described reference clock signal that receives is carried out 2 frequency divisions, obtain 2 fractional frequency signals;
B. described 2 fractional frequency signals are delayed time, the output time delayed signal, be a described local pulse clock cycle time of delay;
C. receive described 2 fractional frequency signals and time delayed signal, with described local pulse clock signal is counting clock, in the high level pulsewidth of described 2 fractional frequency signals or low-level pulse width in the time period, local pulse clock signal is counted, and when described time delayed signal and 2 fractional frequency signal level states are inequality, export this time counts value as the phase demodulation value, and restart counting.
Further, this method comprises:
Set the counts threshold value,
And described step c comprises further: when current counts value was not in the threshold value scope of setting, current counts value was set to predetermined value.
Described step c comprises further:
In the high level pulsewidth of 2 fractional frequency signals, the local pulse clock signal that receives is added 1 counting as the counts value, when current counts value during greater than predetermined high level number of times higher limit, current counts value is set to high level number of times higher limit, in the low-level pulse width of 2 fractional frequency signals, the counts value in the above-mentioned high level pulsewidth is set to 0;
In the low-level pulse width of 2 fractional frequency signals, the local pulse clock signal that receives is added 1 counting as the counts value, when current counts value during less than predetermined low level number of times lower limit, current counts value is set to low level number of times lower limit, in the high level pulsewidth of 2 fractional frequency signals, the counts value in the above-mentioned low-level pulse width is set to 0.
Again further, this method also comprises:
Judge the phase demodulation value whether in the scope of setting, and make the whether effectively indication of phase demodulation value according to judged result.
The present invention also provides a kind of phase-locked loop, comprise: satellite clock receiving element, local clock generation unit and phase discriminator, described phase discriminator is used for according to the satellite clock receiving element that receives output pps pulse per second signal and local clock generation unit output local clock signal, determines and stores phase demodulation value between current input pps pulse per second signal and the pulse clock signal; It is characterized in that:
Described phase discriminator comprises further:
Frequency division module carries out 2 frequency divisions to the described reference clock signal that receives, and exports 2 fractional frequency signals;
Time delay module is delayed time described 2 fractional frequency signals, the output time delayed signal, and be a described local pulse clock cycle time of delay;
The phase demodulation module comprises first judge module, second judge module, the 3rd judge module, the 4th judge module, high level counting module and low level counting module, wherein:
First judge module receives described 2 fractional frequency signals, judges the level state of described 2 fractional frequency signals, and with judged result as the level state gating signal, send to described second judge module and the 3rd judge module;
Second judge module when to receive the level state gating signal be high, when current high level counts value during greater than predetermined high level number of times higher limit, then sends the higher limit asserts signal to the high level counting module; When current high level counts value is less than or equal to predetermined high level number of times higher limit, send the high level count signal to the high level counting module;
The high level counting module, receive the high level count signal after, carry out the high level counts and add 1 counting, and store current high level counts value; When receiving the higher limit asserts signal, current high level counts value is set to high level number of times higher limit;
The 3rd judge module receives the level state gating signal when low, when current low level counts value during less than predetermined low level number of times lower limit, then sends the lower limit asserts signal to the low level counting module; When current low level counts value is greater than or equal to predetermined low level number of times lower limit, send the low level count signal to the low level counting module;
The low level counting module, receive the low level count signal after, carry out the low level counts and add 1 counting, and store current low level counts; When receiving the lower limit asserts signal, current low level counts is set to low level number of times lower limit.
Compared with prior art, the present invention has following remarkable advantage:
(1) in phase discriminator, phase detecting method and the phase-locked loop proposed by the invention, is reference, input signal is carried out 2 frequency divisions, make the duty ratio of frequency input signal no longer include strict requirement by the pulse clock signal rising edge that produces with the local clock generating unit;
(2) in phase discriminator proposed by the invention, the phase detecting method, count by the paired pulses clock signal and to obtain the phase demodulation value, thereby input clock signal need not have identical frequency;
(3) in the phase-locked loop proposed by the invention, owing to introduced the satellite clock receiving element, it can all convert the synchronizing signal of various satellites to pps pulse per second signal, and therefore, this phase-locked loop versatility is stronger, can satisfy the needs of various satellite synchro systems;
(4) phase discriminator and phase detecting method proposed by the invention can directly be judged the correctness of identified result, and need not be by other supplementary means;
(5) phase discriminator proposed by the invention can utilize CPLD (ComplexProgrammable Logic Device, CPLD), field programmable logic device (FieldProgrammable Gate Array, FPGA) or application-specific IC (Application SpecificIntegrated Circuit, ASIC) etc. hardware circuit realizes that flexibility is higher.
Description of drawings
Fig. 1 is the phase-locked loop circuit theory diagram that the satellite synchro system is extracted clock in the prior art;
Fig. 2 is the schematic diagram of first kind of phase discriminator in the prior art;
Fig. 3 is the schematic diagram of second kind of phase discriminator in the prior art;
Fig. 4 is the theory diagram of phase discriminator in the embodiment of the invention;
Fig. 5 is the flow chart of phase detecting method in the embodiment of the invention;
Fig. 6 is the signal relation figure in phase discriminator and the phase detecting method in the embodiment of the invention;
Fig. 7 is the phase-locked loop circuit theory diagram that the satellite synchro system is extracted clock in the embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is done to introduce further, but not as a limitation of the invention.
With reference to shown in Figure 4, a kind of phase discriminator, its local oscillator signal of telecommunication with the output pulse clock signal is connected, comprise: frequency division module, first judge module, second judge module, the 3rd judge module, the 4th judge module, the 5th judge module, high level counting module, low level counting module, time delay module, phase demodulation value memory module, wherein:
Frequency division module carries out 2 frequency divisions to the reference clock signal 1S_sig that receives with its rising edge, obtains 2 fractional frequency signal 2S_sig, and this 2 fractional frequency signal 2S_sig is offered first judge module, the 4th judge module and time delay module;
First judge module, with the pulse clock signal out_sig rising edge of local oscillator output be with reference to the time, when the 2 fractional frequency signal 2S_sig that receive are high level, then send the high-level strobe signal and send low level counting reset signal to the low level counting module to second judge module, when the 2 fractional frequency signal 2S_sig that receive are low level, then send the low level gating signal and send high level counting reset signal to the high level counting module to the 3rd judge module;
Second judge module, after receiving the high-level strobe signal, pulse clock signal out_sig rising edge with local oscillator output is reference, when high level counts value cont_high greater than predetermined high level number of times higher limit up_val, send the higher limit asserts signal to the high level counting module, when high level counts value cont_high is less than or equal to predetermined high level number of times higher limit up_val, send the high level count signal to the high level counting module;
The high level counting module, set and store the initial value of high level counts cont_high, after receiving the high level count signal, carry out high level counts value cont_high and add 1 counting, and store current high level counts value cont_high, when receiving the higher limit asserts signal, current high level counts value cont_high is changed to high level number of times higher limit up_val, when receiving high level counting reset signal, current high level counts value cont_high is changed to 0;
The 3rd judge module, after receiving the low level gating signal, pulse clock signal out_sig rising edge with local oscillator output is reference, as low level counts value cont_low during less than predetermined low level number of times lower limit down_val, then send the lower limit asserts signal to the low level counting module, when low level counts value cont_low is greater than or equal to predetermined low level number of times lower limit down_val, then send the low level count signal to the low level counting module;
The low level counting module, set and store the initial value of low level counts value cont_low, after receiving the low level count signal, carry out low level counts value cont_low and add 1 counting, and store current low level counts value cont_low, when receiving the lower limit asserts signal, current low level counts value cont_low is changed to low level number of times lower limit down_val, when receiving low level counting reset signal, current low level counts value cont_low is changed to 0;
The 4th judge module, pulse clock signal out_sig rising edge with local oscillator output is reference, when the 2 fractional frequency signal 2S_sig that receive are low level, and when time delayed signal 2S_sig_delay is high level, read the current high level count value cont_high in the high level counting module, and send in the phase demodulation value memory module, when the 2 fractional frequency signal 2S_sig that receive are high level, and when time delayed signal 2S_sig_delay is low level, read the current low level count value cont_low in the low level counting module, and send in the phase demodulation value memory module;
The 5th judge module, pulse clock signal out_sig rising edge with local oscillator output is reference, when phase demodulation value cont_val whether less than predefined high level number of times higher limit up_val and greater than predefined low level number of times lower limit down_val, then export effective value 1, show that this phase demodulation value cont_val is effective, otherwise output invalid value 0 shows that this phase demodulation value cont_val is invalid;
Time delay module, pulse clock signal out_sig rising edge with local oscillator output is reference, with the reference clock signal 1S_sig pulse clock cycle of time-delay that receives, obtain time delayed signal 2S_sig_delay, wherein, the described clock cycle is the clock cycle of local oscillator output pulse clock signal out_sig;
Phase demodulation value memory module, receive counts after, it is stored as current phase demodulation value cont_val.
In above-mentioned phase discriminator, frequency division module serves as with reference to carrying out 2 frequency divisions with the reference clock that receives with its rising edge, thus this phase discriminator to input clock signal not in strict duty ratio; And second judge module and high level counting module have been formed the first phase demodulation group, the 3rd judge module and low level counting module have been formed the second phase demodulation group, two the phase demodulation group structures and the course of work are just the same, all are the countings that in the pulse width period of half 2 fractional frequency signal 2S_sig, carry out local pulse clock, obtain the phase demodulation value thus, the trigger condition difference of each phase demodulation group work just, two the phase demodulation groups and first judge module have been formed the phase demodulation module jointly.
In order to make above-mentioned phase discriminator have better generality, can also increase by one module is set, be used to be provided with initial value, the initial value of low level counts value cont_low, high level number of times higher limit up_val, the low level number of times lower limit down_val of high level counts value cont_high, and offer above-mentioned phase demodulation module.
Corresponding, present embodiment also provides a kind of phase detecting method, with reference to shown in Figure 5, comprises the steps:
Step 101 is carried out 2 frequency divisions with the reference clock signal 1S_sig that receives with its rising edge, obtains 2 fractional frequency signal 2S_sig;
Step 102 judges whether 2 fractional frequency signal 2S_sig are high level, if current low level counts value cont_low is set to 0, and execution in step 103, if not, current high level counts value cont_high is set to 0, execution in step 105;
Step 106 is set at predefined low level number of times lower limit down_val with current low level counts value cont_low;
Step 109 is judged whether current phase demodulation value count_val is effective, and is made corresponding indication according to judged result.Described deterministic process is specially: with local oscillator output signal out_sig rising edge is reference, as current phase demodulation value count_val during less than the high level number of times higher limit up_val that sets and greater than the low level number of times lower limit down_val that sets, current phase demodulation value count_val is effective, otherwise current phase demodulation value count_val is invalid.
Mentioned local oscillator provides the controlled clock generator of phase demodulation clock for oscillator that count pulse is provided in phase discriminator or the phase demodulation process or other in the explanation of above-mentioned phase discriminator and phase detecting method.For the foregoing description being made better supplementary notes, in above-mentioned phase discriminator and phase detecting method, the graph of a relation of each mentioned signal as shown in Figure 6.
For what above-mentioned phase discriminator and phase detecting method also needed to remark additionally any be: the foregoing description be utilized 2 fractional frequency signal 2S_sig high level pulsewidth and low-level pulse width two time periods respectively the paired pulses clock count, made full use of the clock pulse width of whole 2 fractional frequency signal 2S_sig like this, can improve the real-time accuracy of phase demodulation value count_val, also can only utilize the time period paired pulses clock of 2 fractional frequency signal 2S_sig high level pulsewidths or low-level pulse width to count in a further embodiment, one group that includes only between the second phase demodulation group of the first phase demodulation group that second judge module and high level counting module form or the 3rd judge module and low level counting module composition according to the design actual conditions in this moment phase discriminator gets final product; And corresponding phase detecting method also includes only a phase demodulation value production process, implementation step also only is and a corresponding judgment process among step 103 and the step 105 that comprises in the said method step, this moment, the phase demodulation process was consistent with said method, did not repeat them here.
Utilize above-mentioned phase discriminator and phase detecting method, present embodiment also provides a kind of phase-locked loop, as shown in Figure 7, comprising: satellite clock receiving element, phase discriminator, local clock generation unit, processing unit, wherein:
The satellite clock receiving element is used for the satellite synchronizing clock signal that receives is handled, and obtains pps pulse per second signal, and offers phase discriminator; This unit be designed to known technology of the prior art, do not repeat them here;
Phase discriminator is used for according to receiving pps pulse per second signal and pulse clock signal, and determine and store phase demodulation value between current input pps pulse per second signal and the pulse clock signal, and when current phase demodulation value is effective, to processing unit output phase demodulation value useful signal;
The local clock generation unit is used to produce the phase demodulation pulse clock signal, and offers phase discriminator, and the adjustment that can produce signal frequency according to the adjustment signal that receives, and this clock generating unit preestablishes an initial clock frequency value; And, can select one-level clock (caesium clock), secondary clock (rubidium clock, high voltage stability control crystal oscillator) or three grades of clocks (high voltage stability control crystal oscillator) etc. according to the practical design needs;
Processing unit, be used for the last effectively phase demodulation value of storage, and after receiving phase demodulation value useful signal, read the current phase demodulation value that produces in the phase discriminator, utilize last effectively phase demodulation value and current phase demodulation value to compare, draw the FREQUENCY CONTROL value according to predefined filtering algorithm, and comprise the adjustment signal of frequency adjusted value according to the said frequencies controlling value, according to control strategy to the transmission of local clock generation unit.
As seen, have following remarkable advantage according to embodiments of the invention:
(1) in phase discriminator, phase detecting method and the phase-locked loop proposed by the invention, is reference, input signal is carried out 2 frequency divisions, make the duty ratio of frequency input signal no longer include strict requirement by the pulse clock signal rising edge that produces with the local clock generating unit;
(2) in phase discriminator proposed by the invention, the phase detecting method, count by the paired pulses clock signal and to obtain the phase demodulation value, thereby input clock signal need not have identical frequency;
(3) in the phase-locked loop proposed by the invention, owing to introduced the satellite clock receiving element, it can all convert the synchronizing signal of various satellites to pps pulse per second signal, and therefore, this phase-locked loop versatility is stronger, can satisfy the needs of various satellite synchro systems;
(4) phase discriminator and phase detecting method proposed by the invention can directly be judged the correctness of identified result, and need not be by other supplementary means;
(5) phase discriminator proposed by the invention can utilize hardware circuits such as CPLD, FPGA or ASIC to realize that flexibility is higher.
Claims (10)
1. a phase discriminator receives reference clock signal and local pulse clock signal, it is characterized in that this phase discriminator comprises:
Frequency division module carries out 2 frequency divisions to the described reference clock signal that receives, and exports 2 fractional frequency signals;
Time delay module is delayed time described 2 fractional frequency signals, the output time delayed signal, and delay time is a described local pulse clock cycle;
The phase demodulation module comprises first judge module, second judge module, the 3rd judge module, the 4th judge module, high level counting module and low level counting module, wherein:
First judge module receives described 2 fractional frequency signals, judges the level state of described 2 fractional frequency signals, and with judged result as the level state gating signal, send to described second judge module and the 3rd judge module;
Second judge module when to receive the level state gating signal be high, when current high level counts value during greater than predetermined high level number of times higher limit, then sends the higher limit asserts signal to the high level counting module; When current high level counts value is less than or equal to predetermined high level number of times higher limit, send the high level count signal to the high level counting module;
The high level counting module, receive the high level count signal after, carry out the high level counts and add 1 counting, and store current high level counts value; When receiving the higher limit asserts signal, current high level counts value is set to high level number of times higher limit;
The 3rd judge module receives the level state gating signal when low, when current low level counts value during less than predetermined low level number of times lower limit, then sends the lower limit asserts signal to the low level counting module; When current low level counts value is greater than or equal to predetermined low level number of times lower limit, send the low level count signal to the low level counting module;
The low level counting module, receive the low level count signal after, carry out the low level counts and add 1 counting, and store current low level counts; When receiving the lower limit asserts signal, current low level counts is set to low level number of times lower limit.
2. phase discriminator as claimed in claim 1 is characterized in that, this phase discriminator also comprises:
Phase demodulation value memory cell is used for the phase demodulation value of described phase demodulation module output is stored as current phase demodulation value.
3. phase discriminator as claimed in claim 1 is characterized in that, this phase discriminator also comprises:
Whether effectively whether the 5th judge module, the phase demodulation value that is used to judge described phase demodulation module output in the scope of setting, and according to judged result output phase demodulation value index signal.
4. phase discriminator as claimed in claim 1 is characterized in that, in the described phase demodulation module, sets the counts threshold value further, and when current counts value was not in the threshold value scope of setting, current counts value was set to predetermined value.
5. phase discriminator as claimed in claim 1 is characterized in that, described local pulse clock signal is the required drive clock output signal of external circuit.
6. phase detecting method comprises:
A. the described reference clock signal that receives is carried out 2 frequency divisions, obtain 2 fractional frequency signals;
B. described 2 fractional frequency signals are delayed time, the output time delayed signal, be a described local pulse clock cycle time of delay;
C. receive described 2 fractional frequency signals and time delayed signal, with described local pulse clock signal is counting clock, in the high level pulsewidth of described 2 fractional frequency signals or low-level pulse width in the time period, local pulse clock signal is counted, and when described time delayed signal and 2 fractional frequency signal level states are inequality, export this time counts value as the phase demodulation value, and restart counting.
7. method as claimed in claim 6 is characterized in that, this method comprises:
Set the counts threshold value,
And described step c comprises further: when current counts value was not in the threshold value scope of setting, current counts value was set to predetermined value.
8. method as claimed in claim 7 is characterized in that, described step c comprises further:
In the high level pulsewidth of 2 fractional frequency signals, the local pulse clock signal that receives is added 1 counting as the counts value, when current counts value during greater than predetermined high level number of times higher limit, current counts value is set to high level number of times higher limit, in the low-level pulse width of 2 fractional frequency signals, the counts value in the above-mentioned high level pulsewidth is set to 0;
In the low-level pulse width of 2 fractional frequency signals, the local pulse clock signal that receives is added 1 counting as the counts value, when current counts value during less than predetermined low level number of times lower limit, current counts value is set to low level number of times lower limit, in the high level pulsewidth of 2 fractional frequency signals, the counts value in the above-mentioned low-level pulse width is set to 0.
9. method as claimed in claim 6 is characterized in that, this method also comprises:
Judge the phase demodulation value whether in the scope of setting, and make the whether effectively indication of phase demodulation value according to judged result.
10. phase-locked loop comprises: phase discriminator, be used for according to receiving pps pulse per second signal and local clock signal, and determine and store phase demodulation value between current input pps pulse per second signal and the pulse clock signal; It is characterized in that:
Described phase discriminator comprises further:
Frequency division module carries out 2 frequency divisions to the described reference clock signal that receives, and exports 2 fractional frequency signals;
Time delay module is delayed time described 2 fractional frequency signals, the output time delayed signal, and be a described local pulse clock cycle time of delay;
The phase demodulation module comprises first judge module, second judge module, the 3rd judge module, the 4th judge module, high level counting module and low level counting module, wherein:
First judge module receives described 2 fractional frequency signals, judges the level state of described 2 fractional frequency signals, and with judged result as the level state gating signal, send to described second judge module and the 3rd judge module;
Second judge module when to receive the level state gating signal be high, when current high level counts value during greater than predetermined high level number of times higher limit, then sends the higher limit asserts signal to the high level counting module; When current high level counts value is less than or equal to predetermined high level number of times higher limit, send the high level count signal to the high level counting module;
The high level counting module, receive the high level count signal after, carry out the high level counts and add 1 counting, and store current high level counts value; When receiving the higher limit asserts signal, current high level counts value is set to high level number of times higher limit;
The 3rd judge module receives the level state gating signal when low, when current low level counts value during less than predetermined low level number of times lower limit, then sends the lower limit asserts signal to the low level counting module; When current low level counts value is greater than or equal to predetermined low level number of times lower limit, send the low level count signal to the low level counting module;
The low level counting module, receive the low level count signal after, carry out the low level counts and add 1 counting, and store current low level counts; When receiving the lower limit asserts signal, current low level counts is set to low level number of times lower limit.
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| CN101610123B (en) * | 2009-07-10 | 2013-03-20 | 中兴通讯股份有限公司 | Clock unit and realization method thereof |
| CN102148616B (en) * | 2011-03-31 | 2013-04-03 | 山东华芯半导体有限公司 | Method and system for preventing error locking of DLL (Delay-Locked Loop) |
| CN103675443B (en) * | 2012-09-06 | 2016-12-21 | 上海航天控制工程研究所 | Manned spacecraft FPGA global clock detection device |
| CN110784218B (en) * | 2019-11-11 | 2023-03-21 | 电信科学技术第五研究所有限公司 | Method for rapidly identifying rubidium clock type |
| CN115002893A (en) * | 2022-07-01 | 2022-09-02 | 白盒子(上海)微电子科技有限公司 | Method and device for improving clock holding capacity of base station based on digital phase-locked loop |
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