CN101276993B - Method of manufacturing semiconductor optical element - Google Patents
Method of manufacturing semiconductor optical element Download PDFInfo
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- CN101276993B CN101276993B CN2007103057567A CN200710305756A CN101276993B CN 101276993 B CN101276993 B CN 101276993B CN 2007103057567 A CN2007103057567 A CN 2007103057567A CN 200710305756 A CN200710305756 A CN 200710305756A CN 101276993 B CN101276993 B CN 101276993B
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Abstract
After a metal cap layer is laminated on a semiconductor laminated structure, a waveguide ridge is formed, the waveguide ridge is coated with an SiO2 film, and a resist is applied; then, a resist pattern is formed, the resist pattern exposing the surface of the SiO2 film on the top of the waveguide ridge, and burying the SiO2 film in channels with a resist film having a surface higher than the surface of the metal cap layer of the waveguide ridge and lower than the surface of the SiO2 film of the waveguide ridge; the SiO2 film is removed by dry etching, using the resist pattern as a mask. The metal cap layer is removed by wet etching, and a p-GaN layer of the waveguide ridge is exposed to form the electrode layer.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor optical device, relate to a kind of manufacture method that possesses the semiconductor optical device of electrode in waveguide crestal culmination portion especially.
Background technology
In recent years, as the densification of CD required from blue region can be luminous to the ultraviolet range semiconductor laser, active development research is a kind of adopts the nitride-based semiconductor laser device of the nitride-based III-V compound semiconductor of AlGaInN etc., and practicability.
Crystalline growth compound semiconductor on the GaN substrate and form this bluish violet LD (hereinafter, laser diode being expressed as LD).
Representational compound semiconductor has the III-V compound semiconductor in conjunction with III family element and V group element, by in conjunction with a plurality of III family's atoms and V group atom, just can obtain to have the mixed crystal compound semiconductor of multiple ratio of components.As the compound semiconductor that in bluish violet LD, uses, for example, GaN, GaPN, GaNAs, InGaN, AlGaN etc. are arranged.
Waveguide ridge LD is provided with electrode layer at the top of waveguide ridge usually.This electrode layer with as being connected of the contact layer of the superiors of waveguide ridge, undertaken by the opening that in the dielectric film that covers the waveguide ridge, is provided with in waveguide crestal culmination portion.Employing stripping means employed, that utilize photo etched mask when forming the waveguide ridge forms the dielectric film with this opening.Thus, because the photo etched mask bonding with contact layer, caving in along the surface of contact layer with the joint portion of contact layer, so a part of dielectric film that also can residual covering waveguide ridge after peeling off in this hollow part, become the surface of the contact layer that only covers this residual dielectric film amount, the contact area of electrode layer and contact layer will become littler than the whole surface area of contact layer.
Among employed contact layer material, for example GaAs etc.,, do not increase contact resistance greatly among the red LD in the past, do not influence the rising of LD operating voltage greatly yet so the contact area of utilizing stripping means to produce reduces because contact resistance is lower.
But, employed material is GaN etc. in the contact layer in bluish violet LD, and the contact resistance of material is than higher, the reduction of the contact area of electrode and contact layer thus, cause improving the contact resistance of electrode and contact layer, improve the result of the operating voltage of bluish violet LD.
For the minimizing of the contact area that prevents electrode and contact layer, enumerate the well known examples of LD manufacture method successively.
Under the situation that forms nitride semiconductor Laser device, at first, on the p of the wafer that contains a plurality of semiconductor layers type contact layer 111, form the p type electrode layer 112 that constitutes by palladium/molybdenum/gold.Then, on p type electrode layer 112, form banded photo etched mask (not shown), utilize RIE (reactive ion etching) to form ridge band 114.That is, utilize Ar gas, form p type electrode 112 by etching, and then by utilizing Ar, Cl
2And SiCl
4Mist, in the way of p type contact layer 111 and p type contact layer 110, carrying out etching, or to p guide layer 109 the way in carry out etching, form the ridge band.And, the resist of remnant ridge band 114 still, in the mode of the upper surface of cover wafers, the dielectric film 115 that forms 0.5 μ m thickness is (mainly by ZrO
2The Zr oxide that constitutes).After this, by removing resist, the top of exposing ridge band 114.And, form the p type pad electrode 116 that constitutes by molybdenum and gold, so that cover p type electrode 112 and near the dielectric film 115 in its both sides at least.(for example, capable with reference to 1, the 9 page of Japanese documentation, 42-50, and Fig. 1).
In addition, in another well known examples, a kind of Alignment Method step, that be used to make ridge waveguide pipe semiconductor LD that comprises stacked two different photoresist layers is disclosed.This manufacture method is the method for the following stated.
The photoresist layer of downside only reacts under the light that has less than the 300nm wavelength, and the photoresist layer of upside only reacts under the light with wavelength longer than 300nm.At the 2nd lining ducting layer 406 and forming in the semiconductor stacked structure of protective layer 408, remove the part of protective layer 408 and the 2nd lining ducting layer 406, formation ridge structure 414 and double channel 412 thereon.And, on the surface of ridge structure 414 and double channel 412, form the 2nd dielectric film 416.On the 2nd dielectric film, form the 1st photoresist layer 420 of lower floor and the 2nd photoresist layer 422 on upper strata.In order to expose near the 1st photoresist layer 420 the ridge structure 414, graphical the 2nd photoresist layer 422.Then, in order to expose the 2nd dielectric film 416 on the ridge structure 414, the 1st photoresist layer 420 is carried out RIE handle.Then, in order to remove the 2nd dielectric film 416 in ridge structure 414 outsides, carry out the etch processes that comprises the RIE processing.Then, remove the 1st residual photoresist layer 420 and the 2nd photoresist layer 422, the 1 metal levels 424 as electrode by evaporation.(for example, with reference to Japanese documentation 2, paragraph numbering [0024] is to [0034], and Fig. 7 to Figure 18).
And, in other well known examples, a kind of method is disclosed, by utilizing the wet etching of Al metal mask, the etching contact layer, and residual metal mask is motionless, with contact layer as mask, carry out wet etching, form ridge and raceway groove, simultaneously, utilize plasma CVD, on whole surface, form dielectric film, then, by peeling off the dielectric film of removing Al figure and deposit thereon.Then, utilize conventional lithography process, the resist figure of the part of p lateral electrode is exposed in formation, as mask, vacuum is being steamed electrode material with this resist figure, removes resist figure and the electrode material on it by peeling off, the electrode that the contact layer of formation and ridge closely bonds (for example, with reference to Japanese documentation 3, paragraph numbering [0025] is to [0034], and Fig. 1).
And, in other well known examples, following operation is disclosed.On the almost whole surface on contact layer 13 surfaces, form the 1st diaphragm 61, on the 1st diaphragm 61, form the 3rd banded diaphragm 63.Etching still adheres to after the 1st diaphragm 61 of the 3rd diaphragm 63, removes the 3rd diaphragm 63, forms the 1st banded diaphragm 61.Then, by with the 1st diaphragm as mask, at the layer under p side contact layer 13 and contact layer, for example p side coating 12 carry out etching midway, form banded waveguide.Then; with the material different with the 1st diaphragm 61; side at the waveguide of band shape; with the nitride semiconductor layer that exposes through etching, the plane of p side coating 12 in the etching of front, form the 2nd diaphragm 62 of the insulating properties that has; utilize stripping means; remove only the 1st diaphragm 61, on the 2nd diaphragm and p side contact layer 13, formed the p electrode that is electrically connected with this p side contact layer 13.(for example, with reference to Japanese documentation 4, paragraph numbering [0020] is to [0027], and Fig. 1).
In these existing methods,, comprise the operation of the semiconductor layer of etching metal film and metal film lower layer simultaneously even as the method for the contact area of guaranteeing the contact layer of waveguide ridge and electrode layer; Under the situation of using 2 layers of resist, stablize the resist of lower floor, residual specific thickness and the operation that stops etching; With one side with metal film as mask, one side is being used the operation peeled off under the situation of a plurality of diaphragms etc., also has problems a little stably making on the unified device of characteristic.In addition, also exist to use the problem points of the degree of freedom that can reduce operation under the situation of a plurality of resists and diaphragm etc.
Thus, utilizing simple operation, stably prevent at the upper surface of waveguide ridge semiconductor layer and electrode layer contact area be reduced to purpose, developed a kind of manufacturing process as described below.
At first,, form the waveguide ridge, on the whole surface of wafer, form SiO by on the wafer of stacked semiconductor layer, forming ditch portion
2Film.Then, on the whole surface of wafer, apply resist, make the thickness thicker formation resist film of the thickness of the resist film of locating at the top of waveguide ridge than the resist film at ditch portion place.Then, similarly utilize dry ecthing, remove resist, in the time of the resist film of residual ditch portion, remove the resist film at the place, top of waveguide ridge, form the resist figure at the top of exposing the waveguide ridge from the surface of resist film.Then, with this resist figure as mask, from the SiO that exposes of surface etching similarly
2Film is Yi Bian remain in the side of ditch portion and the SiO that the place, bottom forms
2Film, remove the SiO that at the top place of waveguide ridge form on one side
2Film is positively at the SiO at the top of waveguide ridge
2Form peristome on the film.
Then, remove after the resist figure, form the p lateral electrode at the place, top of waveguide ridge.
Have again, as a well known examples that p type Ohmic electrode is formed the ridge band as mask, disclose on the p type contact layer that forms by GaN, form banded metal level (the 1st layer is Ni/Au, and the 2nd layer is Pt), then, heat-treat (alloying), form p side Ohmic electrode, this p side Ohmic electrode as mask, is adopted etching gas Cl
2, carry out etching until exposing the such example of p type guide layer (for example, with reference to Japanese documentation 5, paragraph numbering [0035] is to [0038], and Fig. 2).
In addition, in as other well known examples of carrying out ridge formation, operation as described below is disclosed.In the 1st operation, on the almost whole surface on p side contact layer 13 surfaces, form the 1st diaphragm 61 that forms by the Si oxide, on the 1st diaphragm 61, form the 3rd banded diaphragm 63.Etching is removed the 3rd diaphragm 63 after still being attached with the 1st diaphragm 61 of the 3rd diaphragm 63, forms the 1st banded diaphragm 61.Then, in the 2nd operation, from the p side contact layer 13 that forms the 1st diaphragm 61 do not form the partially-etched of the 1st diaphragm 61, part forms the zone, flat waveguide path of corresponding diaphragm shape under the 1st diaphragm 61.Then; in the 3rd operation; use material material, that have insulating properties different, formation the 2nd diaphragm 62 on the plane of the side in flat waveguide path, the nitride semiconductor layer (p side coating 12) that exposes through etching and the 1st diaphragm 61 with the 1st diaphragm 61.After forming the 2nd diaphragm 62, remove the 1st diaphragm 61 by utilizing etching, only remove the 2nd diaphragm that on the 1st diaphragm 61, forms, on the plane of the side of band shape and p side coating 12, form the 2nd diaphragm continuously.
Though do not limit the etch processes in the 3rd operation especially, can list the dry-etching method that for example adopts hydrofluoric acid.(for example, with reference to Japanese documentation 6, paragraph numbering [0018] is to [0024], and Fig. 6).
Japanese documentation 3 spies open the 2000-340880 communique
Japanese documentation 4 spies open the 2003-142769 communique
Japanese documentation 5 spies open the 2004-253545 communique
Japanese documentation 6 spies open the 2000-114664 communique
Summary of the invention
In existing method, after forming the waveguide ridge, use SiO
2Film covers the coating resist, in the resist film of residual ditch portion, forms the resist figure at the top of exposing the waveguide ridge, with this resist figure as mask, the SiO that etching is similarly exposed from the surface
2Film, on one side the side of residual ditch portion and the SiO that the place, bottom forms
2Film, remove the SiO that at the top place of waveguide ridge form on one side
2Film forms SiO at the place, top of waveguide ridge
2The peristome of film in above-mentioned operation, is being removed SiO
2Film to be carrying out in the etching under the situation of dry ecthing, will exist because of etching to make at SiO
2Produce the situation of damage on the semiconductor layer that covers in the film.At for example SiO
2The lower floor of film is under the situation of p type contact layer, has the situation that sustains damage, increases contact resistance because of etching.Especially, when utilizing GaN class material to constitute p type contact layer, GaN class material is difficult to carry out the removal of material in wet etching, be difficult to eliminate this damaged portion with wet etching, has such problem points.
Implement the present invention in order to address the above problem, the 1st purpose of the present invention is to provide a kind of manufacture method, utilize simple procedures, just can be in the upper surface of waveguide ridge, the contact area that stably prevents semiconductor layer and electrode layer reduces, just can prevent simultaneously because of in the semiconductor layer at the top of waveguide ridge, carrying out the damage that etching causes, the raising rate of finished products.
Manufacture method according to semiconductor optical device of the present invention comprises: stack gradually the 1st semiconductor layer, the active layer of the 1st conduction type, the 2nd semiconductor layer and the protective layer of the 2nd conduction type on semiconductor substrate, form the operation of semiconductor stacked structure; On the surface of this semiconductor stacked structure, apply resist, utilize photomechanics, form and to comprise the operation that has corresponding to the 1st resist figure of the banded resist film part of the width of waveguide ridge; As mask, utilize etching to remove the operation that protective layer exposes the 2nd semiconductor layer in the 1st resist figure; By with the 1st resist figure as mask, utilize dry ecthing to remove the part of the upper surface side of the 2nd semiconductor layer, the recess of a part that forms in the bottom the 2nd semiconductor layer residual forms the operation of waveguide ridge thus; Remove the 1st resist figure, contain recess and the most surperficial on have on the surface of semiconductor stacked structure of waveguide ridge of protective layer, form the operation of the 1st dielectric film; The surface of exposing the 1st dielectric film that in waveguide crestal culmination portion, forms, simultaneously by means of resist film with surface higher and lower than the surface of the 1st dielectric film in the waveguide crestal culmination portion than the 2nd semiconductor layer surface of waveguide ridge, bury the 1st dielectric film with the recess of waveguide ridge adjacency underground, form the operation of the 2nd resist figure; With the 2nd resist figure as mask, utilize dry ecthing to remove the 1st dielectric film, expose the operation on the protective layer surface of waveguide ridge; Utilize wet etching to remove protective layer, expose the operation of the 2nd semiconductor layer; And the operation that on the surface of the 2nd semiconductor layer of the waveguide ridge that exposes, forms electrode layer.
In the manufacture method according to semiconductor optical device of the present invention, the 2nd resist figure that forms at the recess place with waveguide ridge adjacency has the surface higher and surperficial lower than the 1st dielectric film in the waveguide crestal culmination portion than the protective layer surface of waveguide ridge.When using the 2nd resist figure, when utilizing dry ecthing to remove the 1st dielectric film of waveguide crestal culmination portion, the 1st dielectric film of the side of not only residual waveguide ridge and recess, but also expose the protective layer of waveguide crestal culmination portion.And, when utilizing wet etching to remove protective layer, also expose the 2nd semiconductor layer, and on this 2nd semiconductor layer that exposes, form electrode layer.Utilize this simple process, the area that just can not reduce the 2nd semiconductor layer and electrode layer bonds.And; when with the 2nd resist figure as mask; when utilizing dry ecthing to remove the 1st dielectric film; owing on the 2nd semiconductor layer of waveguide ridge, form protective layer; so just can prevent because of the damage of dry ecthing, just can suppress to result from the increase of contact resistance of the 2nd semiconductor layer of dry ecthing to the 2nd semiconductor layer.
Description of drawings
Fig. 1 is the profile according to the semiconductor LD of an embodiment of the invention.
Fig. 2 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 3 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 4 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 5 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 6 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 7 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 8 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Fig. 9 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 10 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 11 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 12 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 13 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 14 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 15 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the another kind of manufacture method of semiconductor LD of the present invention.
Figure 16 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the another kind of manufacture method of semiconductor LD of the present invention.
Figure 17 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the another kind of manufacture method of semiconductor LD of the present invention.
Figure 18 is the profile according to the semiconductor LD of an embodiment of the invention.
Figure 19 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 20 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 21 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 22 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 23 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 24 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 25 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 26 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Figure 27 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
Symbol description
12 n type GaN substrates, 16 1n-coating, 18 2n-coating, 20 3n-coating, 26 active layers, 34 p-coating, 36 contact layers, 75 coat of metals, 76 resist figures, 40 waveguide ridges, 78 SiO
2Film, 82 resist figures, 46 p lateral electrodes.
Embodiment
In the execution mode hereinafter, as semiconductor optical device, though, for example describe as an example with bluish violet LD, be not limited to bluish violet LD, be applicable to the semiconductor optical device of redness etc. fully, reach same effect.
Therefore, the various materials that constitute semiconductor stacked structure are not limited to nitride-based semiconductor, also comprise InP class material or GaAs class material.In addition, substrate is not limited to the GaN substrate, also can be the insulated substrate of other semiconductor substrate of InP, GaAs, Si, SiC etc. or sapphire substrate etc.
Fig. 1 is the profile according to the semiconductor LD of an embodiment of the invention.Have again, in each figure, the identical or corresponding parts of identical symbolic representation.
In Fig. 1, this LD 10 is bluish violet LD of waveguide ridge type, be formed on (hereinafter as n type GaN substrate 12, " n type " is recited as " n-", in addition " p type " is recited as " p-", especially will be not the not doping situation of impurity be recited as " i-") the Ga face of a first type surface on the resilient coating 14 that forms with n-GaN, as the 1st semiconductor layer that on this resilient coating 14, forms with n-AlGaN, for example 1n-coating 16,2n-coating 18 and 3n-coating 20; N side SCH (the SeparateConfinement Heterostructure: the separation limit heterostructure) layer 24 and active layer 26 that on 3n-coating 20, stacks gradually the n side optical waveguide layer 22 that forms with n-GaN, forms with InGaN.
On this active layer 26, the electron barrier layer 30 that stacks gradually the p side sch layer 28 that forms with InGaN, forms with p-AlGaN, the p side optical waveguide layer 32 that forms with p-GaN, the p-coating 34 that forms with p-AlGaN, and the contact layer 36 that forms with p-GaN.As the 2nd semiconductor layer, in the present embodiment, can comprise p-coating 34 and contact layer 36.But according to circumstances, the 2nd semiconductor layer both can be 1 layer, also can be more than 3 layers.
By form the raceway groove 38 as recess on contact layer 36 and p-coating 34, contact layer 36 just forms waveguide ridge 40 with the part of the p-coating 34 of a side that contacts with contact layer 36.
In addition, in the present embodiment, the width of raceway groove is 10 μ m.Between raceway groove 38, the step part that forms on two outsides of waveguide ridge 40 is an electrode pad base station 42 for example.
In addition, the degree of depth of waveguide ridge 40, promptly the height apart from raceway groove 38 bottom surfaces for example is 0.5 μ m.
Utilization is as the 1st silicon oxide film 44 of the 1st dielectric film, covers the two sides and the bottom surface of raceway groove 38 of the sidewall of the sidewall that comprises waveguide ridge 40 and electrode pad base station 42.The upper end of the 1st silicon oxide film 44 of the two sides of covering raceway groove 38 is outstanding a little from the upper surface of contact layer 36.For example, use the SiO of thickness 200nm
2Film forms the 1st silicon oxide film 44.In addition, not forming the peristome 44a that the 1st silicon oxide film 44, the 1 silicon oxide films 44 have on the upper surface of contact layer 36 exposes the entire upper surface of contact layer 36.
On the upper surface of contact layer 36, the p lateral electrode 46 of joining and being electrically connected with contact layer 36 is set.By utilizing vacuum deposition method, stack gradually platinum (Pt) and Au and form p lateral electrode 46.This p lateral electrode 46, closely contact with the upper surface of contact layer 36, further it is covered from this upper surface, extend to through the 1st silicon oxide film 44 on the sidewall of waveguide ridge 40 on the part of the 1st silicon oxide film 44 of raceway groove 38 bottoms in the mode of the upper end that sandwiches the 1st silicon oxide film 44.
In addition, on a part of surface of the 1st silicon oxide film 44 of the 1st silicon oxide film 44 on the side of the electrode pad base station 42 on the upper surface of electrode pad base station 42 and in raceway groove 38 and raceway groove 38 bottoms, for example, be provided with and use SiO
2The 2nd silicon oxide film 48 that forms.
On the surface of p lateral electrode 46, set pad electrode 50 with p lateral electrode 46 tight contacts, on p lateral electrode the 46, the 2nd silicon oxide film 44 and the 2nd silicon oxide film 48 of groove 38 inside of both sides, set this pad electrode 50, and, extend on the 2nd silicon oxide film 48 that the upper surface of pad electrode base station 42 is provided with.
And, on the back side of n-GaN substrate 12, be provided with by utilizing vacuum deposition method to stack gradually the n lateral electrode 52 that Ti and Au film form.
In this LD 10, as n type impurity, doped silicon (Si), as p type impurity, magnesium-doped (Mg).
N-GaN substrate 12 has the bed thickness about 100 μ m.In addition, resilient coating 14 has the bed thickness about 1 μ m.1n-coating 16 has the bed thickness about 400nm, for example utilizes n-Al
0.07Ga
0.93N and forming; 2n-coating 18 has the bed thickness about 1000nm, for example utilizes n-Al
0.045Ga
0.955N and forming; 3n-coating 20 has the bed thickness about 300nm, for example utilizes n-Al
0.015Ga
0.985N and forming.
The bed thickness of n side optical waveguide layer 22 is for example 80nm.N side sch layer 24 has the bed thickness of 30nm, uses i-In
0.02Ga
0.98N and forming.
On the trap layer 26c of active layer 26, contact with this trap layer 26c and the p side sch layer 28 that is provided with has the thickness of 30nm, use i-In
0.02Ga
0.98N and forming.
The manufacture method of LD 10 is described then.
Fig. 2～Figure 14 is the part sectioned view of expression according to the semiconductor LD of each manufacturing process of the manufacture method of semiconductor LD of the present invention.
In this manufacturing process, because each layer of n-GaN substrate 12 and the p side optical waveguide layer 32 that on it, stacks gradually, in manufacturing process, not have special change so from each figure omission show section about each layer on its upper strata of the part that comprises p side optical waveguide layer 32.
At first, utilizing pre-thermal cleaning etc. to clean on the surperficial GaN substrate 12,, for example under 1000 ℃ growth temperature, forming n-GaN layer as resilient coating 14 by organometallic chemistry method of vapor-phase growing (below, be called the MOCVD method).
Then, form successively: as the n-Al of 1n-coating 16
0.07Ga
0.93The N layer is as the n-Al of 2n-coating 18
0.045Ga
0.955The N layer is as the n-Al of 3n-coating 20
0.015Ga
0.985The N layer is as the i-In of n side optical waveguide layer 22
0.02Ga
0.98The N layer is as the i-In of n side sch layer 24
0.02Ga
0.98The N layer; Form successively thereon: as the i-In of the trap layer 26a that constitutes active layer 26
0.12Ga
0.88The N layer, as the i-In of barrier layer 26b
0.02Ga
0.98N layer and as the i-In of trap layer 26c
0.12Ga
0.88The N layer.
Then, on active layer 26, form the i-In that has stacked gradually as p side sch layer 28
0.02Ga
0.98The N layer, as the p-Al of electron barrier layer 30
0.2Ga
0.8The N layer, as the p-Al of p side optical waveguide layer 32
0.2Ga
0.8N layer 70, as the p-Al of p-coating 34
0.07Ga
0.93N layer 72 and as the wafer of the p-GaN layer 74 of contact layer 36, and on p-GaN layer 74, stacked coat of metal 75 as protective layer.Now, the stepped construction that will contain coat of metal 75 simply is called semiconductor stacked structure.
Formation such as coat of metal 75 usefulness Au or Cr, the thickness of coat of metal 75 is 5nm～250nm, and is preferably 20nm～50nm.
Fig. 2 shows the result of this operation.
Have again, also can on coat of metal 75 and side that contact layer 36 contacts, the structure of stacked Au or Cr etc. on the Ti layer be set and the good Ti layer of contact layer 36 caking property thinly.
Then; with reference to Fig. 3; on the whole surface of the semiconductor stacked structure that is laminated with coat of metal 75; the coating resist; utilize photomechanics; residual resist on corresponding to the part 76a of the shape of waveguide ridge 40 is removed the resist corresponding to the part 76b of the shape of raceway groove 38, forms the resist figure 76 as the 1st resist figure thus.Fig. 3 is the result of this operation.In this embodiment, be 1.5 μ m corresponding to the width of the part 76a of waveguide ridge 40 shapes, be 10 μ m corresponding to the width of the part 76b of raceway groove 38 shapes.
Then, with reference to Fig. 4, with resist figure 76 as mask, etching metal protective layer 75, p-GaN layer 74 and p-Al
0.07Ga
0.93The part of one side of p-GaN layer 74 contact of N layer 72 forms residual p-Al
0.07Ga
0.93The part of N layer 72 is as the raceway groove 38 of bottom.
For example, utilize dry ecthing to carry out this etching, dry ecthing coat of metal 75, after this utilize RIE (Reactive Ion Etching: reactive ion etching), etching p-GaN layer 74 and p-Al
0.07Ga
0.93The part of one side of p-GaN layer 74 contact of N layer 72 forms residual p-Al
0.07Ga
0.93The part of N layer 72 is as the raceway groove 38 of bottom.In this embodiment, the etch depth a under this situation is: about a=500nm (0.5 μ m).By forming raceway groove 38, form waveguide ridge 40 and electrode pad base station 42.
Fig. 4 shows the result of this operation.
Then,, adopt organic solvent etc., remove the resist figure 76 that uses in etching before with reference to Fig. 5.The degree of depth of the raceway groove 38 of this moment, be that the height of waveguide ridge 40 equals etch depth a, for about 500nm (0.5 μ m).Fig. 5 shows the result of this operation.
Then,, on the whole surface of wafer, use CVD method or vacuum deposition method or sputtering method etc., for example form the SiO that becomes the 1st silicon oxide film 44 as the 1st dielectric film of 0.2 μ m thickness with reference to Fig. 6
2Film 78.SiO
2Film 78 covers upper surface, the surface of raceway groove 38 inside and the upper surface of electrode pad base station 42 of waveguide ridge 40.Fig. 6 shows the result of this operation.
Though use SiO under this situation
2As dielectric film, but except SiO
2Outside, can also use SiO
x(0＜x＜2), SiN, SiON, T'O
2, Ta
2O
5, Al
2O
3, AlN, ZrO
2, Nb
2O
5Deng.
Then,, on the whole surface of wafer, apply photoresist, form resist film 80 with reference to Fig. 7 so that the thickness b of the resist film at raceway groove 38 places than at the top of waveguide ridge 40 and the thickness c of the resist film at the place, top of electrode pad base station 42 thicker.For example, form resist film 80, so that about b=0.8 μ m, about c=0.4 μ m.
In Fig. 7, though described the surface depression of resist film 80 at the place, top of the top of surface ratio waveguide ridge 40 of the resist film 80 on the raceway groove 38 and electrode pad base station 42, if but that the surface energy of resist film is formed equally is smooth, satisfy b＞c naturally.
But, as shown in Figure 7, even if the surface depression of the resist film 80 at the top of the surface ratio waveguide ridge 40 of the resist film 80 on the raceway groove 38 and the top of electrode pad base station 42 place, if but satisfy b＞c, even then the shape on resist film 80 surfaces also can for shape arbitrarily.
Usually, adopt spin coating method to apply photoresist.That is, on wafer, drip resist, form uniform thickness from transferring by making wafer.
And rotation quantity and rotational time by with the viscosity of photoresist and drainage, wafer rotation the time are set suitable numerical value for, just can control the thickness of resist film.
As shown in Figure 7, though be formed with on the surface of wafer under the situation of projection or recess, outstanding part, promptly under this situation at the top of waveguide ridge 40 and the top of electrode pad base station 42 will attenuation, the part of depression, will thickening under this situation in the place of raceway groove 38, but the extent of this thickness is influenced by the viscosity of photoresist.
Under the situation of this wafer shown in Figure 7, when viscosity hour, the relation between the thickness c of the resist film 80 at place, the top of the thickness b of the resist film 80 at the etch depth a of raceway groove 38, raceway groove 38 places and the top of waveguide ridge 40 or electrode pad base station 42 is approximately b=c+a.This just means can make the surperficial about the same smooth of resist film 80.
In addition, not about the same smooth on the surface of resist film 80, under the situation of the surface depression of the local resist of raceway groove 38, when the viscosity of photoresist becomes big, be approximately b=c.The thickness of resist film 80 at place, top that this means the top of the thickness of resist film 80 at raceway groove 38 places and waveguide ridge 40 or electrode pad base station 42 is almost equal.
In addition, not about the same smooth on the surface of resist film 80, under the situation of the surface of the local resist of raceway groove 38 depression, the viscosity that limits resist almost is step-down not, b＞c, promptly the thickness of the resist film 80 of raceway groove 38 parts becomes also thicker than the thickness of the resist film 80 at the place, top of the top of waveguide ridge 40 or electrode pad base station 42.
So, rotation number when viscosity by suitably setting resist and wafer rotation, just the relation between the thickness c of the resist film 80 at the place, top of the top of the thickness b of the resist film 80 at raceway groove 38 part places and waveguide ridge 40 or electrode pad base station 42 can be set at desirable relation, i.e. b＞c.Fig. 7 shows the result of this operation.
Then, with reference to Fig. 8, similarly remove resist from the surface of resist film 80, in the resist film 80 of residual groove 38, fully remove the resist film 80 at the place, top of the top of waveguide ridge 40 and electrode pad base station 42, form the SiO at the place, top of the top of exposing waveguide ridge 40 respectively and electrode pad base station 42
2The resist figure 82 of film 78.
For example, by adopting O
2The dry ecthing of plasma, is the SiO at the top of the top of waveguide ridge 40 and electrode pad base station 42 at the part of specific thickness
2Film 78 will expose fully, and at raceway groove 38, on the surface ratio coat of metal 75 of resist film 80 in the residual De Genggao, in this embodiment, and for example, the about 400nm of etching.
Have again, must be with the surface etching of in this embodiment resist film 80 than the degree of the top residual De Genggao of coat of metal 75.But, because resist film 80, in the time of the top residual De Genggao of its surface ratio the 2nd semiconductor layer, promptly comprise p-coating 34 and contact layer 36 in this embodiment as the 2nd semiconductor layer, thus also can etching must be than the degree of the top residual De Genggao of contact layer 36.
Thickness at the resist film 80 at raceway groove 38 places is about 800nm, or the thickness of the resist film 80 at place, the top of the top of waveguide ridge 40 and electrode pad base station 42 is about 400nm, forms resist film 80.Thus, when utilizing etching when the resist of about 400nm is only removed on the surface of resist film 80, the resist film 80 at the top of the top of waveguide ridge 40 and electrode pad base station 42 is removed, and exposes SiO
2Above the film 78, the surface with the resist film 80 at raceway groove 38 places is formed on SiO simultaneously
2Height and position about half of the thickness of film 78 makes this residual resist film become resist figure 82 as the 2nd resist figure.
The etching of similarly carrying out under the etched situation from the surface of resist film 80 stops, for example, and by adopting O
2The control of the etch quantity the when dry ecthing of plasma removes resist film is by passing through to adopt O from the etching chamber visual observation on one side
2The CO that the dry ecthing of plasma is generated when removing resist film is energized in plasma and the excitation light intensity of the wavelength 451nm that sends, and one side is carried out etching and correctly carried out.
Since can accurately detect on one side resist film 80 etch quantity, carry out etching on one side, so just can form the resist film in the residual raceway groove 38 and remove the top of waveguide ridge 40 and the resist figure 82 of the resist film 80 that the top of electrode pad base station 42 is located.Fig. 8 shows the result of this operation.
Then, with reference to Fig. 9, with resist figure 82 as mask, the SiO that etching is similarly exposed from the surface
2Film 78 is Yi Bian remain in the SiO of raceway groove 38 sides and the formation of place, bottom
2Film 78 is Yi Bian remove at the top of waveguide ridge 40 fully and SiO that place, the top of electrode pad base station 42 forms
2Film 78.Positively at the SiO at place, the top of waveguide ridge 40
2 Form peristome 44a on the film 78.
Etching under this situation can be used based on CF
4Deng reactive ion etching method etc. dry ecthing or based on the wet etch process of dilute hydrofluoric acid etc.
In this operation, when utilizing dry ecthing to remove SiO
2During film 78, the p-GaN layer 74 that coat of metal 75 covers as contact layer 36.Therefore, the damage that causes because of dry ecthing just can not be prolonged and p-GaN layer 74.Therefore, when finishing manufacturing LD 10, in contact layer 36, just can not produce damage.Therefore, the increase of the contact resistance that causes of the damage that just can suppress to produce because of dry ecthing.And then, can improve the rate of finished products of LD 10.
Have, the material of coat of metal 75 also can use but can be by the material of wet etching by the corrosive agent institute etching of etching dielectric film in this operation again.
In these cases, can also utilize the method for the following stated to control correct etch quantity.
For example, adopt CF
4Come dry ecthing SiO Deng the gas that contains fluorine
2Under the situation of film 78, also can be by observation from by SiO
2The SiF that Si in the film 78 and the F in the etching gas produce
2In the light intensity of the about 390nm of wavelength that sends, stop etching.
In addition, utilizing dilute hydrofluoric acid etc. to carry out wet etching SiO
2Under the situation of film 78, also can be from the relative position of wafer surface at the top of waveguide ridge 40 and the SiO that forms of the top of electrode pad base station 42
2 Film 78 is injected the laser of single wavelength, measures intensity of light reflected, just can confirm SiO thus
2The residual thickness of film 78 becomes 0 situation, and then stops etching.Fig. 9 shows the result of this operation.
Then, with reference to Figure 10,, remove resist figure 82 by adopting the wet etching of organic solvent.Figure 10 shows the result of this operation.
And, utilize wet etching to remove coat of metal 75.When coat of metal 75 is to adopt under the situation of Au formation, utilize chloroazotic acid to remove; When adopting Cr to form under the situation of coat of metal 75, utilize hydrochloric acid to remove.In this embodiment; as coat of metal,, be not limited to Au, Cr though for example be illustrated as an example with Au, Cr; if the metal that the impregnable corrosive agent of dielectric film of the sidewall of waveguide ridge 40 is removed similarly also can use as coat of metal.
In addition, with side that contact layer 36 contacts on use under the situation of Ti layer, though utilize the corrosive liquid of HF series to remove because also etching SiO in this case
2Film is so just must make the bed thickness attenuation of Ti layer in advance.In the present embodiment, SiO
2Film is 200nm, with respect to the SiO of this degree
2The thickness of film as the thickness of Ti layer, is preferably more than the 5nm, below the 30nm.Figure 11 shows the result of this operation.
Then, with reference to Figure 12, on the top of waveguide ridge 40, form p lateral electrode 46.
At first, on the whole surface of wafer, the coating resist, utilize photomechanics, form resist figure (not shown), this resist figure as the superiors of waveguide ridge 40 upper surface, the sidewall of waveguide ridge 40 and the part place opening of raceway groove 38 bottoms of p-GaN layer 74, on this resist figure, utilize for example vacuum deposition method, after the electrode layer that formation is made of the stepped construction of Pt and Au, by adopting stripping means, the electrode layer of removing resist film and forming on this resist film forms p lateral electrode 46.
Because the upper surface of the p-GaN layer 74 at the top of waveguide ridge 40,44a exposes at SiO by means of peristome
2The entire upper surface that does not have covering in the film 78 is not so the contact area of this p lateral electrode 46 and p-GaN layer 74 just is reduced when forming peristome 44a.
Therefore, according to the minimizing of p lateral electrode 46, just can prevent the increase of contact resistance with the contact area of p-GaN layer 74.
In addition, cover the SiO of the two sides of raceway groove 38
2The upper end of film 78 is outstanding a little from the upper surface of p-GaN layer 74.Form p lateral electrode 46, so that its upper surface with p-GaN layer 74 closely contacts, this upper surface is further to sandwich SiO certainly
2The mode of the upper end of film 78 is to its covering, via the SiO on the sidewall of waveguide ridge 40
2 Film 78 extends to the SiO of raceway groove 38 bottoms
2On the part of film 78.Figure 12 shows the result of this operation.
Then, form the 2nd silicon oxide film 48.
With reference to Figure 13, at first on the whole surface of wafer, apply resist, utilize photomechanics be formed on removal except the part on the p lateral electrode 46, be electrode pad base station 42 upper surfaces, and raceway groove 38 in electrode pad base station 42 sides and the part place of groove 38 bottoms resist figure (not shown) with opening, utilize evaporation to form the SiO of thickness for 100nm on the whole surface of wafer
2Film is by the SiO that forms on the resist film that utilizes stripping means to remove to form on the p lateral electrode 46 and this resist film
2Film forms by SiO
2Film formed the 2nd silicon oxide film 48.Figure 13 shows the result of this operation.
As the dielectric film under this situation, except SiO
2Outside, can also use SiO
x(0＜x＜2), SiN, SiON, TiO
2, Ta
2O
5, Al
2O
3, AlN, ZrO
2, Nb
2O
5Deng.
At last, ginseng Figure 14 utilizes vacuum deposition method, and on p lateral electrode 46, raceway groove 38 and the 2nd silicon oxide film 48, the stacked metal film that is made of Ti, Pt and Au forms pad electrode 50.
Figure 15～17th, expression is according to the part sectioned view of the semiconductor LD of each manufacturing process of the another kind of manufacture method of semiconductor LD of the present invention.
In each manufacturing process of semiconductor LD of explanation before, the operation till this variation and Fig. 1～Fig. 6 is identical.Fig. 7 of explanation and the operation of Fig. 8 instead, the operation of use Figure 15～Figure 17.
In the operation of before Fig. 6, when by SiO
2After the upper surface of the upper surface of film 78 covering waveguide ridges 40, the surface of raceway groove 38 inside and electrode pad base station 42, with reference to Figure 15, on the whole surface of wafer, coating is the photoresist of principal component with phenolic resins, with the groove 38 of waveguide ridge 40 adjacency in form the SiO at surface and waveguide ridge 40 tops with resist film 90
2The resist film 90 of the upper surface of film 78 height much at one.
In this embodiment, the bed thickness d of the resist film 90 in the raceway groove 38, the SiO that promptly is provided with from the bottom of raceway groove 38
2Height d till the surface of film 78 to the surface of resist film 90 is the size about for example 500nm (O.5 μ m).
Under this situation, the formation method of the resist film 80 among the manufacture method of the resist film 90 of the bed thickness d of the resist film 90 in the correct control raceway groove 38 and the Fig. 7 that has illustrated is identical, rotation number when viscosity by suitably setting resist and wafer rotation just can be set at desirable numerical value with the thickness d of the resist film 90 of raceway groove 38 parts.Figure 15 shows the result of this operation.
Then,, on resist film 90, adopt the photomechanical process method, SiO in the bottom surface of raceway groove 38 with reference to Figure 16
2Residual resist film 90 on the part on the film 78, the SiO on the resist film 90 in raceway groove 38 and the sidewall of waveguide ridge 40
2Between the film 78 and the SiO on the sidewall of resist film 90 and electrode pad base station 42
2Between the film 78, the interval e that sets regulation isolates, and forms the SiO that similarly exposes waveguide ridge 40 tops and place, electrode pad base station 42 tops simultaneously
2The resist figure 92 on film 78 surfaces.Figure 16 shows the result of this operation.
Then,,, for example in atmosphere, keep 140 ℃ temperature to carry out the heating of 10 fens clock times, photoresist is flowed, by the SiO on the sidewall that in raceway groove 38, makes resist film 90 and waveguide ridge 40 by the heat treatment wafer with reference to Figure 17
2Between the film 78 and the SiO on the sidewall of resist film 90 and electrode pad base station 42
2There is not predetermined distance e between the film 78, promptly by making the SiO on the sidewall in resist film and the raceway groove 38
2 Film 78 closely bonds, and is formed on residual resist films in the groove 38 and exposes the top of waveguide ridge 40 and the resist figure 82 at the top of electrode pad base station 42.Figure 17 shows the result of this operation.
The height and position f on the resist film surface that is provided with in the raceway groove 38 of resist figure 82 sets than the SiO at waveguide ridge 40 tops and place, electrode pad base station 42 tops
2 Film 78 surfaces are lower, than the top higher residual degree of the coat of metal 75 at waveguide ridge 40 tops and electrode pad base station 42 tops place.In this embodiment, setting is of a size of about f=400nm.
And, for this reason, before and after the heat treatment in this operation, volume at the hypothesis resist film does not have under the situation of variation, if the area of section of the resist figure 92 in the cross section of Figure 15 and Figure 16 equates with the area of section of resist figure 82, just must set e at interval, so that obtain desirable f value.
Have, in Figure 16, though the interval e of resist figure 92 is set in the both sides of the photoresist film in the groove 38, e can obtain desirable f value if set at interval, also can be arranged on one-sided so at interval again.
The later operation of the later operation of this operation and Fig. 9 of explanation before is identical.
In the manufacture method of the LD 10 of this execution mode 1; be laminated with on the wafer of semiconductor layer; also, form waveguide ridge 40 and electrode pad base station 42, on the whole surface of wafer, form SiO by in the semiconductor stacked structure that has formed coat of metal 75, forming raceway groove 38
2 Film 78.
Then, on the whole surface of wafer, apply resist, form resist film 82, so that the thickness of the resist film 80 at place, the top of the top of the Film Thickness Ratio waveguide ridge 40 of the resist film in the raceway groove 38 and electrode pad base station 42 is thicker.
Then, similarly from the surface removal resist of resist film 80, in the resist film 80 of residual raceway groove 38, remove the resist film 80 at the place, top of the top of waveguide ridge 40 and electrode pad base station 42, form the resist figure 82 at the top of the top of exposing waveguide ridge 40 and electrode pad base station 42.
Then, with resist figure 82 as mask, the SiO that dry ecthing is similarly exposed from the surface
2Film 78, on one side the SiO that forms of residual raceway groove 38 sides and bottom place
2Film 78, remove at the top of waveguide ridge 40 and SiO that the top place of electrode pad base station 42 form on one side
2Film 78, the positively SiO that locates at the top of waveguide ridge 40
2Form the peristome 44a that exposes coat of metal 75 on the film 78.
Then, behind the removal resist figure 82, utilize wet etching to remove coat of metal 75.Then, form p lateral electrode 46 at the top of waveguide ridge 40.
In the manufacture method of this LD, become the upper surface of the p-GaN layer of contact layer 36 under the semiconductor layer that contacts with p lateral electrode 46, this situation, pass through SiO
2The peristome 44a of film 78 is positively exposed, and does not have residual Si O on the upper surface of p-GaN layer
2Film 78.Thus, do not reduce the contact area of p lateral electrode 46 and contact layer 36, do not increase operating voltage.And, utilizing dry ecthing to remove the SiO that the waveguide road forms through the top of ridge 40
2During film 78, owing to contact layer 36 is covered by coat of metal 75, so do not sustain damage because of dry ecthing.Therefore, can suppress to result from the increase of contact resistance of the damage of dry ecthing, operating voltage does not increase.And then, can make characteristic LD 10 good, that rate of finished products is high with simple operation.
As mentioned above, manufacture method according to semiconductor optical device of the present invention, comprise: on semiconductor substrate, stack gradually the 1st semiconductor layer, the active layer of the 1st conduction type, the 2nd semiconductor layer and the protective layer of the 2nd conduction type, form the operation of semiconductor stacked structure; On the surface of this semiconductor stacked structure, apply resist, utilize photomechanics, form and to comprise the operation that has corresponding to the 1st resist figure of the banded resist film part of the width of waveguide ridge; As mask, utilize etching to remove the operation that protective layer exposes the 2nd semiconductor layer in the 1st resist figure; By with the 1st resist figure as mask, utilize dry ecthing to remove the part of the upper surface side of the 2nd semiconductor layer, the recess of a part that forms in the bottom the 2nd semiconductor layer residual forms the operation of waveguide ridge thus; Remove the 1st resist figure, contain recess and the most surperficial on have the operation that forms the 1st dielectric film on the surface of semiconductor stacked structure of waveguide ridge of protective layer; The surface of exposing the 1st dielectric film that in waveguide crestal culmination portion, forms, simultaneously by means of resist film with surface higher and lower than the surface of the 1st dielectric film in the waveguide crestal culmination portion than the 2nd semiconductor layer surface of waveguide ridge, bury the 1st dielectric film with the recess of waveguide ridge adjacency underground, form the operation of the 2nd resist figure; With the 2nd resist figure as mask, utilize dry ecthing to remove the 1st dielectric film, expose the operation on the protective layer surface of waveguide ridge; Utilize wet etching to remove protective layer, expose the operation of the 2nd semiconductor layer; And the operation that on the surface of the 2nd semiconductor layer of the waveguide ridge that exposes, forms electrode layer.Thus, make the 2nd resist figure that forms at recess have the surface higher and surperficial lower than the 1st dielectric film on the top of waveguide ridge than the protective layer surface of waveguide ridge with waveguide ridge adjacency.When using the 2nd resist figure to utilize dry ecthing to remove the 1st dielectric film of waveguide crestal culmination portion, in the 1st dielectric film of the side of residual waveguide ridge and recess, expose the protective layer of waveguide crestal culmination portion.And, when utilizing wet etching to remove protective layer, expose the 2nd semiconductor layer, on this 2nd semiconductor layer that exposes, form electrode layer.By this simple operation, can not reduce the contact area of the 2nd semiconductor layer and electrode layer, make their combinations.And; when utilizing dry ecthing to remove the 1st dielectric film as mask in the 2nd resist figure; owing on the 2nd semiconductor layer of waveguide ridge, form protective layer; so can prevent the damage that the 2nd semiconductor caused because of dry ecthing, can suppress to result from the increase of contact resistance of the 2nd semiconductor layer of dry ecthing.And then can make characteristic semiconductor optical device good, that rate of finished products is high with simple operation.
The profile of the semiconductor LD of one embodiment of the present invention during Figure 18.
In Figure 18, this LD 100 is bluish violet LD of waveguide ridge, is identical structure basically with the structure of LD 10 of explanation in the execution mode 1.
LD 100 is with LD 10 differences, with respect in LD 10, comprises the two sides and the bottom surface of raceway groove 38 of the sidewall of the sidewall of waveguide ridge 40 and electrode pad base station 42, covered by the 1st silicon oxide film 44; In LD 100, the two sides of raceway groove 38 that comprise the sidewall of the sidewall of waveguide ridge 40 and electrode pad base station 42 are covered by the 1st silicon oxide film 44, and the bottom surface of raceway groove 38 is covered by the 1st silicon oxide film.
Therefore, p lateral electrode 46 directly contacts with the upper surface of contact layer 36 and the sidewall of waveguide ridge 40, and extends to the bottom surface of raceway groove 38.In addition, the 2nd silicon oxide film 48 is direct coated electrode pad base station 42 also, and extends to the upper surface of electrode pad base station 42.Other is identical with LD 10 structures.
The manufacture method of LD 100 then, is described.
Figure 19～Figure 27 is the part sectioned view of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.
In this manufacturing process, because n-GaN substrate 12 and stacked thereon p side optical waveguide layer 32 each layer before change in manufacturing process especially, so from each figure, omit, show section for each layer on the upper strata on its of a part that comprises p side optical waveguide layer 32.
At first, utilizing pre-thermal cleaning etc. to clean on the surperficial GaN substrate 12, by the organometallic chemistry method of vapor-phase growing (below, be called the MOCVD method), for example under 1000 ℃ growth temperature, form n-GaN layer successively, as the n-Al of 1n-coating 16 as resilient coating 14
0.07Ga
0.93The N layer is as the n-Al of 2n-coating 18
0.045Ga
0.955The N layer is as the n-Al of 3n-coating 20
0.015Ga
0.985The N layer is as the i-In of n side optical waveguide layer 22
0.02Ga
0.98The N layer is as the i-In of n side sch layer 24
0.02Ga
0.98The N layer; On this, form successively: as the i-In of the trap layer 26a that constitutes active layer 26
0.12Ga
0.88The N layer, as the i-In of barrier layer 26b
0.02Ga
0.98N layer and as the i-In of trap layer 26c
0.12Ga
0.88The N layer.
Then, on active layer 26, form the i-In that has stacked gradually as p side sch layer 28
0.02Ga
0.98The N layer, as the p-Al of electron barrier layer 30
0.2Ga
0.8The N layer, as the p-Al of p side optical waveguide layer 32
0.2Ga
0.8N layer 70, as the p-Al of p-coating 34
0.07Ga
0.93N layer 72 and as the semiconductor stacked structure of the p-GaN layer 74 of contact layer 36.Figure 19 shows the result of this operation.
Then, with reference to Figure 20, on the whole surface of semiconductor stacked structure, apply resist, utilize photomechanics, residual resist on corresponding to the part 76a of the shape of waveguide ridge 40, removal forms the resist figure 76 as the 1st resist figure corresponding to the resist of the part 76b of the shape of raceway groove 38.Figure 20 is the result of this operation.
Then, with reference to Figure 21, with resist figure 76 as mask, etching p-GaN layer 74 and p-Al
0.07Ga
0.93The part of p-GaN layer 74 contact side of N layer 72, residual p-Al
0.07Ga
0.93The part of N layer 72 forms raceway groove 38 as the bottom.This etching utilizes RIE (Reactive Ion Etching: reactive ion etching), etching and p-GaN layer 74 and and p-Al
0.07Ga
0.93The part of one side of p-GaN layer 74 contact of N layer 72, residual p-Al
0.07Ga
0.93The part of N layer 72 forms raceway groove 38 as the bottom.Figure 21 shows the result of this operation.
Then, with reference to Figure 22, the resist figure 76 that uses in the etching before keeping remaining in is constant, uses CVD method or vacuum deposition method or sputtering method etc. on the whole surface of wafer, forms the SiO of the 1st silicon oxide film 44 of conduct the 1st dielectric film that for example becomes 0.2 μ m thickness
2Film 78.SiO
2Film 78 covers upper surface, the surface of raceway groove 38 inside and the upper surface of electrode pad base station 42 of waveguide ridge 40.Figure 22 shows the result of this operation.
As the material of the dielectric film under this situation, can use the oxide of Si, Ti, Al, V, Zr, Nb, Hf, Ta, SiN, SiON, BN, SiC, AlN, TiN, TiC.These materials are because of face orientation difference, etching speed difference.That is, use these materials, utilize vacuum vapour deposition or sputtering method, CVD method etc. to form under the situation of dielectric films, the bottom surface of the top of waveguide ridge 40 and raceway groove 38 membranous is different from form membranous on the sidewall of waveguide ridge.That is, the etching speed difference, the etching speed of the film that forms on the sidewall of waveguide ridge is compared with the film of the bottom surface of the top of waveguide ridge 40 and raceway groove 38, has 50～100 times etching speed.
Then, with reference to Figure 23, use BHF (16%): H
2O=1: 100 corrosive liquid, to the SiO that forms previously
2When film 78 carries out the etching in 10 seconds, though remove the SiO of the side that is formed on waveguide ridge 40 fully
2 Film 78, but at the top of waveguide ridge 40 and the SiO that forms of the bottom surface of raceway groove 38
2 Film 78 does not almost have etched, and residual.Figure 23 shows the result of this operation.
Then, with reference to Figure 24, remove the resist figure 76 of front by the wet etching that with an organic solvent waits.Also remove the SiO that remains on the resist figure simultaneously
2Film 78, the residual SiO that only forms in the bottom surface of raceway groove 38
2 Film 78.
In this operation, become the part of waveguide ridge 40 and electrode pad base station 42.Figure 24 illustrates the result of this operation.
In this operation, owing to be not used in the dry ecthing that the upper surface that makes p-GaN layer 74 exposes, so, do not produce damage at p-GaN layer 74 because of dry ecthing.Therefore, can suppress to result from the increase of contact resistance of damage of the dry ecthing of the contact layer 36 that constitutes by p-GaN layer 74.
Then, with reference to Figure 25, on the top of waveguide ridge 40, form p lateral electrode 46.
At first, on the whole surface of wafer, apply resist, utilize photomechanics, form resist figure (not shown), this resist figure as the superiors of waveguide ridge 40 upper surface, the sidewall of waveguide ridge 40 and the part place opening of raceway groove 38 bottoms of p-GaN layer 74, on this resist figure, utilize for example vacuum deposition method, after the electrode layer that formation is made of the stepped construction of Pt and Au, by adopting stripping means, the electrode layer of removing resist film and forming on this resist film forms p lateral electrode 46.
Because the upper surface of the p-GaN layer 74 at the top of waveguide ridge 40,44a exposes at SiO by means of peristome
2The entire upper surface that does not have covering in the film 78 is not so the contact area of this p lateral electrode 46 and p-GaN layer 74 reduces when forming peristome 44a.
Therefore, can prevent, and the increase of the contact resistance that causes, simultaneously, can suppress to result from the increase of the contact resistance of the damage that dry ecthing causes based on p lateral electrode 46 minimizing with the contact area of p-GaN layer 74.Figure 25 illustrates the result of this operation.
Have, in this manufacture method, at the side of waveguide ridge 40 naked film, the side of waveguide ridge 40 directly contacts with p lateral electrode 46 again.Therefore, produce situation about directly contacting with the side of p lateral electrode 46 and p-coating 34.But even the side of p lateral electrode 46 and p-coating 34 directly contacts, the contact resistance height of p-coating 34 does not almost have electric current to flow through, and thinks in the early stage no problem in the characteristic.
Then, formation is as the 2nd silicon oxide film 48 of the 2nd dielectric film.Figure 26 illustrates the result of this operation.
As the dielectric film under this situation, can use the oxide of Si, Ti, Al, V, Zr, Nb, Hf, Ta, SiN, SiON, BN, SiC, AlN, TiN, TiC etc.At last, on p lateral electrode 46, raceway groove 38 and the 2nd silicon oxide film 48,, form pad electrode 50 by the stacked metal film that constitutes by Ti, Pt and Au of vacuum vapour deposition.Figure 27 shows the result of this operation.
The formation of the formation of the 2nd silicon oxide film 48 and pad electrode 50 is identical with execution mode 1 explanation.
According to the manufacture method of the semiconductor optical device of present embodiment, at first, sequential cascade 1n-coating 16,2n-coating, and 3n-coating 20, active layer 26, p-coating 34 and contact layer 36 form semiconductor stacked structure on n type GaN substrate 12; Then, on the surface of this semiconductor stacked structure, apply resist, form comprise have corresponding to waveguide ridge 40 the resist figure 76 of banded resist film part of width, this resist figure 76 as mask, is formed waveguide ridge 40.Then, on the surface of the semiconductor stacked structure of the waveguide ridge 40 that comprises raceway groove 38 and residual resist figure 76, form SiO
2Film 78 is at the top of raceway groove 38 and waveguide ridge 40 residual Si O
2Film 78 is removed the SiO of waveguide ridge 40 sides simultaneously
2Film 78 exposes waveguide ridge sidewall.Then, utilize the method for peeling off, remove resist figure 76 and the SiO that remains on this resist figure 76
2Film 78 exposes contact layer 36, forms p lateral electrode 46 on the surface of the contact layer 36 of the waveguide ridge 40 that exposes and p-coating 34.In the manufacture method of this semiconductor optical device, when forming peristome 44a, do not reduce the contact area of p lateral electrode 46 and p-GaN layer 74.And, do not use dry ecthing when exposing, so contact layer not because of dry ecthing produces damage, suppresses the increase of contact resistance owing to contact layer 36 at the top that makes waveguide 40.And then, can make characteristic semiconductor optical device good, that rate of finished products is high with simple operation.
As mentioned above, the manufacture method according to semiconductor optical device of the present invention comprises: stack gradually the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type on semiconductor substrate, form the operation of semiconductor stacked structure; On the surface of this semiconductor stacked structure, apply resist, utilize photomechanics, form and to comprise the operation that has corresponding to the 1st resist figure of the banded resist film part of the width of waveguide ridge; As mask, utilize dry ecthing to remove the part of the upper surface side of the 2nd semiconductor layer in the 1st resist figure, the recess of a part that forms in the bottom the 2nd semiconductor layer residual forms the operation of waveguide ridge thus; On the surface of the semiconductor stacked structure of the waveguide ridge that contains recess and residual the 1st resist figure, form the operation of the 1st dielectric film; On one side at residual the 1st dielectric film in the top of recess and waveguide ridge, Yi Bian remove the 1st dielectric film of waveguide ridge side, the operation that waveguide ridge sidewall is exposed; Utilization is peeled off method and is removed resist figure and the 1st dielectric film that remains on this resist figure, the operation that the 2nd semiconductor layer is exposed; On the surface of the 2nd semiconductor layer that exposes the waveguide ridge, form the operation of electrode layer, thus,, can not reduce the contact area of the 2nd semiconductor layer and electrode layer, make their combinations by this simple operation.And, do not use dry ecthing when exposing, so the 2nd semiconductor layer not because of dry ecthing produces damage, suppresses the increase of contact resistance owing to the 2nd semiconductor layer at the top that makes waveguide.And then, can make characteristic semiconductor optical device good, that rate of finished products is high with simple operation.
As mentioned above, the manufacture method of semiconductor optical device of the present invention is applicable to the manufacture method that possesses the semiconductor optical device of electrode in waveguide crestal culmination portion.
Claims (4)
1. the manufacture method of a semiconductor optical device comprises:
On semiconductor substrate, stack gradually the 2nd semiconductor layer and coat of metal that the semiconductor layer by the GaN class of the 1st semiconductor layer, active layer, the 2nd conduction type of the 1st conduction type forms, form the operation of semiconductor stacked structure;
On the surface of this semiconductor stacked structure, apply resist, utilize photomechanics to form to comprise the operation that has corresponding to the 1st resist figure of the banded resist film part of the width of waveguide ridge;
As mask, utilize etching to remove the operation that the 2nd semiconductor layer that coat of metal forms the semiconductor layer by the GaN class exposes in the 1st resist figure;
By with the 1st resist figure as mask, utilize dry ecthing to remove the part of the upper surface side of the 2nd semiconductor layer that the semiconductor layer by the GaN class forms, the recess of the part of the 2nd semiconductor layer that forms residual in the bottom to be formed by the semiconductor layer of GaN class forms the operation of waveguide ridge thus;
Remove the 1st resist figure, contain recess and the most surperficial on have on the surface of semiconductor stacked structure of waveguide ridge of coat of metal, form the operation of the 1st dielectric film;
The surface of exposing the 1st dielectric film that in waveguide crestal culmination portion, forms, simultaneously, the resist film on the surface that the 2nd semiconductor layer surface that forms by means of the semiconductor layer by the GaN class that has than waveguide ridge is high and lower than the surface of the 1st dielectric film in the waveguide crestal culmination portion, bury the 1st dielectric film with the recess of waveguide ridge adjacency underground, form the operation of the 2nd resist figure;
As mask, utilize dry ecthing to remove the 1st dielectric film in the 2nd resist figure, expose the operation of the metal coating laminar surface of waveguide ridge;
Utilize wet etching to remove coat of metal, expose the operation of the 2nd semiconductor layer that the semiconductor layer by the GaN class forms; And
On the surface of the 2nd semiconductor layer that the semiconductor layer by the GaN class of the waveguide ridge that exposes forms, form the operation of electrode layer.
2. the manufacture method of semiconductor optical device according to claim 1 is characterized in that,
In the operation that forms semiconductor stacked structure, the 2nd semiconductor layer contiguous metal protective layer that the semiconductor layer by the GaN class of the 2nd conduction type forms, and have contact layer.
3. the manufacture method of semiconductor optical device according to claim 1 is characterized in that,
The operation that forms the 2nd resist figure comprises:
On the 1st dielectric film, apply resist, and formation is in abutting connection with the operation of the thicker resist film of the thickness of the resist film of the Film Thickness Ratio waveguide crestal culmination portion of the resist film of the recess of waveguide ridge; With
Similarly from the surface removal resist of this resist film, the resist film of the recess of residual and waveguide ridge adjacency, the operation that the 1st dielectric film of waveguide crestal culmination portion is exposed.
4. the manufacture method of a semiconductor optical device comprises:
On the surface of the semiconductor stacked structure of the 2nd semiconductor layer that the semiconductor layer by the GaN class of the 1st semiconductor layer that has stacked gradually the 1st conduction type on the substrate, active layer, the 2nd conduction type forms and coat of metal, the coating resist, utilize photomechanics, form and to comprise the operation that has corresponding to the 1st resist figure of the resist film part of the shape of waveguide ridge;
As mask, utilize etching to remove coat of metal in the 1st resist figure, the operation that the 2nd semiconductor layer that the semiconductor layer by the GaN class is formed exposes;
By with the 1st resist figure as mask, utilize dry ecthing to remove the part of the upper surface side of the 2nd semiconductor layer that the semiconductor layer by the GaN class forms, and the recess of the part of the 2nd semiconductor layer that forms residual in the bottom to form by the semiconductor layer of GaN class, form the operation of waveguide ridge thus;
Remove the 1st resist figure, contain recess and the most surperficial on have on the surface of semiconductor stacked structure of waveguide ridge of coat of metal, form the operation of the 1st dielectric film;
The surface of exposing the 1st dielectric film that forms in the waveguide crestal culmination portion, and the resist film on the surface that the 2nd semiconductor layer surface that forms by means of the semiconductor layer by the GaN class that has than waveguide ridge is high and lower than the surface of the 1st dielectric film in the waveguide crestal culmination portion, bury the 1st dielectric film with the recess of waveguide ridge adjacency underground, form the operation of the 2nd resist figure;
As mask, utilize dry ecthing to remove the 1st dielectric film in the 2nd resist figure, expose the operation of the metal coating laminar surface of waveguide ridge;
Utilize wet etching to remove coat of metal, expose the operation of the 2nd semiconductor layer that the semiconductor layer by the GaN class forms; And
On the surface of the 2nd semiconductor layer that the semiconductor layer by the GaN class of the waveguide ridge that exposes forms, form the operation of electrode layer.
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| JP2006281433 | 2006-10-16 | ||
| JP2006-281433 | 2006-10-16 | ||
| JP2007-232318 | 2007-09-07 | ||
| JP2007232318A JP4142084B2 (en) | 2006-10-16 | 2007-09-07 | Semiconductor optical device manufacturing method |
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| JP2010147117A (en) * | 2008-12-17 | 2010-07-01 | Mitsubishi Electric Corp | Manufacturing method of nitride semiconductor device |
| JP2014192475A (en) * | 2013-03-28 | 2014-10-06 | Japan Oclaro Inc | Nitride optical semiconductor element and optical semiconductor device |
| CN107257082B (en) * | 2017-07-05 | 2020-03-17 | 青岛海信宽带多媒体技术有限公司 | Manufacturing method of electrode contact window of ridge waveguide laser |
| CN113889841A (en) * | 2020-07-02 | 2022-01-04 | 华星光通科技股份有限公司 | Etching protection layer structure of metal semiconductor junction and manufacturing method thereof |
| US11959004B2 (en) * | 2020-12-07 | 2024-04-16 | Texas Instruments Incorporated | Wet anisotropic etching of silicon |
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| CN1380726A (en) * | 2001-04-12 | 2002-11-20 | 索尼株式会社 | Semiconductor laser device |
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| EP0450255B1 (en) * | 1990-04-06 | 1994-07-06 | International Business Machines Corporation | Process for forming the ridge structure of a self-aligned semiconductor laser |
| JP3505780B2 (en) * | 1994-05-16 | 2004-03-15 | ソニー株式会社 | Semiconductor light emitting device |
| JP3264179B2 (en) * | 1996-07-10 | 2002-03-11 | 松下電器産業株式会社 | Semiconductor light emitting device and method of manufacturing the same |
| JPH10117038A (en) * | 1996-10-15 | 1998-05-06 | Fujitsu Ltd | Manufacture of optical semiconductor device |
| JP2000332357A (en) * | 1999-05-20 | 2000-11-30 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JP2002151418A (en) * | 2000-11-14 | 2002-05-24 | Sony Corp | Nitride-family iii-v compound semiconductor substrate and method of manufacturing thereof, and semiconductor device and method of manufacturing thereof |
| JP2004273752A (en) * | 2003-03-07 | 2004-09-30 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor light emitting element |
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| JP平4-48670A 1992.02.18 |
| JP特开2000-340880A 2000.12.08 |
| JP特开2001-308461A 2001.11.02 |
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| CN101276993A (en) | 2008-10-01 |
| JP4752867B2 (en) | 2011-08-17 |
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