CN101275995A

CN101275995A - Global position system GPS receiver radio frequency chip

Info

Publication number: CN101275995A
Application number: CNA2008100178507A
Authority: CN
Inventors: 李迪; 魏建让; 周文益
Original assignee: XIAN HUAXUN MICROELECTRONIC CO Ltd
Current assignee: XIAN HUAXUN MICROELECTRONIC CO Ltd
Priority date: 2008-03-28
Filing date: 2008-03-28
Publication date: 2008-10-01

Abstract

A global positioning system GPS receiver radio frequency chip comprises a first low-noise amplifier and a second low-noise amplifier. The radio frequency input signal enters the first low-noise amplifier which is connected with the second low-noise amplifier that is connected with a frequency mixer. The frequency mixer is connected with a frequency synthesizer. The generated signal is executed with frequency mixing. The frequency mixer is connected with an intermediate frequency filter which is connected with an automatic gain control amplifier that is connected with a digital-analog signal converter. The outputted data signal enters a baseband. The baseband signal, namely a pulse width modulating signal is transmitted to an automatic gain module. Compared with former 0.35 micrometer germanium-silicon technique, the invention has the advantages of greatly improved power consumption and capability, better versatility, and excellent social and economic benefit.

Description

A kind of global position system GPS receiver radio frequency chip

Technical field

The present invention relates to a kind of video receiver chip, the monolithic machine integrated radio frequency chip that is specially adapted to use in the GPS receiver.

Background technology

Previous global position system GPS radio frequency chip adopts 0.35 micron germanium silicon technology, chip area is big, power consumption is higher, every performance index aspect is in perfect inadequately state, and original global position system GPS radio frequency chip design is that first order low noise amplifier with receiving satellite signal is placed on outside the sheet, do not possess versatility.

Previous global position system GPS radio frequency chip only is applicable to the GPS of USA GPS, and with the Galilean satellite system, the GLONASS system does not have compatibility.

Summary of the invention

The objective of the invention is to overcome above-mentioned prior art deficiency, a kind of global position system GPS receiver radio frequency chip is provided.This chip has better generality.

Technical scheme of the present invention is to solve like this:

A kind of global position system GPS receiver radio frequency chip, comprise first low noise amplifier, second low noise amplifier, radio-frequency input signals enters first low noise amplifier, and first low noise amplifier connects second low noise amplifier, and second low noise amplifier connects frequency mixer; Frequency mixer is connected with frequency synthesizer, and the signal of generation carries out mixing, and frequency mixer connects intermediate-frequency filter; Intermediate-frequency filter connects automatic gain control amplifier, and automatic gain control amplifier links to each other with the digital and analogue signals converter, and the data-signal of output enters base band, baseband signal, and promptly pulse-width signal is sent into the automatic gain module.

The RFIN of described first low noise amplifier is a radio-frequency (RF) signal input end, and OUT is the radiofrequency signal output terminal; Voltage source V DD links to each other with the source end of transistor M1; The drain terminal of transistor M1 links to each other with the drain terminal of M2, and the drain terminal of transistor M1 links to each other with the grid end of transistor M2, transistor M5, transistor M6 simultaneously; Wherein, connect an end of capacitor C 1 between the grid end of transistor M2 and transistor M5, the other end ground connection of capacitor C 1; The source end of transistor M2 links to each other with the drain terminal of transistor M3, and the drain terminal of transistor M3 links to each other with the grid end of transistor M3, link to each other with an end of resistance R 1 simultaneously, and the other end of resistance R 1 and transistor M7, the grid end of M8 links to each other; Connect the drain terminal of transistor M4 between transistor M3 and the resistance R 1, the source end of transistor M4 links to each other with ground; Transistor M3, transistor M7, the source end of transistor M8 all links to each other with ground; Transistor M7 links to each other with the drain terminal of transistor M8, links to each other with the source end of transistor M5 and transistor M6 simultaneously; The drain terminal of transistor M5 and transistor M6 connects output terminal.

The INPUT of described second low noise amplifier is the radio-frequency (RF) signal input end that comes from first low noise amplifier, and OUTPUT is the radio-frequency (RF) output end of first low noise amplifier; Voltage source V DD divides two-way, and one the tunnel links to each other with an end of capacitor C 1, the other end and inductance L 1, capacitor C 4, transistor M7, and transistor M8, transistor M9, the source end of transistor M10 links to each other; The other end ground connection VSS of capacitor C 1; Transistor M7, transistor M8, transistor M9, the drain terminal of transistor M10 be respectively at capacitor C 5, capacitor C 6, and capacitor C 7, an end of capacitor C 8 links to each other; Inductance L 1 and capacitor C 4, capacitor C 5, capacitor C 6, capacitor C 7, the other end of capacitor C 8 all links to each other with output terminal OUTPUT; Bias source Ibias enters the source end of transistor M1, and the drain terminal of transistor M1 connects the drain terminal of transistor M2; The drain terminal of transistor M2 and grid end join, and the grid end with transistor M5 joins simultaneously; Connect an end of capacitor C 2 between transistor M2 and the transistor M5 grid, the other end ground connection VSS of capacitor C 2; The drain terminal of transistor M3 connects the source end of transistor M2, simultaneously drain terminal and the grid end short circuit of transistor M3; The grid end of transistor M3 divides two-way, and one the tunnel joins with an end of resistance R 1, and one the tunnel joins with the drain terminal of transistor M6; The source end ground connection VSS of transistor M6; The other end of resistance R 1 divides two-way, a termination transistor M4 grid end, and another road connects capacitor C 3; Capacitor C 3 other end ground connection VSS; The source end ground connection VSS of transistor M4.

The present invention compares with 0.35 original germanium silicon technology, no matter is performance, or power consumption, and chip area all is greatly improved and improves; Simultaneously, original GPS RF chip design is that the first order low noise amplifier with receiving satellite signal is placed on outside the sheet, and the present invention has been integrated into first order low noise amplifier in the radio frequency chip, has better generality.

Description of drawings

Fig. 1 is an one-piece construction schematic block diagram of the present invention;

Fig. 2 is the circuit theory diagrams of first low noise amplifier of Fig. 1;

Fig. 3 is the circuit theory diagrams of second low noise amplifier of Fig. 1;

Fig. 4 is the schematic diagram of the mixer of Fig. 1;

Fig. 5 is the schematic diagram of the intermediate-frequency filter circuit of Fig. 1;

Fig. 6 is the circuit theory diagrams of the operational amplifier (OPAMP) of Fig. 5;

Fig. 7 is the circuit theory diagrams of the automatic gaining controling signal amplifier of Fig. 1;

Fig. 8 is the circuit theory diagrams of the modulus signal converter of Fig. 1;

Embodiment

Accompanying drawing is embodiments of the invention;

Below in conjunction with accompanying drawing summary of the invention of the present invention is described further:

With reference to shown in Figure 1, with first low noise amplifier 2, second low noise amplifier 3, frequency mixer 4, intermediate-frequency filter 7, frequency synthesizer 5, automatic gaining controling signal amplifier 8, analog to digital converter 9 integrated whole video receiver chips, the radiofrequency signal 1 of described input enters first low noise amplifier 2, the output signal of first low noise amplifier 2 enters second low noise amplifier 3, the output signal of second low noise amplifier 3 enters frequency mixer 4, the output signal of frequency mixer 4 enters intermediate-frequency filter 7, the output signal of intermediate-frequency filter 7 enters automatic gaining controling signal amplifier 8, the output signal of automatic gaining controling signal amplifier 8 enters modulus signal converter 10, and modulus signal converter 10 output signal SIGN and MAG enter baseband portion; The output signal of frequency synthesizer 5 is a local oscillated signal 6, and local oscillated signal 6 enters frequency mixer 4.After radiofrequency signal enters integrated radio frequency chip, at first amplify, and guarantee extremely low noise figure by 2 pairs of signals of first low noise amplifier; Signal is delivered to second low noise amplifier 3 after amplifying, further amplify; Signal enters frequency mixer 4 subsequently, and 4 li 6 pairs of radiofrequency signals of local oscillated signal 1 that provide with frequency synthesizer 5 of frequency mixer are carried out down coversion, and signal frequency is dropped to intermediate frequency range; Enter automatic gaining controling signal amplifier 8 after intermediate-freuqncy signal process intermediate-frequency filter 7 filtering that obtain and amplify, its gain coefficient size is determined by the strong and weak degree of satellite-signal, and can regulate in a big way; Intermediate-freuqncy signal is through being amplified into modulus signal converter 10, and its effect is that analog intermediate frequency signal is sampled as digital signal and output, promptly is quantified as the binary data-signal of two-way: SIGN and MAG; The signal of SIGN and MAG enters Base-Band Processing, and simultaneously baseband feedback gives the empty control module of automatic gain 8 one pulse-width signals 9, regulates the gain size of automatic gain module, exports signal that the two-way amplitude meets the demands thus and enters base band and handle.

With reference to shown in Figure 2, RFIN is a radio-frequency (RF) signal input end among the figure, and OUT is the radiofrequency signal output terminal; Voltage source V DD links to each other with the source end of transistor M1; The drain terminal of transistor M1 links to each other with the drain terminal of M2, and the drain terminal of transistor M1 links to each other with the grid end of transistor M2, M5, M6 simultaneously; Wherein, connect an end of capacitor C 1 between the grid end of transistor M2 and M5, the other end ground connection of capacitor C 1; The source end of transistor M2 links to each other with the drain terminal of transistor M3, and the drain terminal of transistor M3 links to each other with the grid end of transistor M3, link to each other with an end of resistance R 1 simultaneously, and the other end of resistance R 1 and transistor M7, the grid end of M8 links to each other; Connect the drain terminal of transistor M4 between transistor M3 and the resistance R 1, the source end of transistor M4 links to each other with ground; Transistor M3, M7, the source end of M8 all links to each other with ground; The drain terminal of transistor M7 and M8 links to each other, and links to each other with the source end of transistor M5 and M6 simultaneously; The drain terminal of transistor M5 and M6 connects output terminal.

With reference to shown in Figure 3, INPUT is the radio-frequency (RF) signal input end that comes from first low noise amplifier 2, and OUTPUT is the radio-frequency (RF) output end of first low noise amplifier 2; Voltage source V DD divides two-way, and one the tunnel links to each other with an end of capacitor C 1, the other end and inductance L 1, capacitor C 4, transistor M7, and M8, M9, the source end of M10 links to each other; The other end ground connection VSS of capacitor C 1; And transistor M7, M8, M9, the drain terminal of M10 be respectively at capacitor C 5, C6, and C7, the end of C8 links to each other; Inductance L 1 and capacitor C 4, C5, C6, C7, the other end of C8 all link to each other with output terminal OUTPUT; Bias source Ibias enters the source end of transistor M1, and the drain terminal of transistor M1 connects the drain terminal of transistor M2; The drain terminal of transistor M2 and grid end join, and the grid end with transistor M5 joins simultaneously; Connect an end of capacitor C 2 between transistor M2 and the M5 grid, the other end ground connection VSS of capacitor C 2; The drain terminal of transistor M3 connects the source end of transistor M2, simultaneously drain terminal and the grid end short circuit of transistor M3; The grid end of transistor M3 divides two-way, and one the tunnel joins with an end of resistance R 1, and one the tunnel joins with the drain terminal of transistor M6; The source end ground connection VSS of transistor M6; The other end of resistance R 1 divides two-way, a termination transistor M4 grid end, and another road connects capacitor C 3; Capacitor C 3 other end ground connection VSS; The source end ground connection VSS of transistor M4.

With reference to shown in Figure 4; VDD is a voltage source among the figure, and Ibias is the bias current sources input, and VSS is an earth terminal, and LO_P and LO_N are frequency synthesizer output signal input end, and RFIN is a rf inputs, and IFN and IFP are medium frequency output end; Current offset source Ibias enters the drain terminal of transistor M1, the drain terminal of the source termination transistor M2 of transistor M1, and the drain terminal of transistor M2 and grid end short circuit, the source end ground connection VSS of transistor M2; The grid end of transistor M2 divides two-way, the end of one road connecting resistance R1, and one the tunnel connects the drain terminal of transistor M3, the source end ground connection of transistor M3, the other end of resistance R 1 divides two-way, and one the tunnel meets transistor M4, M5, M12, M15, the grid end of M16; Another road connects an end of capacitor C 1, the other end ground connection of capacitor C 1; The drain terminal of transistor M4 divides two-way, one road connecting resistance R3, and another road connects an end of capacitor C 2, the other end ground connection of capacitor C 2; The end of the other end connecting resistance R2 of resistance R 3, another termination voltage source V DD of resistance R 2; The source end ground connection of transistor M5, the end of drain terminal connecting resistance R6, the other end of resistance R 6 divides two-way, the end of one road connecting resistance R5, another road connects the drain terminal of transistor M7, termination voltage source, the source VDD of transistor M7; The other end of resistance R 5 divides two-way, the end of one road connecting resistance R4, and another road connects the drain terminal of transistor M6, the termination voltage source, source of transistor M6; Transistor M5 drain terminal connects the input end in parallel that another road enters capacitor C 3 and C4, the other end ground connection of C3 and C4; The source end ground connection of transistor M12, drain terminal and transistor M10, the source end of the M11 node that links to each other, with transistor M10, the transistor M13 in addition that the continuous node of the source end of M11 joins, the drain terminal of M14, the drain terminal of the source termination transistor M15 of transistor M13, the drain terminal of transistor M15 joins with ground; The drain terminal of the drain terminal of transistor M14 and transistor M16 joins, and the source termination of transistor M16 is gone into ground; Transistor M10, the input frequency signal LO_P and the LO_N of the grid termination frequency synthesizer of M11, drain terminal one road connecting resistance R8 of transistor M10, the one tunnel connects capacitor C 5; The other end of resistance R 8 links to each other with the source end of transistor M8, and the drain terminal of transistor M8 meets voltage source V DD; Another road of the drain terminal of transistor M10 connects an end of capacitor C 5, and the other end connecting resistance R7 of capacitor C 5 connects the grid of transistor M8 simultaneously; Another termination voltage source V DD of resistance R 7; Drain terminal one road connecting resistance R10 of transistor M11, the one tunnel connects capacitor C 8; The other end of resistance R 10 links to each other with the source end of transistor M9, and the drain terminal of transistor M9 meets voltage source V DD; Another road of the drain terminal of transistor M11 connects an end of capacitor C 8, and the other end connecting resistance R9 of C8 connects the grid of transistor M9 simultaneously; Another termination voltage source V DD of resistance R 9; Rf inputs RFIN one tunnel enters the grid of transistor M23, the end of another road connecting resistance R17, the end of the other end connecting resistance R18 of resistance R 17, the grid of the other end access transistor M24 of resistance R 18; The source end of transistor M23 links to each other with the source end of transistor M24, the transistor that links to each other with this node has M25, M26, the drain terminal of M27, the source end ground connection of transistor M27, the drain terminal of the source termination transistor M28 of transistor M25, the drain terminal of the source termination transistor M29 of transistor M26, the equal ground connection of source end of transistor M28 and M29; The source end that the drain terminal of transistor M23 meets transistor M19 and the M20 node that links to each other, the drain terminal of transistor M19 meets output terminal IFP, connects capacitor C 9 simultaneously, C10, C13, C14, resistance R 11, the end of R12 and the drain terminal of transistor M21, and the source end of transistor M21 links to each other with the source end of transistor M22; The source end that the drain terminal of transistor M24 meets transistor M21 and the M22 node that links to each other, the drain terminal of transistor M22 meets output terminal IFN, connects capacitor C 11 simultaneously, C12, C13, C14, resistance R 13, the end of R14 and the drain terminal of transistor M20; Another termination voltage source V DD of resistance R 12 and R13; The grid end of transistor M22 also links to each other with the grid end of transistor M19, and links to each other with capacitor C 6, and the other end of C6 is connected in the source end of transistor M8; The grid end short circuit of transistor M20 and M21, and link to each other with an end of capacitor C 7, the other end of C7 links to each other with the source end of transistor M9; Resistance R 16 and R18 also respectively with transistor M4, the drain terminal of M5 links to each other; The source end of transistor M30 links to each other with voltage source V DD, grid end and transistor M31, and the grid end of M32 links to each other, and the drain terminal of transistor M30 links to each other with the source end point of contact of transistor M19 and M20; The drain terminal of transistor M31 and transistor M21, the source end point of contact of M22 links to each other; The source end of transistor M31 links to each other with voltage source; The grid leak of transistor M32 links to each other, and the source end links to each other with voltage source, and drain terminal also links to each other with the drain terminal of transistor M33; The grid end one tunnel of transistor M33 links to each other with the grid end of transistor M27, and one the tunnel links to each other with resistance R 19, and one the tunnel links to each other the other end ground connection of C17 with capacitor C 17; The other end of resistance R 19 is connected with the drain terminal of transistor M34, the source end ground connection of transistor M34; The drain terminal of transistor M34 links to each other with the drain terminal of transistor M35 simultaneously; The drain terminal of transistor M35 and grid end short circuit; The drain terminal of transistor M35 links to each other with the source end of vM36, and the drain terminal of transistor M36 meets Ibias; Transistor M37, M38, M39, the three end short circuits of M40 all meet VDD.

With reference to shown in Figure 5, INPUT is the signal input end of intermediate frequency that comes from frequency mixer 4, and OUTPUT is the filtered intermediate-freuqncy signal output terminal of process; S1-S6 is a switch control module among the figure; The operational amplifier of OPAMP for being connected with output terminal; The signal of phase phasic difference 90 degree that come out from frequency mixer 4 enters switch S 1 and S2 respectively; Divide two-way through the signal after the switch S 1, one road connecting resistance R1, another road connecting resistance R2, and the other end of resistance R 1 and R2 joins, and this node divides three the tunnel again, connects the end of shunt capacitance C1 and C2 respectively, and one the road inserts switch S 3, a road inserts switch S 5; Divide two-way through the output signal of switch S 3, one road connecting resistance R5, another road connecting resistance R6, and the other end of resistance R 5 and R6 joins, and join with an end of capacitor C 3; Output signal through switch S 5 is divided two-way, one road connecting resistance R9, another road connecting resistance R10, and the other end of resistance R 9 and R10 short circuit mutually, this node divides two-way again, one the tunnel joins with an end of capacitor C 3, is connected into the utmost point of output terminal OUTPUT, and one the road flows into the input end of operational amplifier OPAMP; Two-way is divided, one road connecting resistance R3, another road connecting resistance R4 through the signal after the switch S 2 in another road of INPUT signal, and the other end of resistance R 3 and R4 joins, and this node divides three the tunnel again, connects the end of shunt capacitance C1 and C2 respectively, one the road inserts switch S 4, a road inserts switch S 6; Output signal through switch S 4 is divided two-way, one road connecting resistance R7, another road connecting resistance R8, and the other end of resistance R 7 and R8 short circuit mutually, this node divides two-way again, one the tunnel joins with an end of capacitor C 4, is connected into the utmost point of output terminal OUTPUT, and one the road flows into the input end of operational amplifier OPAMP; Two outputs of OPAMP are connected with the input of intermediate-frequency filter; Divide two-way through the output signal of switch S 6, one road connecting resistance R11, another road connecting resistance R12, and the other end of resistance R 11 and R12 joins, and join with an end of capacitor C 4, connect another utmost point of output terminal OUTPUT.

With reference to shown in Figure 6, INPUT is a differential input signal, and OUTPUT is the differential output signal of OPAMP operational amplifier; VCM is a common mode control incoming level; Vb is a bias level; Differential input signal INPUT goes into from the grid termination of transistor M4 and M7; The source end termination of M4 and M7 is joined with the drain terminal of transistor M5; The source end ground connection of M5; The drain terminal of M4 connects the drain terminal of transistor M3, and the drain terminal of transistor M4 connects the grid end of transistor M1 simultaneously; Termination voltage source, the source VDD of transistor M3; The source end termination of M4 and M7 is joined with the drain terminal of transistor M5; The source end ground connection of M5; The drain terminal of M7 connects the drain terminal of transistor M6, and the drain terminal of transistor M7 connects the grid end of transistor M8 simultaneously; Termination voltage source, the source VDD of transistor M6; The drain terminal of transistor M1 and voltage source V DD join, and the drain terminal of drain terminal and transistor M2 joins; The source end ground connection of transistor M2, grid termination level Vb; The drain terminal of transistor M8 and voltage source V DD join, and the drain terminal of drain terminal and transistor M9 joins; The source end ground connection of transistor M9, grid termination level Vb; The drain terminal of transistor M2 and transistor M9 extremely links to each other with one of output OUTPUT respectively; The grid of common mode electrical level VCM access transistor M13 and transistor M14; The drain terminal of transistor M13 and transistor M14 is short circuit mutually, and node connects the drain terminal of transistor M16, the grid of transistor M16 and drain terminal short circuit; The source end ground connection of transistor M16; The source end short circuit of transistor M13 and transistor M10, node connects the drain terminal of transistor M12, termination voltage source, the source VDD of transistor M12; The source end short circuit of transistor M14 and transistor M15, node connects the drain terminal of transistor M17, termination voltage source, the source VDD of transistor M17; The drain terminal short circuit of transistor M10 and transistor M15, the short circuit point connects the drain terminal of transistor M11, the drain terminal of transistor M11 and grid end short circuit; Transistorized source end ground connection;

With reference to shown in Figure 7, INPUT is the differential signal input of intermediate-frequency filter 7 outputs; OUTPUT is the differential output signal of automatic gaining controling signal amplifier 8; Vbias is a bias level; Vcont1 and Vcont2 are the signal controlling level; The utmost point of input signal INPUT connects an end of capacitor C 1, and another utmost point connects an end of capacitor C 2; Another termination transistor M1 of capacitor C 1 and the grid of M3; The grid of transistor M1 and M3 is a short circuit; The source shorted of the source electrode of transistor M1 and transistor M2, the drain electrode of short circuit point access transistor M9; The grid of transistor M9 meets control voltage Vcont; The source electrode that meets transistor M9 connects the drain electrode of transistor M13, and the grid of M13 meets bias level Vbias, and source electrode inserts ground; The end of the drain terminal connecting resistance R1 of transistor M1, another termination voltage source V DD of resistance R 1; Another termination transistor M2 of capacitor C 2 and the grid of M4; The grid of transistor M2 and M4 is a short circuit; The source shorted of the source electrode of transistor M3 and transistor M4, the drain electrode of short circuit point access transistor M10; The grid of transistor M10 meets control voltage Vcont1; The source electrode that meets transistor M10 connects the drain electrode of transistor M14, and the grid of M14 meets bias level Vbias, and source electrode inserts ground; The end of the drain terminal connecting resistance R2 of transistor M2, another termination voltage source V DD of resistance R 2; The drain terminal of transistor M1 and transistor M2 connects capacitor C 3 respectively, the end of C4, capacitor C 3, the other end difference access transistor M5 of C4 and the grid of M6; The grid of transistor M5 and M6 is a short circuit; The source shorted of the source electrode of transistor M5 and transistor M6, the drain electrode of short circuit point access transistor M11; The grid of transistor M11 meets control voltage Vcont; The source electrode that meets transistor M11 connects the drain electrode of transistor M15, and the grid of M15 meets bias level Vbias, and source electrode inserts ground; The end of the drain terminal connecting resistance R3 of transistor M5, another termination voltage source V DD of resistance R 3; Another termination transistor M6 of capacitor C 4 and the grid of M8; The grid of transistor M6 and M8 is a short circuit; The source shorted of the source electrode of transistor M7 and transistor M8, the drain electrode of short circuit point access transistor M12; The grid of transistor M12 meets control voltage Vcont2; The source electrode that meets transistor M12 connects the drain electrode of transistor M16, and the grid of M16 meets bias level Vbias, and source electrode inserts ground; The end of the drain terminal connecting resistance R4 of transistor M6, another termination voltage source V DD of resistance R 4; Transistor M13 wherein, M14, M15, the grid of M16 is a short circuit.

With reference to shown in Figure 8, INPUT is the differential input signal end; OUTPUT is an output signal; Vbias is a bias level; Differential input signal INPUT enters the grid of transistor M6 and M7 respectively; The source end short circuit of transistor M6 and transistor M7, the short circuit point connects the drain terminal of transistor M11, the source end ground connection of M11; The grid of M11 meets bias voltage Vbias; The drain terminal of transistor M6 divides three tunnel, one tunnel drain terminal that meets transistor M2, and one the tunnel connects the drain terminal of transistor M4, and one the tunnel connects the grid of transistor M1; The grid short circuit of the grid of transistor M2 and transistor M3, and with the drain electrode short circuit of M2; Termination voltage source, the source VDD of transistor M2 and transistor M3; The source electrode of transistor M1 meets voltage source V DD, and drain electrode connects the drain electrode of transistor M9; The drain and gate short circuit of transistor M9, and join with the grid of transistor M10; The drain terminal of transistor M7 divides three tunnel, one tunnel drain terminal that meets transistor M5, and one the tunnel connects the drain terminal of transistor M3, and one the tunnel connects the grid of transistor M8; The grid short circuit of the grid of transistor M5 and transistor M4, and with the drain electrode short circuit of M5; Termination voltage source, the source VDD of transistor M5 and transistor M4; The source electrode of transistor M8 meets voltage source V DD, and drain electrode connects the drain electrode of transistor M10; The source end of transistor M10 and transistor M9 is connected;

The present invention can be used among the GPS receiver radio frequency chip HX8130RF, adopts 0.18 micron tsmc technological design to produce, and tests successfully.

Claims

1, a kind of global position system GPS receiver radio frequency chip, comprise first low noise amplifier (2), second low noise amplifier (3), it is characterized in that, radio-frequency input signals (1) enters first low noise amplifier (2), first low noise amplifier (2) connects second low noise amplifier (3), and second low noise amplifier (3) connects frequency mixer (4); Frequency mixer (4) is connected with frequency synthesizer (5), and the signal of generation carries out mixing, and frequency mixer (4) connects intermediate-frequency filter (7); Intermediate-frequency filter (7) connects automatic gain control amplifier (8), automatic gain control amplifier (8) links to each other with digital and analogue signals converter (10), the data-signal of output enters base band, baseband signal, and promptly pulse-width signal (9) is sent into automatic gain module (8).

2, a kind of global position system GPS receiver radio frequency chip according to claim 1 is characterized in that, the RFIN of described first low noise amplifier (2) is a radio-frequency (RF) signal input end, and OUT is the radiofrequency signal output terminal; Voltage source V DD links to each other with the source end of transistor M1; The drain terminal of transistor M1 links to each other with the drain terminal of M2, and the drain terminal of transistor M1 links to each other with the grid end of transistor M2, transistor M5, transistor M6 simultaneously; Wherein, connect an end of capacitor C 1 between the grid end of transistor M2 and transistor M5, the other end ground connection of capacitor C 1; The source end of transistor M2 links to each other with the drain terminal of transistor M3, and the drain terminal of transistor M3 links to each other with the grid end of transistor M3, link to each other with an end of resistance R 1 simultaneously, and the other end of resistance R 1 and transistor M7, the grid end of M8 links to each other; Connect the drain terminal of transistor M4 between transistor M3 and the resistance R 1, the source end of transistor M4 links to each other with ground; Transistor M3, transistor M7, the source end of transistor M8 all links to each other with ground; Transistor M7 links to each other with the drain terminal of transistor M8, links to each other with the source end of transistor M5 and transistor M6 simultaneously; The drain terminal of transistor M5 and transistor M6 connects output terminal.

3, a kind of global position system GPS receiver radio frequency chip according to claim 1, it is characterized in that, the INPUT of described second low noise amplifier (3) is for coming from the radio-frequency (RF) signal input end of first low noise amplifier (2), and OUTPUT is the radio-frequency (RF) output end of first low noise amplifier (2); Voltage source V DD divides two-way, and one the tunnel links to each other with an end of capacitor C 1, the other end and inductance L 1, capacitor C 4, transistor M7, and transistor M8, transistor M9, the source end of transistor M10 links to each other; The other end ground connection VSS of capacitor C 1; Transistor M7, transistor M8, transistor M9, the drain terminal of transistor M10 be respectively at capacitor C 5, capacitor C 6, and capacitor C 7, an end of capacitor C 8 links to each other; Inductance L 1 and capacitor C 4, capacitor C 5, capacitor C 6, capacitor C 7, the other end of capacitor C 8 all links to each other with output terminal OUTPUT; Bias source Ibias enters the source end of transistor M1, and the drain terminal of transistor M1 connects the drain terminal of transistor M2; The drain terminal of transistor M2 and grid end join, and the grid end with transistor M5 joins simultaneously; Connect an end of capacitor C 2 between transistor M2 and the transistor M5 grid, the other end ground connection VSS of capacitor C 2; The drain terminal of transistor M3 connects the source end of transistor M2, simultaneously drain terminal and the grid end short circuit of transistor M3; The grid end of transistor M3 divides two-way, and one the tunnel joins with an end of resistance R 1, and one the tunnel joins with the drain terminal of transistor M6; The source end ground connection VSS of transistor M6; The other end of resistance R 1 divides two-way, a termination transistor M4 grid end, and another road connects capacitor C 3; Capacitor C 3 other end ground connection VSS; The source end ground connection VSS of transistor M4.