CN101257304A - Double-loop circuit frequency synthesizer and method for tuning gross adjustment loop circuit - Google Patents
Double-loop circuit frequency synthesizer and method for tuning gross adjustment loop circuit Download PDFInfo
- Publication number
- CN101257304A CN101257304A CNA2008101033384A CN200810103338A CN101257304A CN 101257304 A CN101257304 A CN 101257304A CN A2008101033384 A CNA2008101033384 A CN A2008101033384A CN 200810103338 A CN200810103338 A CN 200810103338A CN 101257304 A CN101257304 A CN 101257304A
- Authority
- CN
- China
- Prior art keywords
- frequency
- loop
- counter
- frequency counter
- crossover
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a dual-loop frequency synthesizer and a tuning method of rough adjustment loop thereof, belonging to the field of frequency synthesizer in wireless transceiver. The frequency synthesizer consists of a rough adjustment loop and a fine adjustment loop, wherein the rough adjustment loop comprises a crossover frequency counter, a frequency reference counter, a shifter, a comparator and a finite state machine. The input end of the crossover frequency counter is connected with frequency dividing signal Fdiv of a voltage controlled oscillator of the fine adjustment loop, the shifter is connected with the crossover frequency counter or the frequency reference counter for leftwards shifting the counting value of the crossover frequency counter or the frequency reference counter, the counting values of the crossover frequency counter and the frequency reference counter are respectively output to the comparator, the compare result of which is input to the finite state machine. Compared with prior art, the invention reduces the time of rough tuning as well as provides higher tuning precision according to the needs.
Description
Technical field
The invention relates to the frequency synthesizer in the transceiver, be specifically related to the tuning methods of a kind of double-loop frequency synthesizer and coarse tuning loop thereof.
Background technology
Frequency synthesizer (be called for short frequently and combine) is to be used to obtain a series of devices with high stability and high accuracy frequency, is the key modules in the transceiver, selects local oscillation signal is provided for the transceiver channel, is input to the local oscillator end of frequency mixer, to realize down-conversion.Common frequency synthesizer comprises: phase-locking type (PLL) frequency synthesizer and Direct Digital frequency synthesizer.Because the phase-locking type frequency synthesizer has low-cost and high performance advantage, is particularly suitable for producing clock signal and high-frequency carrier signal with precise frequency, therefore, is widely used in digital mobile communication equipment, high-speed digital system and the high-precision control system.
Fig. 1 is the structural representation of traditional phase-locking type frequency synthesizer.Tradition phase-locking type frequency synthesizer is formed phase-locked loop by frequency divider, phase detection discriminator, charge pump, loop filter and voltage controlled oscillator (VCO).Wherein, the output frequency of VCO obtains crossover frequency through frequency divider, phase detection discriminator compares frequency and the phase place difference between reference frequency and the crossover frequency, exports the pulse signal (this pulse signal and frequency size and phase place difference are proportional) of certain width then; Charge pump is converted to electric current to this pulse signal, carries out low-pass filtering by loop filter at last, produces level and smooth voltage signal; This voltage signal control VCO makes its output correspondent frequency signal, and this frequency signal also is the final output frequency of whole phase-locked loop simultaneously.When whole feedback loop was in the lock state, the output frequency of VCO equaled the product of reference frequency and frequency divider frequency division value, by adjusting the frequency division value of frequency divider, can adjust the output frequency of VCO, thereby obtain a series of frequencies.
The general capacitive reactance pipe that adopts only can reach frequency tuning range about 20% as the VCO maximum of frequency tuning element, and in the application of broadband or multiband, such frequency tuning range may be not enough.And if frequency tuning range is too wide, under the certain condition of control voltage span, the gain meeting of VCO is very high, makes VCO very responsive to the interference on the control line.Along with the reduction of supply voltage, this problem can be more serious.In order to address this problem, people have proposed the digital tuning technology.Adopt switched capacitor array can realize discrete frequency change, realize the coarse tuning of frequency, the meticulous variation of frequency then can be realized by continually varying capacitive reactance pipe by capacitance.Digital tuning technology (frequency coarse adjustment) and analog tuner technology (frequency fine tuning) are combined, can realize very wide frequency tuning range.Therefore on traditional basis, develop and a class double-loop frequency synthesizer based on the single loop frequency synthesizer.Double-loop frequency synthesizer generally comprises coarse adjustment and two loops of fine tuning, and coarse tuning loop is searched for fast to switched capacitor array, and the fine tuning loop then accurately locks frequency by negative feedback.
The frequency rough mode transfer piece that present double-loop frequency synthesizer is adopted generally has following several structure:
1) unifrequency counting manner of comparison: patent of invention ZL02125270 (publication number CN1388649C) has proposed a kind of phase-locked ring type frequency synthesizer with digital coarse tuning loop, the implementation structure of its coarse tuning loop as shown in Figure 2, comprising programmable counter, pulse handle up counter, frequency comparison module and coarse tuning control module.When above-mentioned frequency synthesizer begins operate as normal, at first start the coarse tuning loop, reference frequency is counted, when counting down to certain preset value, the sampling crossover frequency, judge magnitude relationship between crossover frequency (Fdiv) and the reference frequency (Fref) according to the height of sampled value level, determine how saltus step of digital controlled signal according to comparative result then.
Above-mentioned double-loop frequency synthesizer adopts digital mode to carry out the frequency coarse adjustment, has simplified implementation complexity.Although this coarse tuning loop can compare the speed between crossover frequency (Fdiv) and the reference frequency (Fref), be difficult to distinguish fast and slow degree between the two, that is to say rational relatively tolerance limit can't be set.Even crossover frequency and reference frequency are very approaching, if the initial time of two signals does not keep synchronously, this coarse tuning loop can't judge that still both equate.Therefore this coarse tuning structure requires very high to two frequency signals in the synchronism of initial time.
Patent of invention 200510086226 (publication number CN1731681A) has proposed another kind of phase-locking type frequency synthesizer with digital coarse tuning loop, the implementation structure of its coarse tuning loop as shown in Figure 3, comprise count comparator, successive approximation register and the voltage controlled oscillator (VCO) that connect successively, and the input of count comparator links to each other directly with the VCO output.Identical with patent of invention ZL02125270 is, all is only a kind of frequency to be counted, and the former only counts reference frequency, and this patent is only counted the VCO output frequency.Difference is that this patent is directly counted the VCO output frequency, has not only shortened locking time greatly, and the height of reference frequency is not required yet.But under the situation of VCO output frequency very high (for example 6GHz), owing to be subjected to the restriction of digital circuit operating frequency, the count comparator of coarse tuning loop is difficult to keep operate as normal, and high-speed digital circuit must cause the significantly increase of whole frequency synthesizer power consumption.
2) bifrequency counting manner of comparison: document " CMOS PLL Calibration Techniques ", (Adem Aktas andMohammedIsmail, IEEE circuits﹠amp; Devices magazine, vol.4, pp.6-11 has proposed to have the phase-locking type frequency synthesizer of digital adaptation frequency calibration circuit in SEPTEMBER/OCTOBER2004), as shown in Figure 4.The coarse tuning loop part is made up of frequency comparison module (Frequency detector) and control logic (State machine).In the frequency comparison module, reference frequency R and crossover frequency V are counted by two counter modules respectively, after reaching pre-set count values, one of them counter stops counting, judge the frequency magnitude relationship of R and V according to their count results, and then judge that the VCO frequency is higher or on the low side, thereby digital controlled signal is made timely adjustment by the coarse adjustment control circuit.
This structure is setpoint frequency tolerance limit relatively easily, but under the very low situation of reference frequency, the overlong time that coarse tuning loop is required, thus increased whole locking time of frequency synthesizer.And this structure does not solve reference frequency R and the crossover frequency V stationary problem at the counting initial period, can bring the synchronous error of counting, influences last coarse adjustment precision.
In sum, the coarse tuning loop that adopted of existing double-loop frequency synthesizer can't satisfy multiple requirements such as frequency accuracy, coarse adjustment time, synchronous error and power consumption simultaneously.
Summary of the invention
The present invention has overcome deficiency of the prior art, and a kind of double-loop frequency synthesizer is provided, and this structure both can have been dwindled the coarse tuning required time greatly, can obtain higher tuning precision as required again.
Another object of the present invention is to, provide a kind of and the corresponding tuning methods of said structure.
Technical scheme of the present invention is:
A kind of double-loop frequency synthesizer, form by coarse tuning loop and fine tuning loop, wherein, the fine tuning loop comprises the frequency divider that connects successively, phase detection discriminator, charge pump, loop filter and voltage controlled oscillator, wherein the output of the input of frequency divider and voltage controlled oscillator links to each other, it is characterized in that, coarse tuning loop is by the crossover frequency counter, the reference frequency counter, shift unit, comparator and finite state machine are formed, the fractional frequency signal Fdiv of the input of crossover frequency counter and the voltage controlled oscillator of above-mentioned fine tuning loop links to each other, described shift unit is connected with described crossover frequency counter, be used for count value with the above-mentioned crossover frequency counter n position that moves to left, the count value of crossover frequency counter and reference frequency counter is exported to comparator respectively, and the comparative result of comparator is as the input of finite state machine.
A kind of double-loop frequency synthesizer, form by coarse tuning loop and fine tuning loop, wherein, the fine tuning loop comprises the frequency divider that connects successively, phase detection discriminator, charge pump, loop filter and voltage controlled oscillator, wherein the output of the input of frequency divider and voltage controlled oscillator links to each other, it is characterized in that, coarse tuning loop is by the crossover frequency counter, the reference frequency counter, shift unit, comparator and finite state machine are formed, the fractional frequency signal Fdiv of the input of crossover frequency counter and the voltage controlled oscillator of above-mentioned fine tuning loop links to each other, described shift unit is connected with described reference frequency counter, be used for count value with the above-mentioned reference frequency counter n position that moves to left, the count value of crossover frequency counter and reference frequency counter is exported to comparator respectively, and the comparative result of comparator is as the input of finite state machine.
Between above-mentioned reference frequency counter and the crossover frequency counter handshake is arranged.
A kind of coarse tuning loop tuning methods of double-loop frequency synthesizer, its step comprises:
1) incoming frequency of setting the reference frequency counter be above-mentioned fine tuning loop phase frequency detector input reference frequency Fref 2
nDoubly, n is a positive integer;
2) after the crossover frequency rolling counters forward begins, the crossover frequency counter sends handshake to the reference frequency counter, the initial counting of control reference frequency counter;
3) shift unit makes the New count value become 2 of original count value the count value of the crossover frequency counter n position that moves to left
nDoubly;
4) comparator compares the count value of crossover frequency counter and reference frequency counter, obtains the magnitude relationship of reference frequency and crossover frequency;
5) finite state machine is determined digital controlled signal according to the reference frequency of comparator output and the magnitude relationship of crossover frequency, changes the output frequency of voltage controlled oscillator;
6) repeat above-mentioned steps 2), 3), 4) and 5), reach best digital control word or all digital control word search finish until finite state machine, provide coarse adjustment and finish signal.
A kind of coarse tuning loop tuning methods of double-loop frequency synthesizer, its step comprises:
1) incoming frequency of setting the reference frequency counter be above-mentioned fine tuning loop phase frequency detector input reference frequency Fref 2
nDoubly, n is a negative integer;
2) after the reference frequency rolling counters forward begins, the reference frequency counter sends handshake to the crossover frequency counter, the initial counting of control crossover frequency counter;
3) shift unit is with the count value of the reference frequency counter n position counting that moves to left, and the value of this counting is 2 of an original count value
nDoubly;
4) comparator compares the count value of crossover frequency counter and reference frequency counter, obtains the magnitude relationship of reference frequency and crossover frequency;
5) finite state machine is determined digital controlled signal according to the reference frequency of comparator output and the magnitude relationship of crossover frequency, changes the output frequency of voltage controlled oscillator;
6) repeat above-mentioned steps 2), 3), 4) and 5), reach best digital control word or all digital control word search finish until finite state machine, provide coarse adjustment and finish signal.
Described finite state machine adopts one by one dichotomy to determine digital controlled signal.
Compared with prior art, the invention has the beneficial effects as follows:
At first, the present invention counts the pulse of reference frequency and crossover frequency respectively, serves as the counting benchmark with slower frequency, and count value is big more, and counting precision is high more.But, must need very long gate time in order to obtain big count value, thereby cause the coarse adjustment overlong time because fine tuning loop reference frequency is very low.Under the situation that with the crossover frequency is the counting benchmark, reference frequency is high more, and count value is just big more, and counting precision is also just high more.Therefore, adopted higher reference frequency in the coarse tuning loop of the present invention, and passed through coarse adjustment reference frequency (2 of Fref
nDoubly) carry out 2
nFrequency division just can obtain the reference frequency Fref of fine tuning loop, does not need to increase extra derived reference signal.Situation is opposite when n is negative integer, is undertaken 2 by the reference frequency Fref to the fine tuning loop
nFrequency division just can obtain slower coarse adjustment reference frequency CKR, is that the counting benchmark is counted crossover frequency faster with CKR, can obtain bigger count value equally.
Description of drawings
Fig. 1 is the structural representation of traditional phase-locking type frequency synthesizer;
Fig. 2 is the implementation structure figure of coarse tuning loop among the patent of invention ZL02125270;
Fig. 3 is the implementation structure figure of coarse tuning loop in the patent of invention 200510086226;
Fig. 4 is the implementation structure figure that has coarse tuning loop in the frequency synthesizer of digital adaptation frequency calibration circuit;
Fig. 5 is the structural representation of double-loop frequency synthesizer among the present invention;
Fig. 6 is the implementation structure figure (n is a positive integer) of coarse tuning loop among the present invention;
Fig. 7 is the implementation structure figure (n is a negative integer) of coarse tuning loop among the present invention;
Fig. 8 is the schematic diagram of binary chop of the present invention;
Fig. 9 is the oscillogram of coarse adjustment control signal in the simulation result of most preferred embodiment of the present invention;
The final locking frequency spectrum of the most preferred embodiment of the present invention that Figure 10 measures for spectrum analyzer.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
Double-loop frequency synthesizer structure of the present invention as shown in Figure 5, wherein, the fine tuning loop still adopts traditional structure, form by frequency divider, phase detection discriminator, charge pump, loop filter and the voltage controlled oscillator (VCO) that connect successively, wherein the output of the input of frequency divider and VCO links to each other, and it has formed double-loop frequency synthesizer jointly with coarse tuning loop.The structure of coarse tuning loop of the present invention inside is referring to Fig. 6 and Fig. 7.Coarse tuning loop is made up of crossover frequency counter (CNV), reference frequency counter (CNR), shift unit, comparator and five parts of finite state machine (FSM), its concrete annexation is: the fractional frequency signal Fdiv of the input of CNV and VCO links to each other, and the incoming frequency of CNR is 2 of phase frequency detector input reference frequency Fref
nDoubly.When n was positive integer, CNV sent handshake to CNR, the initial counting of control CNR, and when counting finished, shift unit made the New count value become 2 of original count value the count value of the CNV n position that moves to left
nDoubly, the count value of CNR and CNV is exported to comparator, and the comparative result of comparator carries out the state redirect and exports the control corresponding position according to these comparative results FSM as the input of FSM; When n was negative integer, some variations took place in the coarse tuning loop structure, send handshake by CNR to CNV, the initial counting of control CNV, and shift unit makes the New count value become 2 of original count value the count value of the CNR n position that moves to left
nDoubly, all the other annexations are constant.
According to the present invention, with n is that positive integer is an example, the CNV of present embodiment comprises a counter and a small amount of control logic, operation principle is as follows: when the coarse tuning process starts, CNV begins counting and accumulated counts value when the fractional frequency signal rising edge arrives, when CNV began to count, it sent handshake to CNR, and CNR also begins reference frequency is counted.When counting down to preset value, sends CNV the comparison triggering signal, comparator (comparator) compares CNV count value (the n position moves to left) and CNR count value, controls the redirect of finite state machine according to both poor (DIFF) and the magnitude relationship of compare threshold (Delta).If DIFF＞+Delta, illustrate that current VCO frequency is greater than target frequency; If DIFF＜-Delta, illustrate that current VCO frequency is less than target frequency; If-Delta＜DIFF＜+Delta, target frequency is described on the frequency modulation curve of current VCO, the coarse adjustment process finishes.Counting preset value by adjusting CNV and the value of Delta can be controlled the time and the precision of coarse tuning loop.
Finite state machine (FSM) adopts one by one dichotomy (as shown in Figure 8) to determine each position digital signal.Its basic functional principle is as follows: earlier the highest order signal is put 1, other signals put 0, check comparative result (being produced by comparator) behind the one-period.If comparative result shows that 1 is too big, so with the highest order zero clearing; Otherwise highest order still puts 1.Then with inferior high position 1, and keep other invariant positions, check comparative result behind the one-period, finish time high-order setting.The rest may be inferred, all sets up up to all positions.Last FSM keeps everybody value constant, and provides the signal FINISH that setting completed.
With 5 control signals is the tuning process of coarse tuning loop among example explanation the present invention: the adjustable range of VCO is to peak frequency Fmax from minimum frequency Fmin during the supposition coarse adjustment, wherein the control signal of Fmin correspondence is 11111, and the control signal of Fmax correspondence is 00000; Target frequency is Ft, and corresponding control signal is 10011, and then coarse tuning process will divide for 5 steps finished as follows in 5 compare cycles:
When the first step begins, FSM puts 1 with first of control signal is exploratory, and other positions are 0, i.e. coarse adjustment control signal is: 10000, this moment, the crossover frequency of VCO was F1, CNV counts with F1, and CNR counts with reference frequency (CKR), and comparator provides both comparative results, suppose that comparative result is that poor (DIFF) of F1 and CKR is greater than threshold value just relatively, show current frequency greater than target frequency, FSM keeps highest order constant according to this comparative result, and the first step finishes;
Second step is when beginning, FSM is set to 1 to a time high position exploratoryly, be that control bit is 11000, output frequency is F2, poor (DIFF) and the magnitude relationship between the compare threshold that check F2 and CKR according to the method for the first step this moment are supposed DIFF＜negative compare threshold here, show that current frequency is less than target frequency, FSM is time high-order negate, second EOS;
The beginning of the 3rd step, FSM is set to 1 to the 3rd exploratoryly, and promptly control bit is 10100, and output frequency is F3.Poor (DIFF) and the magnitude relationship between the compare threshold that check F3 and CKR according to the method for the first step this moment are supposed DIFF＜negative compare threshold, show current frequency still less than target frequency, and FSM is the 3rd negate, the 3rd EOS;
The beginning of the 4th step, FSM is set to 1 to the 4th exploratoryly, and promptly control bit is 10010, and output frequency is F4.Comparator provides both comparative results, suppose comparative result be poor (DIFF) of F4 and CKR greater than threshold value just relatively, show current frequency once more greater than target frequency, FSM keeps the 4th invariant position, the 4th EOS;
The beginning of the 5th step, FSM is set to 1 to the 5th, and promptly control bit is 10011, and output frequency is F5, sends coarse tuning loop end signal FINISH simultaneously.
So far, the coarse adjustment process finishes, being provided with of each control bit is constant, and the output frequency of VCO is very near target frequency.At this moment, disconnect coarse tuning loop, open the fine tuning loop, the fine tuning locking process that enters double-loop frequency synthesizer.
The tuning methods of above-mentioned novel coarse tuning loop can be realized by following most preferred embodiment.
In the present embodiment, the adjustable range of setting VCO is 850-1900MHz, and target frequency is 948MHz, and the control signal of FSM is 5, and the control signal of setting 850MHz frequency correspondence is 11111, and the control signal of 1900MHz frequency correspondence is 00000.Adopt novel coarse tuning loop shown in Figure 6 to realize the tuning methods of present embodiment, the coarse tuning process of this double-loop frequency synthesizer will be finished in 5 compare cycles.In order to ensure the present embodiment operate as normal, provide a set of configuration data: n=4 below, reference frequency CKR=16MHz, Fref=1MHz, the reference level that VCO connects in the coarse tuning loop course of work is 0.9V.
When the 1st compare cycle begins, FSM puts 1 with first of control signal is exploratory, other positions are 0, and promptly control signal is set as 10000, and this moment, the output frequency of VCO was about 1409MHz (all frequency values given here all are the actual values that obtains by the test to present embodiment);
During the 1st end cycle, through counting relatively, obtain comparative result 1409MHz＞948MHz, therefore the 2nd cycle, the 1st of control signal remains unchanged; Simultaneously put 1 by exploratory for the 2nd, promptly control signal is set as 11000, and then the VCO output frequency is about 1036MHz;
During the 2nd end cycle, through counting relatively, obtain comparative result 1036MHz＞948MHz, therefore the 3rd cycle, the 2nd of control signal remains unchanged; Simultaneously put 1 by exploratory for the 3rd, promptly control signal is set as 11100, and the VCO output frequency is 931MHz;
During the 3rd end cycle, through counting relatively, obtain comparative result 931MHz＜948MHz, therefore the 4th cycle, put 0 by negate for the 3rd of control signal; Simultaneously put 1 by exploratory for the 4th, promptly control signal is set as 11010, and corresponding output frequency is 983MHz;
During the 4th end cycle, through counting relatively, obtain comparative result 983MHz＞948MHz,
Therefore in the 5th cycle, the 4th of control signal remains unchanged; Simultaneously directly put 1 for the 5th, control signal is set as 11011, and corresponding output frequency is 960MHz, and is more approaching with 948MHz, and the coarse adjustment process finishes, and FSM output control signal is 11011, and it is constant that output frequency remains on 960MHz.FSM exports coarse tuning end signal FINISH simultaneously, closes coarse tuning loop, enters the fine tuning process of double-loop frequency synthesizer.
Double-loop frequency synthesizer in the present embodiment has passed through the simulating, verifying of Cadence eda tool and the testing authentication after the flow.The change procedure of control signal in described coarse tuning loop when Fig. 9 has shown emulation.Figure 10 is the last locking frequency spectrum of above-mentioned locking process that spectrum analyzer is measured.
The present invention compares with traditional structure, has both dwindled the coarse tuning required time greatly, can obtain higher tuning precision as required again.
More than by specific embodiment described double-loop frequency synthesizer provided by the present invention with and the coarse tuning loop tuning methods, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to the present invention.
Claims (8)
1, a kind of double-loop frequency synthesizer, form by coarse tuning loop and fine tuning loop, wherein, the fine tuning loop comprises the frequency divider that connects successively, phase detection discriminator, charge pump, loop filter and voltage controlled oscillator, wherein the output of the input of frequency divider and voltage controlled oscillator links to each other, it is characterized in that, coarse tuning loop is by the crossover frequency counter, the reference frequency counter, shift unit, comparator and finite state machine are formed, the fractional frequency signal Fdiv of the input of crossover frequency counter and the voltage controlled oscillator of above-mentioned fine tuning loop links to each other, described shift unit is connected with described crossover frequency counter, be used for count value with the above-mentioned crossover frequency counter n position that moves to left, the count value of crossover frequency counter and reference frequency counter is exported to comparator respectively, and the comparative result of comparator is as the input of finite state machine.
2, double-loop frequency synthesizer as claimed in claim 1 is characterized in that, between above-mentioned reference frequency counter and the crossover frequency counter handshake is arranged.
3, a kind of double-loop frequency synthesizer, form by coarse tuning loop and fine tuning loop, wherein, the fine tuning loop comprises the frequency divider that connects successively, phase detection discriminator, charge pump, loop filter and voltage controlled oscillator, wherein the output of the input of frequency divider and voltage controlled oscillator links to each other, it is characterized in that, coarse tuning loop is by the crossover frequency counter, the reference frequency counter, shift unit, comparator and finite state machine are formed, the fractional frequency signal Fdiv of the input of crossover frequency counter and the voltage controlled oscillator of above-mentioned fine tuning loop links to each other, described shift unit is connected with described reference frequency counter, be used for count value with the above-mentioned reference frequency counter n position that moves to left, the count value of crossover frequency counter and reference frequency counter is exported to comparator respectively, and the comparative result of comparator is as the input of finite state machine.
4, double-loop frequency synthesizer as claimed in claim 3 is characterized in that, between above-mentioned reference frequency counter and the crossover frequency counter handshake is arranged.
5, a kind of coarse tuning loop tuning methods of double-loop frequency synthesizer, its step comprises:
1) incoming frequency of setting the reference frequency counter be above-mentioned fine tuning loop phase frequency detector input reference frequency Fref 2
nDoubly, n is a positive integer;
2) after the crossover frequency rolling counters forward begins, the crossover frequency counter sends handshake to the reference frequency counter, the initial counting of control reference frequency counter;
3) shift unit makes the New count value become 2 of original count value the count value of the crossover frequency counter n position that moves to left
nDoubly;
4) comparator compares the count value of crossover frequency counter and reference frequency counter, obtains the magnitude relationship of reference frequency and crossover frequency;
5) finite state machine is determined digital controlled signal according to the reference frequency of comparator output and the magnitude relationship of crossover frequency, changes the output frequency of voltage controlled oscillator;
6) repeat above-mentioned steps 2), 3), 4) and 5), reach best digital control word or all digital control word search finish until finite state machine, provide coarse adjustment and finish signal.
6, the coarse tuning loop tuning methods of double-loop frequency synthesizer as claimed in claim 5 is characterized in that, described finite state machine adopts one by one dichotomy to determine digital controlled signal.
7, a kind of coarse tuning loop tuning methods of double-loop frequency synthesizer, its step comprises:
1) incoming frequency of setting the reference frequency counter be above-mentioned fine tuning loop phase frequency detector input reference frequency Fref 2
nDoubly, n is a negative integer;
2) after the reference frequency rolling counters forward begins, the reference frequency counter sends handshake to the crossover frequency counter, the initial counting of control crossover frequency counter;
3) shift unit is with the count value of the reference frequency counter n position counting that moves to left, and the value of this counting is 2 of an original count value
nDoubly;
4) comparator compares the count value of crossover frequency counter and reference frequency counter, obtains the magnitude relationship of reference frequency and crossover frequency;
5) finite state machine is determined digital controlled signal according to the reference frequency of comparator output and the magnitude relationship of crossover frequency, changes the output frequency of voltage controlled oscillator;
6) repeat above-mentioned steps 2), 3), 4) and 5), reach best digital control word or all digital control word search finish until finite state machine, provide coarse adjustment and finish signal.
8, the coarse tuning loop tuning methods of double-loop frequency synthesizer as claimed in claim 7 is characterized in that, described finite state machine adopts one by one dichotomy to determine digital controlled signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101033384A CN101257304B (en) | 2008-04-03 | 2008-04-03 | Method for tuning gross adjustment loop circuit of double-loop circuit frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101033384A CN101257304B (en) | 2008-04-03 | 2008-04-03 | Method for tuning gross adjustment loop circuit of double-loop circuit frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101257304A true CN101257304A (en) | 2008-09-03 |
| CN101257304B CN101257304B (en) | 2011-11-09 |
Family
ID=39891825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101033384A Expired - Fee Related CN101257304B (en) | 2008-04-03 | 2008-04-03 | Method for tuning gross adjustment loop circuit of double-loop circuit frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101257304B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801416A (en) * | 2011-05-27 | 2012-11-28 | 联咏科技股份有限公司 | Phase lock loop circuit |
| CN102868399A (en) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method |
| CN102868395A (en) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and open loop frequency coarse tuning method |
| CN103095295A (en) * | 2012-12-28 | 2013-05-08 | 重庆西南集成电路设计有限责任公司 | Phase-locking frequency synthesizer, self-adaptation frequency calibration circuit and calibration method |
| CN103187970A (en) * | 2011-12-29 | 2013-07-03 | 国民技术股份有限公司 | Searching circuit through automatic frequency control and searching method thereof |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104052474A (en) * | 2014-06-03 | 2014-09-17 | 华为技术有限公司 | Frequency correction method and system of phase-locked loop |
| CN104135285A (en) * | 2014-08-07 | 2014-11-05 | 上海交通大学 | Frequency calibration circuit and method thereof |
| CN104796140A (en) * | 2014-01-20 | 2015-07-22 | 三星电子株式会社 | Digital phase-locked loop (DPLL), method of controlling DPLL, and ultra low power (ULP) transceiver using DPLL |
| CN106656173A (en) * | 2016-12-26 | 2017-05-10 | 上海迦美信芯通讯技术有限公司 | Frequency calibration circuit and frequency calibration method for oscillator |
| CN109104187A (en) * | 2018-09-14 | 2018-12-28 | 中国人民解放军陆军工程大学 | A kind of full-digital broadband frequency synthesizer |
| CN109194334A (en) * | 2018-11-12 | 2019-01-11 | 苏州云芯微电子科技有限公司 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
| WO2019127537A1 (en) * | 2017-12-29 | 2019-07-04 | 海能达通信股份有限公司 | Wideband low-phase-noise frequency synthesizer circuit and electronic device |
| CN110277992A (en) * | 2019-05-30 | 2019-09-24 | 芯创智（北京）微电子有限公司 | A kind of Semi-digital phaselocked loop of no bias current |
| CN111864915A (en) * | 2020-07-27 | 2020-10-30 | 北京理工大学 | Wireless charging system regulation and control method and system for realizing ZVS (zero voltage switching) in wide power range |
| CN117394851A (en) * | 2023-12-11 | 2024-01-12 | 西安航天民芯科技有限公司 | Oscillator control method and control system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE526070C2 (en) * | 2003-09-22 | 2005-06-28 | Impsys Digital Security Ab | Synchronizing method of communication session between e.g. enterprise and employees, involves performing handshake procedure to synchronize session counters of communication units by successively communicated signatures |
-
2008
- 2008-04-03 CN CN2008101033384A patent/CN101257304B/en not_active Expired - Fee Related
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801416A (en) * | 2011-05-27 | 2012-11-28 | 联咏科技股份有限公司 | Phase lock loop circuit |
| CN102801416B (en) * | 2011-05-27 | 2015-03-04 | 联咏科技股份有限公司 | Phase lock loop circuit |
| CN103187970A (en) * | 2011-12-29 | 2013-07-03 | 国民技术股份有限公司 | Searching circuit through automatic frequency control and searching method thereof |
| CN102868399B (en) * | 2012-10-11 | 2015-01-21 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method |
| CN102868395A (en) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and open loop frequency coarse tuning method |
| CN102868399A (en) * | 2012-10-11 | 2013-01-09 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and phase-locked loop loss lock detecting and adjusting method |
| CN102868395B (en) * | 2012-10-11 | 2015-12-16 | 广州润芯信息技术有限公司 | Phase-locked loop frequency integrator and open loop frequency coarse tuning method |
| CN103095295B (en) * | 2012-12-28 | 2015-09-23 | 重庆西南集成电路设计有限责任公司 | Frequency synthesizer of phase locking and adaptive frequency calibration circuit and calibration steps |
| CN103095295A (en) * | 2012-12-28 | 2013-05-08 | 重庆西南集成电路设计有限责任公司 | Phase-locking frequency synthesizer, self-adaptation frequency calibration circuit and calibration method |
| CN104796140A (en) * | 2014-01-20 | 2015-07-22 | 三星电子株式会社 | Digital phase-locked loop (DPLL), method of controlling DPLL, and ultra low power (ULP) transceiver using DPLL |
| CN104796140B8 (en) * | 2014-01-20 | 2019-07-12 | 三星电子株式会社 | Digital phase-locked loop DPLL, the method for controlling DPLL and the ultra low power transceiver using DPLL |
| CN104796140B (en) * | 2014-01-20 | 2019-05-10 | 三星电子株式会社 | Digital phase-locked loop DPLL, the method for controlling DPLL and the ultra low power transceiver using DPLL |
| CN104052474A (en) * | 2014-06-03 | 2014-09-17 | 华为技术有限公司 | Frequency correction method and system of phase-locked loop |
| US9455854B2 (en) | 2014-06-03 | 2016-09-27 | Huawei Technologies Co., Ltd. | Phase-locked loop frequency calibration method and system |
| CN104052474B (en) * | 2014-06-03 | 2017-03-15 | 华为技术有限公司 | A kind of phase-locked loop frequency bearing calibration and system |
| CN104038215B (en) * | 2014-06-13 | 2017-06-09 | 南京邮电大学 | A kind of ∑ △ fractional frequencies synthesizer automatic frequency calibration circuit |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104135285B (en) * | 2014-08-07 | 2017-02-15 | 上海交通大学 | Frequency calibration circuit and method thereof |
| CN104135285A (en) * | 2014-08-07 | 2014-11-05 | 上海交通大学 | Frequency calibration circuit and method thereof |
| CN106656173A (en) * | 2016-12-26 | 2017-05-10 | 上海迦美信芯通讯技术有限公司 | Frequency calibration circuit and frequency calibration method for oscillator |
| WO2019127537A1 (en) * | 2017-12-29 | 2019-07-04 | 海能达通信股份有限公司 | Wideband low-phase-noise frequency synthesizer circuit and electronic device |
| CN109104187A (en) * | 2018-09-14 | 2018-12-28 | 中国人民解放军陆军工程大学 | A kind of full-digital broadband frequency synthesizer |
| CN109104187B (en) * | 2018-09-14 | 2022-09-06 | 中国人民解放军陆军工程大学 | Full-digital broadband frequency synthesizer |
| CN109194334A (en) * | 2018-11-12 | 2019-01-11 | 苏州云芯微电子科技有限公司 | A kind of synchronization system applied to multi-channel high-speed digital analog converter |
| CN109194334B (en) * | 2018-11-12 | 2024-01-23 | 苏州云芯微电子科技有限公司 | Synchronous system applied to multichannel high-speed digital-to-analog converter |
| CN110277992A (en) * | 2019-05-30 | 2019-09-24 | 芯创智（北京）微电子有限公司 | A kind of Semi-digital phaselocked loop of no bias current |
| CN111864915A (en) * | 2020-07-27 | 2020-10-30 | 北京理工大学 | Wireless charging system regulation and control method and system for realizing ZVS (zero voltage switching) in wide power range |
| CN117394851A (en) * | 2023-12-11 | 2024-01-12 | 西安航天民芯科技有限公司 | Oscillator control method and control system |
| CN117394851B (en) * | 2023-12-11 | 2024-03-08 | 西安航天民芯科技有限公司 | Oscillator control method and control system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101257304B (en) | 2011-11-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101257304B (en) | Method for tuning gross adjustment loop circuit of double-loop circuit frequency synthesizer | |
| CN104135285B (en) | Frequency calibration circuit and method thereof | |
| CN101272143B (en) | Method and apparatus for frequency synthesizing | |
| CN1731681A (en) | Double-loop frequency synthesizer and method for tuning coarse loop | |
| CN113014254B (en) | Phase-locked loop circuit | |
| CN106209093B (en) | A kind of digital fractional frequency-division phase-locked loop structure | |
| JP5347534B2 (en) | Phase comparator, PLL circuit, and phase comparator control method | |
| CN102122953B (en) | Fast lock-in all-digital phase-locked loop with extended tracking range | |
| CN101409553B (en) | Phase delay line structure | |
| CN104038215B (en) | A kind of ∑ △ fractional frequencies synthesizer automatic frequency calibration circuit | |
| CN101807920A (en) | Self-adaptive frequency calibration frequency synthesizer | |
| CN106817126B (en) | High-precision digital frequency locking ring with wide output frequency range and high frequency locking speed | |
| CN102195645A (en) | Frequency synthesizer suitable for software radio system | |
| CN107911114B (en) | Broadband phase-locked loop with constant loop bandwidth | |
| CN105634480B (en) | Broadband charge pump phase-locked loop and dynamic threshold automatic frequency tuning method | |
| CN103746688A (en) | Automatic frequency-tuning phase-locked loop and automatic frequency-tuning method thereof | |
| CN104242930B (en) | A kind of frequency synthesizer applied to wireless transceiver system | |
| CN101123435B (en) | Method for adjusting oscillator in phase-locked loop and related frequency synthesizer | |
| CN103236841B (en) | Based on period ratio compared with switching regulator phase frequency detector and digital phase-locked loop | |
| CN102684685A (en) | phase locked loop and method thereof | |
| CN108063618A (en) | A kind of VCO auto-calibration circuits and method | |
| CN108923782A (en) | A kind of all-digital phase-locked loop and its quick phase-lock technique | |
| CN1269068A (en) | Charge pump steering systems and methods for loop filters of phase locked loops | |
| CN1169299C (en) | Phase-locked loop frequency synthesizer with digital coarse tuning loop | |
| CN101739373B (en) | System and method for calibrating serial bus time pulse frequency |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111109 Termination date: 20200403 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |