CN101257289A - Low-power consumption double-capacitance spread type CMOS oscillator - Google Patents

Abstract

The invention discloses a double-capacitance relax-expansion type CMOS oscillator, comprising a double-capacitance circuit, a RS trigger and a comparison circuit. The comparison circuit is composed of a comparator (Comp3) and a trigger D, the two output ends of the double-capacitance circuit are respectively connected with two in-phase input ends of a comparator, the inverting-phase input end of the comparator is connected with a reference voltage. The output end of the comparator is connected with the triggering edge of trigger D, the two output ends of trigger D are respectively connected with the R and S ends of RS trigger, the two output ends of RS trigger are respectively connected with two input ends of the double-capacitance circuit, and one output end of the trigger D is used as a main output end. Compared with prior art, the comparator (Comp3) and the comparator (Comp1 or Comp2) consumes same electric current, whereas, because all the tubes of the trigger D are in open-close state without the needs of biasing circuit, the comparator (Comp3) has less quiescent power drain than that of the comparator (Comp1 or Comp2).The invention has simple circuit structure, small occupation, low power consumption and high efficiency.

Description

A kind of low-power consumption double-capacitance spread type CMOS oscillator

Technical field

The invention belongs to switch power technology, be specially a kind of low-power consumption double-capacitance spread type CMOS oscillator, is a kind of CMOS oscillator of simple in structure, low-power consumption, is particularly useful in the portable set.

Background technology

Pierce circuit can be seen in many applications of electronic circuitry.Development of electronic technology as DC/DC converter, capacitive transducer, audio receiver and FM (frequency modulation(FM)) generator etc., just develops towards small size, highly integrated direction at present.As the requisite pierce circuit of these equipment, also promptly helping integrated direction more and developing towards taking still less chip area.The quality of pierce circuit directly has influence on the performance of switch power supply system, so also more and more higher to the requirement of pierce circuit.

Oscillator roughly can be divided into tuned oscillator and nonresonant oscillator two big classes.Tuned oscillator produces and is similar to sinusoidal wave output, and the output of nonresonant oscillator is generally square wave and triangular wave.Because the nonresonant oscillator does not need a lot of discrete components and is suitable in the integrated circuit very much.The nonresonant oscillator roughly has two kinds of constituted modes: a kind of is to utilize comparator to realize; Another kind is to utilize self-excitation mechanism to realize by the oscillating loop that CMOS constitutes.The spread type oscillator utilizes comparator to realize, it has good frequency linearity control ability.Low-power consumption, high efficiency are a trend of Switching Power Supply and portable set, so how reducing power consumption, raising the efficiency also is the challenge that the spread type oscillator is faced.

Fig. 1 has described a kind of circuit theory diagrams of typical double-capacitance spread type oscillator.Two condenser networks 1 are the output for the control comparison circuit 2 that replaces, and the frequency of oscillator is by constant-current source I ₀Determine.But the power consumption of the pierce circuit shown in this figure is bigger, and to comparing the comparator C omp in the circuit 2 ₁With comparator C omp ₂Require very highly, otherwise disorder on the logical sequence will occur.

Summary of the invention

The object of the present invention is to provide a kind of low-power consumption double-capacitance spread type CMOS oscillator, this oscillator structure is simple, can reduce power consumption, raises the efficiency.

Low-power consumption double-capacitance spread type CMOS oscillator provided by the invention comprises two condenser networks and rest-set flip-flop; It is characterized in that: it also comprises comparison circuit, and comparison circuit is by comparator C omp ₃Constitute with d type flip flop, two outputs of two condenser networks meet two in-phase input end IN of comparator respectively _P1, IN _P2, the inverting input IN of comparator _NMeet reference voltage V _Ref, the output C of comparator _OutConnect the triggering edge of d type flip flop, two output Q of d type flip flop ₁, Q ₁~ meet two input R, S of rest-set flip-flop, two output Q of rest-set flip-flop respectively ₂, Q ₂~ meet two inputs of two condenser networks, one of them output Q of d type flip flop respectively ₁~ as total output V _Out

Comparison circuit of the present invention has low-power consumption, high efficiency advantage compared with prior art.Comparison circuit among the present invention is made of a comparator and a d type flip flop, and in existing technology, comparison circuit is made of two comparators.Comparator C omp ₃Institute's consumed current and comparator C omp ₁And Comp ₂Institute's consumed current difference is little, but the d type flip flop in the comparison circuit of the present invention is a digital units, and the transistor of its inside all is to be operated on off state, and quiescent current is very little, and need not any biasing circuit, so power consumption is very low.And comparator C omp ₁With comparator C omp ₂In transistor all be to be operated in the saturation region, and need extra biasing circuit.In a word, double-capacitance spread type oscillator circuit structure novelty of the present invention, simple compared with prior art, greatly reduces power consumption, has improved efficient.

Description of drawings

Fig. 1 is the circuit theory diagrams of existing double-capacitance spread type oscillator;

Fig. 2 is the physical circuit figure of comparator among Fig. 1;

Fig. 3 is the circuit theory diagrams of double-capacitance spread type oscillator of the present invention;

Fig. 4 is the circuit diagram corresponding to first kind of execution mode of comparator among Fig. 3;

Fig. 5 is the circuit diagram of second kind of execution mode of comparator among corresponding and Fig. 3;

Fig. 6 is the circuit diagram corresponding to a kind of embodiment of Fig. 3.

Embodiment

The present invention is further detailed explanation below in conjunction with accompanying drawing and example.

As shown in Figure 3, double-capacitance spread type oscillator of the present invention is made of two condenser networks 1, comparison circuit 3 and rest-set flip-flop.Wherein, comparison circuit 3 is by comparator C omp ₃Constitute with d type flip flop, two outputs of two condenser networks 1 meet comparator C omp respectively ₃Two in-phase input end IN _P1And IN _P2, comparator C omp ₃Inverting input IN _NMeet reference voltage V _Ref, comparator C omp ₃Output C _OutConnect the triggering edge of d type flip flop, the output Q of d type flip flop ₁And Q ₁~ meet input R, the S of rest-set flip-flop, the output Q of rest-set flip-flop respectively ₂And Q ₂~ meet two inputs of two condenser networks 1, the output Q of d type flip flop respectively ₁~ as total output V _Out

In the foregoing circuit, the charge and discharge of the electric capacity in two condenser networks 1 are the output Q by rest-set flip-flop ₂And Q ₂~ control.Work as Q ₂Output high level " 1 ", Q ₂During ~ output low level " 0 ", NMOS manages MN ₁By, MN ₂Conducting, PMOS manages MP ₁Conducting, MP ₂End, at this moment, constant-current source I ₀By PMOS pipe MP ₁To capacitor C ₁Charge capacitor C ₂By NMOS pipe MN ₂Discharge.And the process of discharge is very fast, mainly depends on the breadth length ratio of discharge tube.Therefore, work as V ₂Drop to reference voltage V _RefWhen following, V ₁Can't rise to reference voltage V _RefSo, this time comparator C omp ₃Output low level " 0 ".Along with V ₁Continuation rise, work as V ₁Surpass reference voltage V _RefThe time, comparator C omp ₃The output high level " 1 " that will overturn, this is equivalent to rising edge of d type flip flop, makes the Q of d type flip flop ₁End upset output high level " 1 ", Q ₁~ end upset output low level, thereby rest-set flip-flop output Q ₂Upset is output as low level " 0 ", Q ₂~ upset is output as high level " 1 ".So NMOS manages MN ₁Conducting, MN ₂End capacitor C ₁By NMOS pipe MN ₁Discharge, constant-current source I ₀By PMOS pipe MP ₂To capacitor C ₂Charge.Thereby, voltage V ₁Begin to descend voltage V ₂Begin to rise.Because discharge process is very fast, so V ₁Drop to reference voltage V _RefWhen following, V ₂Can't rise to reference voltage V _RefSo, Comp ₃Upset is output as low level " 0 ", makes rest-set flip-flop output Q ₂Upset is output as high level " 1 ", Q once more ₂~ upset is output as low level " 0 " once more.So go round and begin again, will be at output V _OutThe place obtain one accurately duty ratio be 50% square wave.It should be noted that capacitance voltage V ₁(or V ₂) rise to reference voltage V _RefAfter, can't descend immediately, it can continue a period of time of rising because of propagation delay Td.Here said propagation delay Td is meant at capacitance voltage V ₁(or V ₂) reach reference voltage V _RefAnd trigger carries out the transition period, existing delay in conducting with between disconnecting.The generation of propagation delay Td be by electronic component itself intrinsic delay cause the comparator C omp in the comparison circuit 3 for example ₃The time that is spent when input signal is compared, be used for time that state exchange spent of d type flip flop and rest-set flip-flop, and PMOS pipe MP ₁And MP ₂With NMOS pipe MN ₁And MN ₂The time that is spent when changing etc. in conducting and between turn-offing.

As shown in Figure 4, the comparator C omp among the present invention ₃First kind implement circuit and comprise that biasing circuit 4, NMOS manage MN ₇, MN ₈, MN ₉, MN ₁₀And MN ₁₁, and PMOS pipe MP ₇, MP ₈And MP ₁₀Biasing circuit 4 comprises NMOS pipe MN ₁₁With PMOS pipe MP ₁₁NMOS manages MN ₁₁Grid, drain electrode and PMOS pipe MP ₁₁Drain electrode connect source ground altogether.PMOS manages MP ₁₁Grid meet the input offset voltage V of biasing circuit 4 _B, source electrode meets supply voltage V _DD, drain electrode meets NMOS pipe MN ₁₁Drain electrode.NMOS manages MN ₇, MN ₈And MN ₉Grid device Comp as a comparison respectively ₃Inverting input IN _N, in-phase input end IN _P1And IN _P2Their source electrode connects altogether, is connected on NMOS pipe MN ₁₂Drain electrode; NMOS manages MN ₇Drain electrode meet PMOS pipe MP ₇Drain electrode, NMOS manages MN ₈And MN ₉Drain electrode connect altogether, be connected on PMOS pipe MP ₈Drain electrode.PMOS manages MP ₇And MP ₈Grid and PMOS pipe MP ₇Drain electrode connect altogether, be connected on NMOS pipe MN ₇Drain electrode; Their source electrode connects altogether, is connected on supply voltage V _DDOn; PMOS manages MP ₈Drain electrode meet NMOS pipe MN ₈And MN ₉Drain electrode.PMOS manages MP ₁₀Grid meet PMOS pipe MP ₈Drain electrode, source electrode meets supply voltage V _DD, device Comp as a comparison drains ₃Output C _OutNMOS manages MN ₁₂And MN ₁₀Grid connect altogether, meet NMOS pipe MN ₁₁Grid; Their source electrode also connects altogether, ground connection; NMOS manages MN ₁₂Drain electrode meet NMOS pipe MN ₇Source electrode, NMOS manages MN ₁₀Drain electrode meet comparator C omp ₃Output C _Out

At comparator C omp shown in Figure 4 ₃In, biasing circuit 4 provides offset signal for other parts.Wherein, NMOS pipe MN ₁₂And MN ₁₀The image current that obtains from biasing circuit by current mirror action to be NMOS pipe MN exactly ₇, MN ₈, MN ₉And MN ₁₀Bias current is provided.Input IN _NBe comparator C omp ₃End of oppisite phase, input IN _P1And IN _P2Be comparator C omp ₃Two in-phase ends.PMOS manages MP ₇And MP ₈Be respectively the active load of comparator input pipe,, and simultaneously double-end signal be converted into single-ended signal, be transported to PMOS pipe MP with the output impedance of raising first order circuit ₁₀Grid.As in-phase end input signal IN _P1(or IN _P2) greater than inverting input signal IN _NThe time, output C _OutBe high level just; As in-phase end input signal IN _P1And IN _P2All less than inverting input signal IN _NThe time, output C _OutBe low level just.

As shown in Figure 5, the comparator circuit Comp among the present invention ₃Second kind implement circuit and comprise that biasing circuit 5, NMOS manage MN ₂₀, MN ₂₁, MN ₂₂, MN ₂₃, MN ₂₄And MN ₂₆, and PMOS pipe MP ₂₁, MP ₂₂, MP ₂₃And MP ₂₄Biasing circuit 5 comprises PMOS pipe MP ₂₅With NMOS pipe MN ₂₅PMOS manages MP ₂₅Source electrode meet supply voltage V _DD, grid meets comparator C omp ₃Input offset voltage V _B, drain electrode meets NMOS pipe MN ₂₅Drain electrode; NMOS manages MN ₂₅Source ground, grid, drain electrode and PMOS pipe MP ₂₅Drain electrode connect altogether.NMOS manages MN ₂₁, MN ₂₂And MN ₂₀Grid device Comp as a comparison respectively ₃Inverting input IN _N, in-phase input end IN _P1And IN _P2Their source electrode connects altogether, meets NMOS pipe MN ₂₆Drain electrode; NMOS manages MN ₂₁Drain electrode meet PMOS pipe MP ₂₁Drain electrode, NMOS manages MN ₂₂And MN ₂₀Drain electrode connect altogether, meet PMOS pipe MP ₂₂Drain electrode.NMOS manages MN ₂₆Grid meet NMOS pipe MN ₂₅Grid, source ground, drain electrode meets NMOS pipe MN ₂₁Source electrode.NMOS manages MN ₂₃And MN ₂₄Source electrode connect ground connection altogether; Grid and NMOS pipe MN ₂₃Drain electrode connect altogether, meet PMOS pipe MP ₂₃Drain electrode; NMOS manages MN ₂₄Drain electrode device Comp as a comparison ₃Output C _OutPMOS manages MP ₂₁Grid, drain electrode and PMOS pipe MP ₂₃Grid connect altogether, meet NMOS pipe MN ₂₁Drain electrode; Their source electrode connects altogether, meets supply voltage V _DDPMOS manages MP ₂₃Drain electrode meet NMOS pipe MN ₂₃Drain electrode.PMOS manages MP ₂₂Grid, drain electrode and PMOS pipe MP ₂₄Grid connect altogether, meet NMOS pipe MN ₂₂Drain electrode; Their source electrode also connects altogether, meets supply voltage V _DDPMOS manages MP ₂₄Drain electrode meet comparator C omp ₃Output C _Out

At comparator C omp shown in Figure 5 ₃In, the effect of biasing circuit 5 and comparator C omp shown in Figure 4 ₃In the effect of biasing circuit 4 the same.

Can obtain capacitor C from Fig. 3 ₁(or C ₂) charging interval be:

$t_r=\frac{V_H-V_L}{I_0}*C$

In the following formula, V _HRefer to capacitance voltage V ₁(or V ₂) high level, equal reference voltage V _RefV _LRefer to capacitance voltage V ₁(or V ₂) low level, equal 0; C refers to capacitor C ₁(equal C ₂) value; I ₀Refer to constant-current source I ₀Value.Therefore, the output frequency of oscillator:

$f=\frac{1}{2*(t_r+t_d)}$

Wherein, t _rBe the charging interval of electric capacity, t _dBe the propagation delay time.

Comparison diagram 1 and Fig. 3 as can be seen, in the double-capacitance spread type pierce circuit principle shown in Figure 3, a comparator C omp in the comparison circuit 3 ₃Two comparator C omp in the comparison circuit 2 among Fig. 1 have been replaced with d type flip flop ₁And Comp ₂The shared chip area of comparison circuit 2 and comparison circuit 3 is about the same.From Fig. 2 and Fig. 4 as can be seen, comparator C omp ₃Only than comparator Comp ₁(or Comp ₂) the NMOS pipe in many places, so, comparator C omp ₁(or Comp ₂) and comparator C omp ₃Institute's consumed current almost is the same.But the d type flip flop in the comparison circuit 3 is a simple digital circuit, and its all metal-oxide-semiconductors all are operated on off state, and need not any biasing circuit, so its quiescent dissipation is very little.And comparator C omp ₁(or Comp ₂) in metal-oxide-semiconductor all must operate at the saturation region, all need the biasing circuit could operate as normal separately.So comparator C omp ₁(or Comp ₂) power consumption big more a lot of than d type flip flop.

In a word, compared to Figure 1 Fig. 3 though increased a d type flip flop circuit, has reduced by a comparator circuit, and this makes Fig. 3 take under chip area and Fig. 1 situation about the same, has reduced power consumption greatly and has improved efficient.

For example the present invention is made further detail analysis below.

As shown in Figure 6, the constant-current source circuit in two condenser networks 1 comprises PMOS pipe MP ₁₂, MP ₁₃And MP ₁₄, and fixing bias current sources I ₁Except constant-current source circuit, two condenser networks 1 also comprise PMOS pipe MP ₁And MP ₂, NMOS manages MN ₁And MN ₂, and capacitor C ₁And C ₂Bias current sources I ₁Negativing ending grounding, positive termination PMOS pipe MP ₁₂Drain electrode.PMOS manages MP ₁₂, MP ₁₃And MP ₁₄Source electrode connect altogether, meet supply voltage V _INGrid also connects altogether, meets PMOS pipe MP ₁₂Drain electrode; PMOS manages MP ₁₃And MP ₁₄Drain electrode meet PMOS pipe MP respectively ₁Source electrode and PMOS pipe MP ₂Source electrode.NMOS manages MN ₁And MN ₂Source electrode connect ground connection altogether; Their drain electrode meets PMOS pipe MP respectively ₁Drain electrode and MP ₂Drain electrode, grid meets the Q of rest-set flip-flop respectively ₂~ output and Q ₂Output.PMOS manages MP ₁Grid meet NMOS pipe MN ₁Grid, drain electrode meet NMOS pipe MN ₁Drain electrode, source electrode meet PMOS pipe MP ₁₃Drain electrode.PMOS manages MP ₂Grid meet NMOS pipe MN ₂Grid, drain electrode meet NMOS pipe MN ₂Drain electrode, source electrode meet PMOS pipe MP ₁₄Drain electrode.Capacitor C ₁And C ₂Bottom crown connect ground connection altogether; Top crown meets NMOS pipe MN respectively ₈And MN ₉Grid.

Comparator C omp in the comparison circuit 3 ₃Formation identical with structure shown in Figure 4.Wherein, input signal V _BAnd V _RefIt all is the bias voltage that inserts from other module.

The circuit structure of the d type flip flop in the comparison circuit 3 can be realized with existing typical circuit structure.The clock input signal CP that its rising edge triggers meets comparator C omp ₃Output; Input D and the output Q of self ₁~ connect altogether, meet the output signal V of oscillator _OutOutput Q ₁Meet the input R of rest-set flip-flop.

The circuit structure of rest-set flip-flop can be realized with existing typical circuit structure.Its input R meets the Q of d type flip flop in the comparison circuit 3 ₁Output; Input S meets the output Q of d type flip flop in the comparison circuit 3 ₁~; Output Q ₂Meet NMOS pipe MN ₂Grid; Output Q ₂~ meet NMOS to manage MN ₁Grid.

PMOS pipe MP in two condenser networks 1 ₁₃And MP ₁₄Obtain constant electric current I by current mirror ₀, give capacitor C respectively ₁And C ₂Charging.Charging current is B*I1, and wherein, B is a constant, and it represents PMOS pipe MP ₁₃(or MP ₁₄) manage MP with PMOS ₁₂Breadth length ratio, I ₁The bias current that expression is fixing.If the initial condition Q of rest-set flip-flop ₂Be high level, Q ₂~ be low level, then NMOS manages MN ₁By, MN ₂Conducting, PMOS manages MP ₁And MP ₁₃Conducting, MP ₂And MP ₁₄End.Capacitor C ₁Charging, C ₁Discharge.Because discharge process is very fast, so, V worked as ₂Drop to reference voltage V _RefWhen following, V ₁Can't rise to V _RefSo, this time comparator C omp ₃Still output low level.Along with V ₁Continuation rise, will reach V _Ref, at this moment, comparator C omp ₃Will overturn the output high level.The input signal CP of d type flip flop is by low transition during to high level, output Q ₁And Q ₁~ all can overturn, export high level and low level respectively.At this moment, the output signal V of oscillator _OutBe low level also by original high level upset.So, the output Q of rest-set flip-flop ₂And Q ₂~ will and then overturn difference output low level and high level.This makes NMOS manage MN ₁Conducting, MN ₂End.Capacitor C ₁Discharge, C ₂Charging.Because discharge process is very fast, so V ₁Drop to reference voltage V _RefThe time, V ₂Can't rise to V _Ref, this moment comparator C omp ₃Can the upset output low level.Work as V ₂Rise to reference voltage V _RefThe time, comparator C omp ₃The output high level will overturn.Make the output Q of d type flip flop ₁And Q ₁~ upset simultaneously, output low level and high level respectively.At this moment, oscillator output V _OutUpset is high level once more.So, the output Q of rest-set flip-flop ₂And Q ₂~ also be turned into high level and low level once more simultaneously.This gets back to initial condition again, so repeatedly, just can obtain duty ratio and be 50% output square wave.

In existing double-capacitance spread type oscillator, if because the imbalance of circuit or technology causes comparator C omp ₁With comparator C omp ₂Can not well mate, the output of these two comparators just can not be overturn simultaneously so, and two inputs of rest-set flip-flop just might keep moment with a kind of level " 1 " or " 0 ", and this is that double-capacitance spread type oscillator institute is unallowed.Therefore, in the existing technology, to comparator Comp ₁And Comp ₂The precision of circuit and the matching degree between them require very high.And in comparison circuit of the present invention, because a comparator C omp is only arranged ₃So, just do not have the matching problem.This has just reduced comparator C omp ₃The difficulty of design, thus can utilize simple circuit configuration to reduce its power consumption.In comparison circuit, IN _NDevice Comp as a comparison ₃Inverting input, IN _P1And IN _P2Difference is device Comp as a comparison ₃In-phase input end; C _OutBe comparator C omp ₃Output.As comparator C omp ₃In-phase input end signal IN _P1And IN _P2All less than inverting input signal IN _NThe time, comparator C omp ₃Output V _OutBe low level just; As in-phase input end signal IN _P1(or IN _P2) greater than inverting input signal IN _NThe time, comparator C omp ₃Output C _OutBe high level just.As comparator C omp ₃Output V _OutWhen being high level, will give rising edge signal of CP input of d type flip flop, make two output Q of d type flip flop by low transition ₁And Q ₁~ overturn.In addition, the d type flip flop in the double-capacitance spread type oscillator of the present invention in the comparison circuit is an existing typical circuit, and its quiescent dissipation is almost nil.

Claims (3)

1, a kind of low-power consumption double-capacitance spread type CMOS oscillator comprises two condenser networks (1) and rest-set flip-flop; It is characterized in that: it also comprises comparison circuit (3), and comparison circuit (3) is made of comparator and d type flip flop, and two outputs of two condenser networks (1) meet two in-phase input end IN of comparator respectively _P1, IN _P2, the inverting input IN of comparator _NMeet reference voltage V _Ref, the output C of comparator _OutConnect the triggering edge of d type flip flop, two output Q of d type flip flop ₁, Q ₁~ meet two input R, S of rest-set flip-flop, two output Q of rest-set flip-flop respectively ₂, Q ₂~ meet two inputs of two condenser networks (1), one of them output Q of d type flip flop respectively ₁~ as total output V _Out

2, low-power consumption double-capacitance spread type CMOS oscillator according to claim 1 is characterized in that: described comparator comprises that biasing circuit (4), NMOS manage MN ₇, MN ₈, MN ₉, MN ₁₀And MN ₁₂, and PMOS pipe MP ₇, MP ₈And MP ₁₀

Biasing circuit 4 comprises NMOS pipe MN ₁₁With PMOS pipe MP ₁₁NMOS manages MN ₁₁Grid, drain electrode and PMOS pipe MP ₁₁Drain electrode connect source ground altogether; PMOS manages MP ₁₁Grid meet the input offset voltage V of comparator _B, source electrode meets supply voltage V _DD, drain electrode meets NMOS pipe MN ₁₁Drain electrode;

NMOS manages MN ₇, MN ₈And MN ₉The grid inverting input IN of device as a comparison respectively _N, in-phase input end IN _P1And IN _P2Their source electrode connects altogether, is connected on NMOS pipe MN ₁₂Drain electrode; NMOS manages MN ₇Drain electrode meet PMOS pipe MP ₇Drain electrode, NMOS manages MN ₈And MN ₉Drain electrode connect altogether, be connected on PMOS pipe MP ₈Drain electrode; PMOS manages MP ₇And MP ₈Grid and PMOS pipe MP ₇Drain electrode connect altogether, be connected on NMOS pipe MN ₇Drain electrode; Their source electrode connects altogether, is connected on supply voltage V _DDOn; PMOS manages MP ₈Drain electrode meet NMOS pipe MN ₈And MN ₉Drain electrode; PMOS manages MP ₁₀Grid meet PMOS pipe MP ₈Drain electrode, source electrode meets supply voltage V _DD, the output C of device as a comparison drains _OutNMOS manages MN ₁₂And MN ₁₀Grid connect altogether, meet NMOS pipe MN ₁₁Grid; Their source electrode also connects back ground connection altogether; NMOS manages MN ₁₂Drain electrode meet NMOS pipe MN ₇Source electrode, NMOS manages MN ₁₀Drain electrode meet the output C of comparator _Out

3, low-power consumption double-capacitance spread type CMOS oscillator according to claim 1, it is characterized in that: comparator circuit comprises biasing circuit ₅, NMOS manages MN ₂₀, MN ₂₁, MN ₂₂, MN ₂₃, MN ₂₄And MN ₂₆, and PMOS pipe MP ₂₁, MP ₂₂, MP ₂₃And MP ₂₄Biasing circuit (5) comprises PMOS pipe MP ₂₅With NMOS pipe MN ₂₅PMOS manages MP ₂₅Source electrode meet supply voltage V _DD, grid meets the input offset voltage V of comparator _B, drain electrode meets NMOS pipe MN ₂₅Drain electrode; NMOS manages MN ₂₅Source ground, grid, drain electrode and PMOS pipe MP ₂₅Drain electrode connect altogether; NMOS manages MN ₂₁, MN ₂₂And MN ₂₀The grid inverting input IN of device as a comparison respectively _N, in-phase input end IN _P1And IN _P2Their source electrode connects altogether, meets NMOS pipe MN ₂₆Drain electrode; NMOS manages MN ₂₁Drain electrode meet PMOS pipe MP ₂₁Drain electrode, NMOS manages MN ₂₂And MN ₂₀Drain electrode connect altogether, meet PMOS pipe MP ₂₂Drain electrode; NMOS manages MN ₂₆Grid meet NMOS pipe MN ₂₅Grid, source ground, drain electrode meets NMOS pipe MN ₂₁Source electrode; NMOS manages MN ₂₃And MN ₂₄Source electrode connect ground connection altogether; Grid and NMOS pipe MN ₂₃Drain electrode connect altogether, meet PMOS pipe MP ₂₃Drain electrode; NMOS manages MN ₂₄The drain electrode output C of device as a comparison _OutPMOS manages MP ₂₁Grid, drain electrode and PMOS pipe MP ₂₃Grid connect altogether, meet NMOS pipe MN ₂₁Drain electrode; Their source electrode connects altogether, meets supply voltage V _DDPMOS manages MP ₂₃Drain electrode meet NMOS pipe MN ₂₃Drain electrode; PMOS manages MP ₂₂Grid, drain electrode and PMOS pipe MP ₂₄Grid connect altogether, meet NMOS pipe MN ₂₂Drain electrode; Their source electrode also connects altogether, meets supply voltage V _DDPMOS manages MP ₂₄Drain electrode meet the output C of comparator _Out

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