CN101228697B - Gain error correction in an analog-to-digital converter - Google Patents

Abstract

An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance means and switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Description

Error correction circuit and use its analog to digital converter

Related application

The application requires to be filed on June 16th, 2005 and transfers its assignee's the U.S. Provisional Application No.60/691 that is entitled as " Gain and OffsetError Correction Methods (gain and biased error bearing calibration) ", No. 964 priority, this provisional application clearly is included in this by quoting.

Technical field

The disclosure relates generally to gain error correction.In particular, the disclosure relates to such as the gain error correction in the analog to digital converter discrete time circuit such as (ADC).

Background technology

Usually in any ADC, locate to exist system's biased error and locate to exist gain error in full-code (full-scale-code) at scale zero sign indicating number (zero-code).Because these errors are systematic, they can be calibrated after through the test of the first round before the ADC large-scale production.

These errors are being to comprise the look-up table of correcting code or by using relevant double sampling (double-sampling) to proofread and correct by use in the past.These methods relate to more circuit and require higher power.Under ADC was used in such as the situation in the less powered battery environment such as radio telephone, PDA or laptop computer, circuit minimized and Power Cutback were more important with the battery maintenance life-span.

Correspondingly, it will be favourable providing a kind of system that is used for the improvement of corrects bias error.

Summary of the invention

In a specific embodiment, the system and method for correct for gain error can comprise the backplane voltage of offset capacitor device.

In a particular embodiment, provide a kind of error correction circuit that uses with analog to digital converter, having comprised: corrective capacity device and the switching device that is coupled to this corrective capacity device.This switching device is coupled to ground connection and a plurality of reference voltage and is configured to the base plate of described corrective capacity device is coupled to ground connection and is coupled to one of a plurality of reference voltages in the maintenance stage of described ADC in the sample phase of described ADC.

The advantage of one or more embodiment disclosed herein can be included in the actual gain error correction under the situation of no high power consumption.

Comprise accompanying drawing summary in reading, specify and the whole application of following chapters and sections such as claim after, others of the present disclosure, advantage and feature will be conspicuous.

The accompanying drawing summary

Below in conjunction with specifying that accompanying drawing is understood, the each side of embodiment described here and attendant advantages will become and be more prone to apparent by reference, in the accompanying drawing:

Fig. 1 is the sketch plan of an exemplary successive approximation register ADC (SAR-ADC) of prior art;

Fig. 2 shows the diagrammatic sketch of exemplary operation of the SAR-ADC of prior art;

Fig. 3 is a diagrammatic sketch of having described the exemplary biased sum of errors gain error that SAR-ADC introduced of prior art;

Fig. 4 shows the diagrammatic sketch of an exemplary embodiment of gain error correction;

Fig. 5 shows the diagrammatic sketch of the exemplary embodiment of the ADC with gain error correction among Fig. 4.

Specifically describe

Fig. 1 shows the SAR-ADC 100 of prior art.ADC 100 samples sample-hold circuit 120 by input multiplexer (mux) 110 with analog input signal.Comparison between the input signal of carrying out reference voltage (from digital to analog converter (DAC) 170) by comparator 130 then and being sampled.The output of comparator 130 is transferred to latch 140, and the latter offers latched signal the successive approximation register 160 of a part that can be used as digital interface 150.The digit order number that digital interface 150 outputs obtain.This comparative result of device 130 based on the comparison, DAC 170 have generated a new reference voltage and have finished for the second time relatively to generate second position.This operation proceeds to always and obtains all required positions.Digital interface 150 is selected signal 151 and is provided inhibit signal 152 to control this operation to sample-hold circuit 120 by providing to input multiplexer 110.Digital interface 150 also can comprise the successive approximation register 160 that generates comparison signal 161, comparator clock 162 and latch clock 163.Comparison signal is fed to DAC 170 (being used for providing reference voltage to comparator 130).Comparator clock 162 is used for comparator 130 timings and latch clock 163 is used for latch 140 regularly.

Input voltage and the reference voltage that is generated by the SAR-ADC among Fig. 1 are illustrated in Fig. 2.The input voltage of being sampled is by solid line 200 expressions, and dotted line 210 expression reference voltages.As shown in Figure 2, by begin to extract the position up to obtaining all positions from highest significant position to the SAR-ADC of order from Fig. 1 of least significant bit.As represented in the figure, VDD is full scale (full-scale) voltage and Vgnd is scale zero (zero-scale) voltage.

With reference to Fig. 1, the various key elements that can directly cause biasing and gain error are arranged, such as (comparator 130, DAC170 and sample-hold circuit 120).The electric charge that the root of error can be classified as mismatch, sample-hold circuit 120 switches of comparator 130 injects, 120 benchmark coupling (recalcitrating (kickback) noise) and the parasitic antenna on the DAC 170 from DAC 170 to sample-hold circuit.These errors are systematic and can calibrate afterwards at characterized systematically (characterization).

Represented biasing and gain error diagrammatic sketch among Fig. 3 to an example of the influence of sign indicating number through changing.As shown in the figure, the ideal output of lines 300 expressions ADC under the sign indicating number coupling input signal situation of conversion.Biased error causes this desirable lines skew, and this is by lines 310 expressions.Represented as lines 320, gain error causes the slope variation of lines.Can there be in this error of two types one or both.

Referring now to Fig. 4, show an exemplary embodiment of gain error correction 430.The gain error correction 430 of Fig. 4 has been offset the backplane voltage of some capacitors so that gain error correction to be provided.

Sample-hold circuit 420 comprises sampling-maintenance stage switch 422 and sampling-maintenance capacitor 425 (Csh).Other assembly of sample-hold circuit 420 is not shown.The output of sample-hold circuit 420 is fed to error correction circuit 430.For example can be sampling-maintained switch 422 control sampling processes of cmos switch.Basically, when Φ 1 was effective high state (active high), sampling-maintenance stage switch 422 worked (closure) and input signal is transferred to the top board of the calibrating capacitor 435 of sampling-maintenance capacitor 425 and error correction circuit 430.When stage switch 422 was opened, sampling process finished and begins to keep operation.Sampling-maintenance capacitor 425 can be by the capacitor (Cu) of a plurality of unit-sized, and for example 200 Cu form.

Gain error correction 430 comprises for example a plurality of calibrating capacitor 435a-c (Ccorr).The base plate of each is electrically coupled to the corresponding battle array of the first switch 440a-c that is coupled to ground connection and the serial battle array that is coupled to the second switch 445a-c of the 3rd switch 450a-c among these calibrating capacitors 435a-c.Among the 3rd switch 450a-c each is coupled to resistor network 460 so that different reference voltages to be provided at difference again.For example, the 3rd switch 450a can be coupling between resistor 470a and the 470b so that the first reference voltage V ref1 to be provided.The 3rd switch 450b can be coupling between resistor 470b and the 470c so that the second reference voltage V ref2 to be provided.Similarly, the 3rd switch 450c can be coupling between resistor 470d and the 470e so that the 3rd reference voltage V ref3 to be provided.

In an exemplary embodiment, applied reference voltage is activated for high state so that do not make the linear deterioration of this ADC based on whom by binary coding and the 3rd switch.For example, the base plate of calibrating capacitor 435a-c is connected to Vgnd (when Φ 1 is activated for effective high state and the first switch 440a) during the sampling operation.Keeping operating period (when Φ 2 is effective high state), second switch 445a-c is activated and one of the 3rd switch 450a-c is activated so that the backplane voltage of corresponding calibrating capacitor 435a-c is displaced to corresponding reference voltage.

Suppose that the maximum amplitude of the error that will proofread and correct is Ccorr* (Vref3+Vref2+Vref1)/(Csh+3*Ccorr) from 10 of ADC outputs.Obviously, Vref3 is Vdd/2, and Vref2 is Vdd/4, and Vref1 is Vdd/8.And,, this side-play amount easily control according to position (for example, b10, b9 and b8) so can passing through these the 3rd switches 450a-c owing between the base plate of calibrating capacitor 435a-c and reference voltage V ref1-3, the 3rd switch 450a-c is arranged.This allows the correction near the higher degree of full-code (full-code).For example,

When b10=b9=b8=1, V correction _ maximum=Vdd*7/8*Cu/ (203Cu)=11.2mV.

As b10=b9=0 and during b8=1, V correction _ maximum=Vdd*1/8*Cu/ (203Cu)=1.6mV.

Fig. 5 shows the exemplary embodiment of the ADC with error correction circuit among Fig. 4.The element of ADC 100 is similar among the element of ADC 500 and Fig. 1, yet comprises error correction circuit 430 between sample-hold circuit 120 and comparator 140.

Use the configuration of disclosed structure here, system and method described here provides the method for proofreading and correct gain error in the ADC.The needs of gain error correction have been avoided thus.

Use so that any technical staff of this area can utilize or use the disclosure describing before the disclosed embodiments to be provided.To it will be readily apparent to those skilled in the art that, and universal principle described here may be used on other embodiment and can not deviate from spirit of the present disclosure and scope to the various modifications of these embodiment.Thus, the disclosure is not intended to be limited to embodiment shown here, and consistent with the wideest scope according to principle and novel feature as defined by the appended claims.

Claims (4)

1. error correction circuit that can use with analog to digital converter comprises:

A plurality of calibrating capacitors of parallel arranged; And

A plurality of switch arrays, each in described a plurality of switch arrays is coupled to calibrating capacitor separately, and each switch arrays comprises

First switch, the sample phase that is coupled to ground and is provided in described analog to digital converter works,

Second switch, the maintenance stage that is arranged in described analog to digital converter works, and

The 3rd switch is coupled to reference voltage and described second switch, and the specific carry-out bit that is provided in described analog to digital converter is to work between high period;

Wherein said first switch and the described second and the 3rd switch parallel arranged.

2. error correction circuit as claimed in claim 1 is characterized in that, also comprises:

A plurality of resistors, described a plurality of resistor serial arrangement are to provide a plurality of reference voltages to described a plurality of switch arrays.

3. analog to digital converter comprises:

Sample-hold circuit;

Comparator; And

Be included in the error correction circuit between described sample-hold circuit and the described comparator, described error correction circuit comprises

A plurality of calibrating capacitors of parallel arranged; And

A plurality of switch arrays, each in described a plurality of switch arrays is coupled to calibrating capacitor separately, and each switch arrays comprises

First switch, the sample phase that is coupled to ground and is provided in described analog to digital converter works,

Second switch, the maintenance stage that is arranged in described analog to digital converter works, and

The 3rd switch is coupled to reference voltage and described second switch, and the specific carry-out bit that is provided in described analog to digital converter is to work between high period;

Wherein said first switch and the described second and the 3rd switch parallel arranged.

4. analog to digital converter as claimed in claim 3 is characterized in that, described error correction circuit also comprises:

A plurality of resistors, described a plurality of resistor serial arrangement are to provide a plurality of reference voltages to described a plurality of switch arrays.

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